Functions that access the ITM debug interface. More...

Variables
uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:7

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::IT:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:7

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::IT:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::SFPA:1

uint32_t CONTROL_Type::_reserved1:28

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::SFPA:1

uint32_t CONTROL_Type::_reserved1:28

}	CONTROL_Type::b

volatile uint8_t	NVIC_Type::IPR [496U]

uint32_t	NVIC_Type::RESERVED6 [580U]

volatile uint32_t	NVIC_Type::STIR

volatile uint32_t	SCB_Type::VTOR

volatile uint8_t	SCB_Type::SHPR [12U]

volatile uint32_t	SCB_Type::CFSR

volatile uint32_t	SCB_Type::HFSR

volatile uint32_t	SCB_Type::DFSR

volatile uint32_t	SCB_Type::MMFAR

volatile uint32_t	SCB_Type::BFAR

volatile uint32_t	SCB_Type::AFSR

const volatile uint32_t	SCB_Type::ID_PFR [2U]

const volatile uint32_t	SCB_Type::ID_DFR

const volatile uint32_t	SCB_Type::ID_ADR

const volatile uint32_t	SCB_Type::ID_MMFR [4U]

const volatile uint32_t	SCB_Type::ID_ISAR [6U]

const volatile uint32_t	SCB_Type::CLIDR

const volatile uint32_t	SCB_Type::CTR

const volatile uint32_t	SCB_Type::CCSIDR

volatile uint32_t	SCB_Type::CSSELR

volatile uint32_t	SCB_Type::CPACR

volatile uint32_t	SCB_Type::NSACR

uint32_t	SCB_Type::RESERVED3 [92U]

volatile uint32_t	SCB_Type::STIR

uint32_t	SCB_Type::RESERVED4 [15U]

const volatile uint32_t	SCB_Type::MVFR0

const volatile uint32_t	SCB_Type::MVFR1

const volatile uint32_t	SCB_Type::MVFR2

uint32_t	SCB_Type::RESERVED5 [1U]

volatile uint32_t	SCB_Type::ICIALLU

uint32_t	SCB_Type::RESERVED6 [1U]

volatile uint32_t	SCB_Type::ICIMVAU

volatile uint32_t	SCB_Type::DCIMVAC

volatile uint32_t	SCB_Type::DCISW

volatile uint32_t	SCB_Type::DCCMVAU

volatile uint32_t	SCB_Type::DCCMVAC

volatile uint32_t	SCB_Type::DCCSW

volatile uint32_t	SCB_Type::DCCIMVAC

volatile uint32_t	SCB_Type::DCCISW

uint32_t	SCB_Type::RESERVED7 [6U]

volatile uint32_t	SCB_Type::ITCMCR

volatile uint32_t	SCB_Type::DTCMCR

volatile uint32_t	SCB_Type::AHBPCR

volatile uint32_t	SCB_Type::CACR

volatile uint32_t	SCB_Type::AHBSCR

uint32_t	SCB_Type::RESERVED8 [1U]

volatile uint32_t	SCB_Type::ABFSR

uint32_t	SCnSCB_Type::RESERVED0 [1U]

const volatile uint32_t	SCnSCB_Type::ICTR

volatile uint32_t	SCnSCB_Type::ACTLR

volatile uint32_t	SCnSCB_Type::CPPWR

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

uint32_t	ITM_Type::RESERVED0 [864U]

volatile uint32_t	ITM_Type::TER

uint32_t	ITM_Type::RESERVED1 [15U]

volatile uint32_t	ITM_Type::TPR

uint32_t	ITM_Type::RESERVED2 [15U]

volatile uint32_t	ITM_Type::TCR

uint32_t	ITM_Type::RESERVED3 [29U]

volatile uint32_t	ITM_Type::IWR

const volatile uint32_t	ITM_Type::IRR

volatile uint32_t	ITM_Type::IMCR

uint32_t	ITM_Type::RESERVED4 [43U]

volatile uint32_t	ITM_Type::LAR

const volatile uint32_t	ITM_Type::LSR

uint32_t	ITM_Type::RESERVED5 [1U]

const volatile uint32_t	ITM_Type::DEVARCH

uint32_t	ITM_Type::RESERVED6 [4U]

const volatile uint32_t	ITM_Type::PID4

const volatile uint32_t	ITM_Type::PID5

const volatile uint32_t	ITM_Type::PID6

const volatile uint32_t	ITM_Type::PID7

const volatile uint32_t	ITM_Type::PID0

const volatile uint32_t	ITM_Type::PID1

const volatile uint32_t	ITM_Type::PID2

const volatile uint32_t	ITM_Type::PID3

const volatile uint32_t	ITM_Type::CID0

const volatile uint32_t	ITM_Type::CID1

const volatile uint32_t	ITM_Type::CID2

const volatile uint32_t	ITM_Type::CID3

volatile uint32_t	DWT_Type::CYCCNT

volatile uint32_t	DWT_Type::CPICNT

volatile uint32_t	DWT_Type::EXCCNT

volatile uint32_t	DWT_Type::SLEEPCNT

volatile uint32_t	DWT_Type::LSUCNT

volatile uint32_t	DWT_Type::FOLDCNT

uint32_t	DWT_Type::RESERVED32 [934U]

const volatile uint32_t	DWT_Type::LSR

uint32_t	DWT_Type::RESERVED33 [1U]

const volatile uint32_t	DWT_Type::DEVARCH

uint32_t	FPU_Type::RESERVED0 [1U]

volatile uint32_t	FPU_Type::FPCCR

volatile uint32_t	FPU_Type::FPCAR

volatile uint32_t	FPU_Type::FPDSCR

const volatile uint32_t	FPU_Type::MVFR0

const volatile uint32_t	FPU_Type::MVFR1

uint32_t APSR_Type::_reserved0:27

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:27

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::_reserved1:8

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::_reserved1:8

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

volatile uint8_t	NVIC_Type::IP [240U]

volatile uint8_t	SCB_Type::SHP [12U]

const volatile uint32_t	SCB_Type::PFR [2U]

const volatile uint32_t	SCB_Type::DFR

const volatile uint32_t	SCB_Type::ADR

const volatile uint32_t	SCB_Type::MMFR [4U]

const volatile uint32_t	SCB_Type::ISAR [5U]

uint32_t	SCnSCB_Type::RESERVED1 [1U]

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

volatile uint32_t	DWT_Type::MASK0

volatile uint32_t	DWT_Type::MASK1

volatile uint32_t	DWT_Type::MASK2

volatile uint32_t	DWT_Type::MASK3

const volatile uint32_t	TPI_Type::FSCR

const volatile uint32_t	TPI_Type::FIFO0

const volatile uint32_t	TPI_Type::ITATBCTR2

const volatile uint32_t	TPI_Type::FIFO1

uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:7

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::IT:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:7

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::IT:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::SFPA:1

uint32_t CONTROL_Type::_reserved1:28

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::SFPA:1

uint32_t CONTROL_Type::_reserved1:28

}	CONTROL_Type::b

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::_reserved0:29

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::_reserved0:29

}	CONTROL_Type::b

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:16

uint32_t APSR_Type::GE:4

uint32_t APSR_Type::_reserved1:7

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::GE:4

uint32_t xPSR_Type::_reserved1:4

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::_reserved0:29

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::FPCA:1

uint32_t CONTROL_Type::_reserved0:29

}	CONTROL_Type::b

const volatile uint32_t	SCB_Type::ID_AFR

const volatile uint32_t	SCB_Type::ID_MFR [4U]

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

volatile uint32_t	DWT_Type::LAR

const volatile uint32_t	FPU_Type::MVFR2

uint32_t APSR_Type::_reserved0:27

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:27

uint32_t APSR_Type::Q:1

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::_reserved1:8

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:1

uint32_t xPSR_Type::ICI_IT_1:6

uint32_t xPSR_Type::_reserved1:8

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::ICI_IT_2:2

uint32_t xPSR_Type::Q:1

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

union {
volatile uint8_t ITM_Type::u8

volatile uint16_t ITM_Type::u16

volatile uint32_t ITM_Type::u32

}	ITM_Type::PORT [32U]

volatile int32_t	ITM_RxBuffer

__STATIC_INLINE uint32_t	ITM_SendChar (uint32_t ch)
	ITM Send Character. More...

__STATIC_INLINE int32_t	ITM_ReceiveChar (void)
	ITM Receive Character. More...

__STATIC_INLINE int32_t	ITM_CheckChar (void)
	ITM Check Character. More...

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

volatile int32_t	ITM_RxBuffer

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

volatile int32_t	ITM_RxBuffer

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

volatile int32_t	ITM_RxBuffer

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

volatile int32_t	ITM_RxBuffer

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

volatile int32_t	ITM_RxBuffer

#define	ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Detailed Description

Functions that access the ITM debug interface.

Macro Definition Documentation

◆ ITM_RXBUFFER_EMPTY [1/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 1839 of file core_sc300.h.

◆ ITM_RXBUFFER_EMPTY [2/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 1865 of file core_cm3.h.

◆ ITM_RXBUFFER_EMPTY [3/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2053 of file core_cm4.h.

◆ ITM_RXBUFFER_EMPTY [4/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2595 of file core_cm7.h.

◆ ITM_RXBUFFER_EMPTY [5/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2851 of file core_armv8mml.h.

◆ ITM_RXBUFFER_EMPTY [6/6]

#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U)

Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2926 of file core_cm33.h.

Function Documentation

◆ ITM_CheckChar()

__STATIC_INLINE int32_t ITM_CheckChar ( void )

ITM Check Character.

Checks whether a character is pending for reading in the variable ITM_RxBuffer.

Returns: 0 No character available.; 1 Character available.

< Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2903 of file core_armv8mml.h.

 {
  
   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
   {
     return (0);                              /* no character available */
   }
   else
   {
     return (1);                              /*    character available */
   }
 }

◆ ITM_ReceiveChar()

__STATIC_INLINE int32_t ITM_ReceiveChar ( void )

ITM Receive Character.

Inputs a character via the external variable ITM_RxBuffer.

Returns: Received character.; -1 No character pending.

< Value identifying ITM_RxBuffer is ready for next character.

Definition at line 2883 of file core_armv8mml.h.

 {
   int32_t ch = -1;                           /* no character available */
  
   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
   {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }
  
   return (ch);
 }

◆ ITM_SendChar()

__STATIC_INLINE uint32_t ITM_SendChar ( uint32_t ch )

ITM Send Character.

Transmits a character via the ITM channel 0, and

Just returns when no debugger is connected that has booked the output.
Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Parameters

[in] ch Character to transmit.

Returns
Character to transmit.

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM TCR: ITM Enable bit Mask

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

< ITM Base Address

< ITM configuration struct

Definition at line 2862 of file core_armv8mml.h.

 {
   if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
       ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0U].u32 == 0UL)
     {
       __NOP();
     }
     ITM->PORT[0U].u8 = (uint8_t)ch;
   }
   return (ch);
 }

Variable Documentation

◆ _reserved0 [1/20]

uint32_t { ... } ::_reserved0

bit: 0..26 Reserved

Definition at line 210 of file core_cm3.h.

◆ _reserved0 [2/20]

uint32_t { ... } ::_reserved0

bit: 0..26 Reserved

Definition at line 210 of file core_sc300.h.

◆ _reserved0 [3/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 245 of file core_cm3.h.

◆ _reserved0 [4/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 245 of file core_sc300.h.

◆ _reserved0 [5/20]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 263 of file core_cm3.h.

◆ _reserved0 [6/20]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 263 of file core_sc300.h.

◆ _reserved0 [7/20]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 263 of file core_cm4.h.

◆ _reserved0 [8/20]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 278 of file core_cm7.h.

◆ _reserved0 [9/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 303 of file core_cm4.h.

◆ _reserved0 [10/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 318 of file core_cm7.h.

◆ _reserved0 [11/20]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 318 of file core_armv8mml.h.

◆ _reserved0 [12/20]

uint32_t { ... } ::_reserved0

bit: 0..15 Reserved

Definition at line 318 of file core_cm33.h.

◆ _reserved0 [13/20]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 321 of file core_cm4.h.

◆ _reserved0 [14/20]

uint32_t { ... } ::_reserved0

bit: 9 Reserved

Definition at line 336 of file core_cm7.h.

◆ _reserved0 [15/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 358 of file core_cm33.h.

◆ _reserved0 [16/20]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 358 of file core_armv8mml.h.

◆ _reserved0 [17/20]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 376 of file core_armv8mml.h.

◆ _reserved0 [18/20]

uint32_t { ... } ::_reserved0

bit: 9..15 Reserved

Definition at line 376 of file core_cm33.h.

◆ _reserved0 [19/20]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

Definition at line 378 of file core_cm4.h.

◆ _reserved0 [20/20]

uint32_t { ... } ::_reserved0

bit: 3..31 Reserved

Definition at line 393 of file core_cm7.h.

◆ _reserved1 [1/15]

uint32_t { ... } ::_reserved1

bit: 16..23 Reserved

Definition at line 265 of file core_cm3.h.

◆ _reserved1 [2/15]

uint32_t { ... } ::_reserved1

bit: 16..23 Reserved

Definition at line 265 of file core_sc300.h.

◆ _reserved1 [3/15]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 265 of file core_cm4.h.

◆ _reserved1 [4/15]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 280 of file core_cm7.h.

◆ _reserved1 [5/15]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 315 of file core_sc300.h.

◆ _reserved1 [6/15]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 315 of file core_cm3.h.

◆ _reserved1 [7/15]

uint32_t APSR_Type::_reserved1

bit: 20..26 Reserved

Definition at line 320 of file core_armv8mml.h.

◆ _reserved1 [8/15]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 320 of file core_armv8mml.h.

◆ _reserved1 [9/15]

uint32_t { ... } ::_reserved1

bit: 20..26 Reserved

Definition at line 320 of file core_cm33.h.

◆ _reserved1 [10/15]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 324 of file core_cm4.h.

◆ _reserved1 [11/15]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 339 of file core_cm7.h.

◆ _reserved1 [12/15]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 378 of file core_armv8mml.h.

◆ _reserved1 [13/15]

uint32_t { ... } ::_reserved1

bit: 20..23 Reserved

Definition at line 378 of file core_cm33.h.

◆ _reserved1 [14/15]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 430 of file core_armv8mml.h.

◆ _reserved1 [15/15]

uint32_t { ... } ::_reserved1

bit: 4..31 Reserved

Definition at line 430 of file core_cm33.h.

◆ ABFSR

volatile uint32_t SCB_Type::ABFSR

Defines 'read / write' structure member permissions Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register

Definition at line 548 of file core_armv8mml.h.

◆ ACTLR

volatile uint32_t SCnSCB_Type::ACTLR

Defines 'read / write' structure member permissions Offset: 0x008 (R/W) Auxiliary Control Register

Definition at line 1013 of file core_armv8mml.h.

◆ ADR

const volatile uint32_t SCB_Type::ADR

Defines 'read only' structure member permissions Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 392 of file core_cm3.h.

◆ AFSR

volatile uint32_t SCB_Type::AFSR

Defines 'read / write' structure member permissions Offset: 0x03C (R/W) Auxiliary Fault Status Register

Definition at line 512 of file core_armv8mml.h.

◆ AHBPCR

volatile uint32_t SCB_Type::AHBPCR

Defines 'read / write' structure member permissions Offset: 0x298 (R/W) AHBP Control Register

Definition at line 544 of file core_armv8mml.h.

◆ AHBSCR

volatile uint32_t SCB_Type::AHBSCR

Defines 'read / write' structure member permissions Offset: 0x2A0 (R/W) AHB Slave Control Register

Definition at line 546 of file core_armv8mml.h.

◆ b [1/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [2/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [3/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [4/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [5/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [6/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [7/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [8/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [9/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [10/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [11/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [12/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [13/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [14/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [15/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [16/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [17/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [18/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [19/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [20/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [21/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [22/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [23/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [24/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ BFAR

volatile uint32_t SCB_Type::BFAR

Defines 'read / write' structure member permissions Offset: 0x038 (R/W) BusFault Address Register

Definition at line 511 of file core_armv8mml.h.

◆ C [1/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 213 of file core_cm3.h.

◆ C [2/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 213 of file core_sc300.h.

◆ C [3/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 268 of file core_cm4.h.

◆ C [4/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 270 of file core_sc300.h.

◆ C [5/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 270 of file core_cm3.h.

◆ C [6/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 283 of file core_cm7.h.

◆ C [7/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 323 of file core_armv8mml.h.

◆ C [8/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 323 of file core_cm33.h.

◆ C [9/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 329 of file core_cm4.h.

◆ C [10/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 344 of file core_cm7.h.

◆ C [11/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 383 of file core_armv8mml.h.

◆ C [12/12]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 383 of file core_cm33.h.

◆ CACR

volatile uint32_t SCB_Type::CACR

Defines 'read / write' structure member permissions Offset: 0x29C (R/W) L1 Cache Control Register

Definition at line 545 of file core_armv8mml.h.

◆ CCSIDR

const volatile uint32_t SCB_Type::CCSIDR

Defines 'read only' structure member permissions Offset: 0x080 (R/ ) Cache Size ID Register

Definition at line 520 of file core_armv8mml.h.

◆ CFSR

volatile uint32_t SCB_Type::CFSR

Defines 'read / write' structure member permissions Offset: 0x028 (R/W) Configurable Fault Status Register

Definition at line 507 of file core_armv8mml.h.

◆ CID0

const volatile uint32_t ITM_Type::CID0

Defines 'read only' structure member permissions Offset: 0xFF0 (R/ ) ITM Component Identification Register #0

Definition at line 1118 of file core_armv8mml.h.

◆ CID1

const volatile uint32_t ITM_Type::CID1

Defines 'read only' structure member permissions Offset: 0xFF4 (R/ ) ITM Component Identification Register #1

Definition at line 1119 of file core_armv8mml.h.

◆ CID2

const volatile uint32_t ITM_Type::CID2

Defines 'read only' structure member permissions Offset: 0xFF8 (R/ ) ITM Component Identification Register #2

Definition at line 1120 of file core_armv8mml.h.

◆ CID3

const volatile uint32_t ITM_Type::CID3

Defines 'read only' structure member permissions Offset: 0xFFC (R/ ) ITM Component Identification Register #3

Definition at line 1121 of file core_armv8mml.h.

◆ CLIDR

const volatile uint32_t SCB_Type::CLIDR

Defines 'read only' structure member permissions Offset: 0x078 (R/ ) Cache Level ID register

Definition at line 518 of file core_armv8mml.h.

◆ CPACR

volatile uint32_t SCB_Type::CPACR

Defines 'read / write' structure member permissions Offset: 0x088 (R/W) Coprocessor Access Control Register

Definition at line 522 of file core_armv8mml.h.

◆ CPICNT

volatile uint32_t DWT_Type::CPICNT

Defines 'read / write' structure member permissions Offset: 0x008 (R/W) CPI Count Register

Definition at line 1205 of file core_armv8mml.h.

◆ CPPWR

volatile uint32_t SCnSCB_Type::CPPWR

Defines 'read / write' structure member permissions Offset: 0x00C (R/W) Coprocessor Power Control Register

Definition at line 1014 of file core_armv8mml.h.

◆ CSSELR

volatile uint32_t SCB_Type::CSSELR

Defines 'read / write' structure member permissions Offset: 0x084 (R/W) Cache Size Selection Register

Definition at line 521 of file core_armv8mml.h.

◆ CTR

const volatile uint32_t SCB_Type::CTR

Defines 'read only' structure member permissions Offset: 0x07C (R/ ) Cache Type register

Definition at line 519 of file core_armv8mml.h.

◆ CYCCNT

volatile uint32_t DWT_Type::CYCCNT

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) Cycle Count Register

Definition at line 1204 of file core_armv8mml.h.

◆ DCCIMVAC

volatile uint32_t SCB_Type::DCCIMVAC

Defines 'write only' structure member permissions Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC

Definition at line 539 of file core_armv8mml.h.

◆ DCCISW

volatile uint32_t SCB_Type::DCCISW

Defines 'write only' structure member permissions Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way

Definition at line 540 of file core_armv8mml.h.

◆ DCCMVAC

volatile uint32_t SCB_Type::DCCMVAC

Defines 'write only' structure member permissions Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC

Definition at line 537 of file core_armv8mml.h.

◆ DCCMVAU

volatile uint32_t SCB_Type::DCCMVAU

Defines 'write only' structure member permissions Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU

Definition at line 536 of file core_armv8mml.h.

◆ DCCSW

volatile uint32_t SCB_Type::DCCSW

Defines 'write only' structure member permissions Offset: 0x26C ( /W) D-Cache Clean by Set-way

Definition at line 538 of file core_armv8mml.h.

◆ DCIMVAC

volatile uint32_t SCB_Type::DCIMVAC

Defines 'write only' structure member permissions Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC

Definition at line 534 of file core_armv8mml.h.

◆ DCISW

volatile uint32_t SCB_Type::DCISW

Defines 'write only' structure member permissions Offset: 0x260 ( /W) D-Cache Invalidate by Set-way

Definition at line 535 of file core_armv8mml.h.

◆ DEVARCH [1/2]

const volatile uint32_t ITM_Type::DEVARCH

Defines 'read only' structure member permissions Offset: 0xFBC (R/ ) ITM Device Architecture Register

Definition at line 1108 of file core_armv8mml.h.

◆ DEVARCH [2/2]

const volatile uint32_t DWT_Type::DEVARCH

Defines 'read only' structure member permissions Offset: 0xFBC (R/ ) Device Architecture Register

Definition at line 1277 of file core_armv8mml.h.

◆ DFR

const volatile uint32_t SCB_Type::DFR

Defines 'read only' structure member permissions Offset: 0x048 (R/ ) Debug Feature Register

Definition at line 391 of file core_cm3.h.

◆ DFSR

volatile uint32_t SCB_Type::DFSR

Defines 'read / write' structure member permissions Offset: 0x030 (R/W) Debug Fault Status Register

Definition at line 509 of file core_armv8mml.h.

◆ DTCMCR

volatile uint32_t SCB_Type::DTCMCR

Defines 'read / write' structure member permissions Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers

Definition at line 543 of file core_armv8mml.h.

◆ EXCCNT

volatile uint32_t DWT_Type::EXCCNT

Defines 'read / write' structure member permissions Offset: 0x00C (R/W) Exception Overhead Count Register

Definition at line 1206 of file core_armv8mml.h.

◆ FIFO0

const volatile uint32_t TPI_Type::FIFO0

Defines 'read only' structure member permissions Offset: 0xEEC (R/ ) Integration ETM Data

Definition at line 1010 of file core_cm3.h.

◆ FIFO1

const volatile uint32_t TPI_Type::FIFO1

Defines 'read only' structure member permissions Offset: 0xEFC (R/ ) Integration ITM Data

Definition at line 1014 of file core_cm3.h.

◆ FOLDCNT

volatile uint32_t DWT_Type::FOLDCNT

Defines 'read / write' structure member permissions Offset: 0x018 (R/W) Folded-instruction Count Register

Definition at line 1209 of file core_armv8mml.h.

◆ FPCA [1/5]

uint32_t { ... } ::FPCA

bit: 2 FP extension active flag

Definition at line 377 of file core_cm4.h.

◆ FPCA [2/5]

uint32_t { ... } ::FPCA

bit: 2 FP extension active flag

Definition at line 392 of file core_cm7.h.

◆ FPCA [3/5]

uint32_t CONTROL_Type::FPCA

bit: 2 Floating-point context active

bit: 2 FP extension active flag

Definition at line 428 of file core_armv8mml.h.

◆ FPCA [4/5]

uint32_t { ... } ::FPCA

bit: 2 Floating-point context active

Definition at line 428 of file core_armv8mml.h.

◆ FPCA [5/5]

uint32_t { ... } ::FPCA

bit: 2 Floating-point context active

Definition at line 428 of file core_cm33.h.

◆ FPCAR

volatile uint32_t FPU_Type::FPCAR

Defines 'read / write' structure member permissions Offset: 0x008 (R/W) Floating-Point Context Address Register

Definition at line 1689 of file core_armv8mml.h.

◆ FPCCR

volatile uint32_t FPU_Type::FPCCR

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) Floating-Point Context Control Register

Definition at line 1688 of file core_armv8mml.h.

◆ FPDSCR

volatile uint32_t FPU_Type::FPDSCR

Defines 'read / write' structure member permissions Offset: 0x00C (R/W) Floating-Point Default Status Control Register

Definition at line 1690 of file core_armv8mml.h.

◆ FSCR

const volatile uint32_t TPI_Type::FSCR

Defines 'read only' structure member permissions Offset: 0x308 (R/ ) Formatter Synchronization Counter Register

Definition at line 1007 of file core_cm3.h.

◆ GE [1/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 264 of file core_cm4.h.

◆ GE [2/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 279 of file core_cm7.h.

◆ GE [3/10]

uint32_t APSR_Type::GE

bit: 16..19 Greater than or Equal flags

Definition at line 319 of file core_armv8mml.h.

◆ GE [4/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 319 of file core_cm33.h.

◆ GE [5/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 319 of file core_armv8mml.h.

◆ GE [6/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 323 of file core_cm4.h.

◆ GE [7/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 338 of file core_cm7.h.

◆ GE [8/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 377 of file core_armv8mml.h.

◆ GE [9/10]

uint32_t xPSR_Type::GE

bit: 16..19 Greater than or Equal flags

Definition at line 377 of file core_armv8mml.h.

◆ GE [10/10]

uint32_t { ... } ::GE

bit: 16..19 Greater than or Equal flags

Definition at line 377 of file core_cm33.h.

◆ HFSR

volatile uint32_t SCB_Type::HFSR

Defines 'read / write' structure member permissions Offset: 0x02C (R/W) HardFault Status Register

Definition at line 508 of file core_armv8mml.h.

◆ ICI_IT_1 [1/5]

uint32_t xPSR_Type::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 264 of file core_cm3.h.

◆ ICI_IT_1 [2/5]

uint32_t { ... } ::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 264 of file core_cm3.h.

◆ ICI_IT_1 [3/5]

uint32_t { ... } ::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 264 of file core_sc300.h.

◆ ICI_IT_1 [4/5]

uint32_t { ... } ::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 322 of file core_cm4.h.

◆ ICI_IT_1 [5/5]

uint32_t { ... } ::ICI_IT_1

bit: 10..15 ICI/IT part 1

Definition at line 337 of file core_cm7.h.

◆ ICI_IT_2 [1/5]

uint32_t { ... } ::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 267 of file core_sc300.h.

◆ ICI_IT_2 [2/5]

uint32_t { ... } ::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 267 of file core_cm3.h.

◆ ICI_IT_2 [3/5]

uint32_t xPSR_Type::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 267 of file core_cm3.h.

◆ ICI_IT_2 [4/5]

uint32_t { ... } ::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 326 of file core_cm4.h.

◆ ICI_IT_2 [5/5]

uint32_t { ... } ::ICI_IT_2

bit: 25..26 ICI/IT part 2

Definition at line 341 of file core_cm7.h.

◆ ICIALLU

volatile uint32_t SCB_Type::ICIALLU

Defines 'write only' structure member permissions Offset: 0x250 ( /W) I-Cache Invalidate All to PoU

Definition at line 531 of file core_armv8mml.h.

◆ ICIMVAU

volatile uint32_t SCB_Type::ICIMVAU

Defines 'write only' structure member permissions Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU

Definition at line 533 of file core_armv8mml.h.

◆ ICTR

const volatile uint32_t SCnSCB_Type::ICTR

Defines 'read only' structure member permissions Offset: 0x004 (R/ ) Interrupt Controller Type Register

Definition at line 1012 of file core_armv8mml.h.

◆ ID_ADR

const volatile uint32_t SCB_Type::ID_ADR

Defines 'read only' structure member permissions Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 515 of file core_armv8mml.h.

◆ ID_AFR

const volatile uint32_t SCB_Type::ID_AFR

Defines 'read only' structure member permissions Offset: 0x04C (R/ ) Auxiliary Feature Register

Definition at line 473 of file core_cm7.h.

◆ ID_DFR

const volatile uint32_t SCB_Type::ID_DFR

Defines 'read only' structure member permissions Offset: 0x048 (R/ ) Debug Feature Register

Definition at line 514 of file core_armv8mml.h.

◆ ID_ISAR

const volatile uint32_t SCB_Type::ID_ISAR

Defines 'read only' structure member permissions Offset: 0x060 (R/ ) Instruction Set Attributes Register

Definition at line 517 of file core_armv8mml.h.

◆ ID_MFR

const volatile uint32_t SCB_Type::ID_MFR[4U]

Defines 'read only' structure member permissions Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 474 of file core_cm7.h.

◆ ID_MMFR

const volatile uint32_t SCB_Type::ID_MMFR

Defines 'read only' structure member permissions Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 516 of file core_armv8mml.h.

◆ ID_PFR

const volatile uint32_t SCB_Type::ID_PFR

Defines 'read only' structure member permissions Offset: 0x040 (R/ ) Processor Feature Register

Definition at line 513 of file core_armv8mml.h.

◆ IMCR

volatile uint32_t ITM_Type::IMCR

Defines 'read / write' structure member permissions Offset: 0xF00 (R/W) ITM Integration Mode Control Register

Definition at line 1103 of file core_armv8mml.h.

◆ IP

volatile uint8_t NVIC_Type::IP[240U]

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 352 of file core_cm3.h.

◆ IPR

volatile uint8_t NVIC_Type::IPR[496U]

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 475 of file core_armv8mml.h.

◆ IRR

const volatile uint32_t ITM_Type::IRR

Defines 'read only' structure member permissions Offset: 0xEFC (R/ ) ITM Integration Read Register

Definition at line 1102 of file core_armv8mml.h.

◆ ISAR

const volatile uint32_t SCB_Type::ISAR

Defines 'read only' structure member permissions Offset: 0x060 (R/ ) Instruction Set Attributes Register

Definition at line 394 of file core_cm3.h.

◆ ISR [1/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 244 of file core_cm3.h.

◆ ISR [2/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 244 of file core_sc300.h.

◆ ISR [3/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 262 of file core_sc300.h.

◆ ISR [4/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 262 of file core_cm3.h.

◆ ISR [5/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 302 of file core_cm4.h.

◆ ISR [6/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 317 of file core_cm7.h.

◆ ISR [7/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 320 of file core_cm4.h.

◆ ISR [8/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 335 of file core_cm7.h.

◆ ISR [9/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 357 of file core_cm33.h.

◆ ISR [10/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 357 of file core_armv8mml.h.

◆ ISR [11/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 375 of file core_cm33.h.

◆ ISR [12/12]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 375 of file core_armv8mml.h.

◆ IT [1/3]

uint32_t xPSR_Type::IT

bit: 25..26 saved IT state (read 0)

Definition at line 380 of file core_armv8mml.h.

◆ IT [2/3]

uint32_t { ... } ::IT

bit: 25..26 saved IT state (read 0)

Definition at line 380 of file core_armv8mml.h.

◆ IT [3/3]

uint32_t { ... } ::IT

bit: 25..26 saved IT state (read 0)

Definition at line 380 of file core_cm33.h.

◆ ITATBCTR2

const volatile uint32_t TPI_Type::ITATBCTR2

Defines 'read only' structure member permissions Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 1011 of file core_cm3.h.

◆ ITCMCR

volatile uint32_t SCB_Type::ITCMCR

Defines 'read / write' structure member permissions Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register

Definition at line 542 of file core_armv8mml.h.

◆ ITM_RxBuffer [1/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ ITM_RxBuffer [2/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ ITM_RxBuffer [3/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ ITM_RxBuffer [4/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ ITM_RxBuffer [5/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ ITM_RxBuffer [6/6]

volatile int32_t ITM_RxBuffer

External variable to receive characters.

◆ IWR

volatile uint32_t ITM_Type::IWR

Defines 'write only' structure member permissions Offset: 0xEF8 ( /W) ITM Integration Write Register

Definition at line 1101 of file core_armv8mml.h.

◆ LAR [1/2]

volatile uint32_t ITM_Type::LAR

Defines 'write only' structure member permissions Offset: 0xFB0 ( /W) ITM Lock Access Register

Definition at line 1105 of file core_armv8mml.h.

◆ LAR [2/2]

volatile uint32_t DWT_Type::LAR

Defines 'write only' structure member permissions Offset: 0xFB0 ( W) Lock Access Register

Definition at line 1142 of file core_cm7.h.

◆ LSR [1/2]

const volatile uint32_t ITM_Type::LSR

Defines 'read only' structure member permissions Offset: 0xFB4 (R/ ) ITM Lock Status Register

Definition at line 1106 of file core_armv8mml.h.

◆ LSR [2/2]

const volatile uint32_t DWT_Type::LSR

Defines 'read only' structure member permissions Offset: 0xFB4 (R ) Lock Status Register

Definition at line 1275 of file core_armv8mml.h.

◆ LSUCNT

volatile uint32_t DWT_Type::LSUCNT

Defines 'read / write' structure member permissions Offset: 0x014 (R/W) LSU Count Register

Definition at line 1208 of file core_armv8mml.h.

◆ MASK0

volatile uint32_t DWT_Type::MASK0

Defines 'read / write' structure member permissions Offset: 0x024 (R/W) Mask Register 0

Definition at line 860 of file core_cm3.h.

◆ MASK1

volatile uint32_t DWT_Type::MASK1

Defines 'read / write' structure member permissions Offset: 0x034 (R/W) Mask Register 1

Definition at line 864 of file core_cm3.h.

◆ MASK2

volatile uint32_t DWT_Type::MASK2

Defines 'read / write' structure member permissions Offset: 0x044 (R/W) Mask Register 2

Definition at line 868 of file core_cm3.h.

◆ MASK3

volatile uint32_t DWT_Type::MASK3

Defines 'read / write' structure member permissions Offset: 0x054 (R/W) Mask Register 3

Definition at line 872 of file core_cm3.h.

◆ MMFAR

volatile uint32_t SCB_Type::MMFAR

Defines 'read / write' structure member permissions Offset: 0x034 (R/W) MemManage Fault Address Register

Definition at line 510 of file core_armv8mml.h.

◆ MMFR

const volatile uint32_t SCB_Type::MMFR

Defines 'read only' structure member permissions Offset: 0x050 (R/ ) Memory Model Feature Register

Definition at line 393 of file core_cm3.h.

◆ MVFR0 [1/2]

const volatile uint32_t SCB_Type::MVFR0

Defines 'read only' structure member permissions Offset: 0x240 (R/ ) Media and VFP Feature Register 0

Definition at line 527 of file core_armv8mml.h.

◆ MVFR0 [2/2]

const volatile uint32_t FPU_Type::MVFR0

Defines 'read only' structure member permissions Offset: 0x010 (R/ ) Media and FP Feature Register 0

Definition at line 1691 of file core_armv8mml.h.

◆ MVFR1 [1/2]

const volatile uint32_t SCB_Type::MVFR1

Defines 'read only' structure member permissions Offset: 0x244 (R/ ) Media and VFP Feature Register 1

Definition at line 528 of file core_armv8mml.h.

◆ MVFR1 [2/2]

const volatile uint32_t FPU_Type::MVFR1

Defines 'read only' structure member permissions Offset: 0x014 (R/ ) Media and FP Feature Register 1

Definition at line 1692 of file core_armv8mml.h.

◆ MVFR2 [1/2]

const volatile uint32_t SCB_Type::MVFR2

Defines 'read only' structure member permissions Offset: 0x248 (R/ ) Media and VFP Feature Register 2

Definition at line 529 of file core_armv8mml.h.

◆ MVFR2 [2/2]

const volatile uint32_t FPU_Type::MVFR2

Defines 'read only' structure member permissions Offset: 0x018 (R/ ) Media and FP Feature Register 2

Definition at line 1532 of file core_cm7.h.

◆ N [1/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 215 of file core_cm3.h.

◆ N [2/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 215 of file core_sc300.h.

◆ N [3/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 270 of file core_cm4.h.

◆ N [4/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 272 of file core_cm3.h.

◆ N [5/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 272 of file core_sc300.h.

◆ N [6/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 285 of file core_cm7.h.

◆ N [7/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 325 of file core_armv8mml.h.

◆ N [8/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 325 of file core_cm33.h.

◆ N [9/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 331 of file core_cm4.h.

◆ N [10/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 346 of file core_cm7.h.

◆ N [11/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 385 of file core_cm33.h.

◆ N [12/12]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 385 of file core_armv8mml.h.

◆ nPRIV [1/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 313 of file core_sc300.h.

◆ nPRIV [2/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 313 of file core_cm3.h.

◆ nPRIV [3/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 375 of file core_cm4.h.

◆ nPRIV [4/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 390 of file core_cm7.h.

◆ nPRIV [5/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 426 of file core_cm33.h.

◆ nPRIV [6/6]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 426 of file core_armv8mml.h.

◆ NSACR

volatile uint32_t SCB_Type::NSACR

Defines 'read / write' structure member permissions Offset: 0x08C (R/W) Non-Secure Access Control Register

Definition at line 523 of file core_armv8mml.h.

◆ PFR

const volatile uint32_t SCB_Type::PFR

Defines 'read only' structure member permissions Offset: 0x040 (R/ ) Processor Feature Register

Definition at line 390 of file core_cm3.h.

◆ PID0

const volatile uint32_t ITM_Type::PID0

Defines 'read only' structure member permissions Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0

Definition at line 1114 of file core_armv8mml.h.

◆ PID1

const volatile uint32_t ITM_Type::PID1

Defines 'read only' structure member permissions Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1

Definition at line 1115 of file core_armv8mml.h.

◆ PID2

const volatile uint32_t ITM_Type::PID2

Defines 'read only' structure member permissions Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2

Definition at line 1116 of file core_armv8mml.h.

◆ PID3

const volatile uint32_t ITM_Type::PID3

Defines 'read only' structure member permissions Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3

Definition at line 1117 of file core_armv8mml.h.

◆ PID4

const volatile uint32_t ITM_Type::PID4

Defines 'read only' structure member permissions Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4

Definition at line 1110 of file core_armv8mml.h.

◆ PID5

const volatile uint32_t ITM_Type::PID5

Defines 'read only' structure member permissions Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5

Definition at line 1111 of file core_armv8mml.h.

◆ PID6

const volatile uint32_t ITM_Type::PID6

Defines 'read only' structure member permissions Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6

Definition at line 1112 of file core_armv8mml.h.

◆ PID7

const volatile uint32_t ITM_Type::PID7

Defines 'read only' structure member permissions Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7

Definition at line 1113 of file core_armv8mml.h.

◆ PORT [1/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ PORT [2/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ PORT [3/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ PORT [4/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ PORT [5/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers

◆ PORT [6/6]

volatile { ... } ITM_Type::PORT[32U]

Defines 'write only' structure member permissions Offset: 0x000 ( /W) ITM Stimulus Port Registers