Cache Functions

Functions that configure Instruction and Data cache. More...

Modules
	SysTick Functions
	Functions that configure the System.
__STATIC_INLINE void	SCB_EnableICache (void)
	Enable I-Cache. More...
__STATIC_INLINE void	SCB_DisableICache (void)
	Disable I-Cache. More...
__STATIC_INLINE void	SCB_InvalidateICache (void)
	Invalidate I-Cache. More...
__STATIC_INLINE void	SCB_EnableDCache (void)
	Enable D-Cache. More...
__STATIC_INLINE void	SCB_DisableDCache (void)
	Disable D-Cache. More...
__STATIC_INLINE void	SCB_InvalidateDCache (void)
	Invalidate D-Cache. More...
__STATIC_INLINE void	SCB_CleanDCache (void)
	Clean D-Cache. More...
__STATIC_INLINE void	SCB_CleanInvalidateDCache (void)
	Clean & Invalidate D-Cache. More...
__STATIC_INLINE void	SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
	D-Cache Invalidate by address. More...
__STATIC_INLINE void	SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
	D-Cache Clean by address. More...
__STATIC_INLINE void	SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
	D-Cache Clean and Invalidate by address. More...
#define	CCSIDR_WAYS(x)   (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
#define	CCSIDR_SETS(x)   (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

Detailed Description

Functions that configure Instruction and Data cache.

Macro Definition Documentation

CCSIDR_SETS

#define CCSIDR_SETS

(

x

)

(((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )

Definition at line 2222 of file core_cm7.h.

CCSIDR_WAYS

#define CCSIDR_WAYS

(

x

)

(((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)

Definition at line 2221 of file core_cm7.h.

Function Documentation

SCB_CleanDCache()

__STATIC_INLINE void SCB_CleanDCache

(

void

)

Clean D-Cache.

Cleans D-Cache

Definition at line 2392 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;
 
     SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
   __DSB();
 
    ccsidr = SCB->CCSIDR;
 
                                            /* clean D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
      do {
        SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
                      ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk)  );
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
    } while(sets-- != 0U);
 
    __DSB();
    __ISB();
  #endif
}

SCB_CleanDCache_by_Addr()

__STATIC_INLINE void SCB_CleanDCache_by_Addr	(	uint32_t *	addr,
		int32_t	dsize
	)

D-Cache Clean by address.

Cleans D-Cache for the given address

Parameters

[in]	addr	address (aligned to 32-byte boundary)
[in]	dsize	size of memory block (in number of bytes)

Definition at line 2491 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize;
    uint32_t op_addr = (uint32_t) addr;
     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
    __DSB();
 
    while (op_size > 0) {
      SCB->DCCMVAC = op_addr;
      op_addr += (uint32_t)linesize;
      op_size -=           linesize;
    }
 
    __DSB();
    __ISB();
  #endif
}

SCB_CleanInvalidateDCache()

__STATIC_INLINE void SCB_CleanInvalidateDCache

(

void

)

Clean & Invalidate D-Cache.

Cleans and Invalidates D-Cache

Definition at line 2427 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;
 
    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
    __DSB();
 
    ccsidr = SCB->CCSIDR;
 
                                            /* clean & invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
      do {
        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
    } while(sets-- != 0U);
 
    __DSB();
    __ISB();
  #endif
}

SCB_CleanInvalidateDCache_by_Addr()

__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr	(	uint32_t *	addr,
		int32_t	dsize
	)

D-Cache Clean and Invalidate by address.

Cleans and invalidates D_Cache for the given address

Parameters

[in]	addr	address (aligned to 32-byte boundary)
[in]	dsize	size of memory block (in number of bytes)

Definition at line 2518 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize;
    uint32_t op_addr = (uint32_t) addr;
     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
    __DSB();
 
    while (op_size > 0) {
      SCB->DCCIMVAC = op_addr;
      op_addr += (uint32_t)linesize;
      op_size -=           linesize;
    }
 
    __DSB();
    __ISB();
  #endif
}

SCB_DisableDCache()

__STATIC_INLINE void SCB_DisableDCache

(

void

)

Disable D-Cache.

Turns off D-Cache

Definition at line 2319 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;
 
    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
    __DSB();
 
    SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk;  /* disable D-Cache */
    __DSB();
 
    ccsidr = SCB->CCSIDR;
 
                                            /* clean & invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
      do {
        SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
                       ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk)  );
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
    } while(sets-- != 0U);
 
    __DSB();
    __ISB();
  #endif
}

SCB_DisableICache()

__STATIC_INLINE void SCB_DisableICache

(

void

)

Disable I-Cache.

Turns off I-Cache

Definition at line 2248 of file core_cm7.h.

{
  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
    __DSB();
    __ISB();
    SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk;  /* disable I-Cache */
    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
    __DSB();
    __ISB();
  #endif
}

SCB_EnableDCache()

__STATIC_INLINE void SCB_EnableDCache

(

void

)

Enable D-Cache.

Turns on D-Cache

Definition at line 2281 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;
 
    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
    __DSB();
 
    ccsidr = SCB->CCSIDR;
 
                                            /* invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
      do {
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
    } while(sets-- != 0U);
    __DSB();
 
    SCB->CCR |=  (uint32_t)SCB_CCR_DC_Msk;  /* enable D-Cache */
 
    __DSB();
    __ISB();
  #endif
}

SCB_EnableICache()

__STATIC_INLINE void SCB_EnableICache

(

void

)

Enable I-Cache.

Turns on I-Cache

Definition at line 2229 of file core_cm7.h.

{
  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
    __DSB();
    __ISB();
    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */
    __DSB();
    __ISB();
    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */
    __DSB();
    __ISB();
  #endif
}

SCB_InvalidateDCache()

__STATIC_INLINE void SCB_InvalidateDCache

(

void

)

Invalidate D-Cache.

Invalidates D-Cache

Definition at line 2357 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
    uint32_t ccsidr;
    uint32_t sets;
    uint32_t ways;
 
    SCB->CSSELR = 0U; /*(0U << 1U) | 0U;*/  /* Level 1 data cache */
    __DSB();
 
    ccsidr = SCB->CCSIDR;
 
                                            /* invalidate D-Cache */
    sets = (uint32_t)(CCSIDR_SETS(ccsidr));
    do {
      ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
      do {
        SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
                      ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk)  );
        #if defined ( __CC_ARM )
          __schedule_barrier();
        #endif
      } while (ways-- != 0U);
    } while(sets-- != 0U);
 
    __DSB();
    __ISB();
  #endif
}

SCB_InvalidateDCache_by_Addr()

__STATIC_INLINE void SCB_InvalidateDCache_by_Addr	(	uint32_t *	addr,
		int32_t	dsize
	)

D-Cache Invalidate by address.

Invalidates D-Cache for the given address

Parameters

[in]	addr	address (aligned to 32-byte boundary)
[in]	dsize	size of memory block (in number of bytes)

Definition at line 2464 of file core_cm7.h.

{
  #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize;
    uint32_t op_addr = (uint32_t)addr;
     int32_t linesize = 32;                /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */
 
    __DSB();
 
    while (op_size > 0) {
      SCB->DCIMVAC = op_addr;
      op_addr += (uint32_t)linesize;
      op_size -=           linesize;
    }
 
    __DSB();
    __ISB();
  #endif
}

SCB_InvalidateICache()

__STATIC_INLINE void SCB_InvalidateICache

(

void

)

Invalidate I-Cache.

Invalidates I-Cache

Definition at line 2265 of file core_cm7.h.

{
  #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
    __DSB();
    __ISB();
    SCB->ICIALLU = 0UL;
    __DSB();
    __ISB();
  #endif
}