DIY Logging Volt/Ampmeter
core_cm3.h
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1 /**************************************************************************//**
2  * @file core_cm3.h
3  * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
4  * @version V5.0.8
5  * @date 04. June 2018
6  ******************************************************************************/
7 /*
8  * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
9  *
10  * SPDX-License-Identifier: Apache-2.0
11  *
12  * Licensed under the Apache License, Version 2.0 (the License); you may
13  * not use this file except in compliance with the License.
14  * You may obtain a copy of the License at
15  *
16  * www.apache.org/licenses/LICENSE-2.0
17  *
18  * Unless required by applicable law or agreed to in writing, software
19  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21  * See the License for the specific language governing permissions and
22  * limitations under the License.
23  */
24 
25 #if defined ( __ICCARM__ )
26  #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28  #pragma clang system_header /* treat file as system include file */
29 #endif
30 
31 #ifndef __CORE_CM3_H_GENERIC
32 #define __CORE_CM3_H_GENERIC
33 
34 #include <stdint.h>
35 
36 #ifdef __cplusplus
37  extern "C" {
38 #endif
39 
40 /**
41  \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
42  CMSIS violates the following MISRA-C:2004 rules:
43 
44  \li Required Rule 8.5, object/function definition in header file.<br>
45  Function definitions in header files are used to allow 'inlining'.
46 
47  \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
48  Unions are used for effective representation of core registers.
49 
50  \li Advisory Rule 19.7, Function-like macro defined.<br>
51  Function-like macros are used to allow more efficient code.
52  */
53 
54 
55 /*******************************************************************************
56  * CMSIS definitions
57  ******************************************************************************/
58 /**
59  \ingroup Cortex_M3
60  @{
61  */
62 
63 #include "cmsis_version.h"
64 
65 /* CMSIS CM3 definitions */
66 #define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
67 #define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
68 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \
69  __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
70 
71 #define __CORTEX_M (3U) /*!< Cortex-M Core */
72 
73 /** __FPU_USED indicates whether an FPU is used or not.
74  This core does not support an FPU at all
75 */
76 #define __FPU_USED 0U
77 
78 #if defined ( __CC_ARM )
79  #if defined __TARGET_FPU_VFP
80  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
81  #endif
82 
83 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
84  #if defined __ARM_PCS_VFP
85  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
86  #endif
87 
88 #elif defined ( __GNUC__ )
89  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
90  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91  #endif
92 
93 #elif defined ( __ICCARM__ )
94  #if defined __ARMVFP__
95  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
96  #endif
97 
98 #elif defined ( __TI_ARM__ )
99  #if defined __TI_VFP_SUPPORT__
100  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
101  #endif
102 
103 #elif defined ( __TASKING__ )
104  #if defined __FPU_VFP__
105  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
106  #endif
107 
108 #elif defined ( __CSMC__ )
109  #if ( __CSMC__ & 0x400U)
110  #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
111  #endif
112 
113 #endif
114 
115 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
116 
117 
118 #ifdef __cplusplus
119 }
120 #endif
121 
122 #endif /* __CORE_CM3_H_GENERIC */
123 
124 #ifndef __CMSIS_GENERIC
125 
126 #ifndef __CORE_CM3_H_DEPENDANT
127 #define __CORE_CM3_H_DEPENDANT
128 
129 #ifdef __cplusplus
130  extern "C" {
131 #endif
132 
133 /* check device defines and use defaults */
134 #if defined __CHECK_DEVICE_DEFINES
135  #ifndef __CM3_REV
136  #define __CM3_REV 0x0200U
137  #warning "__CM3_REV not defined in device header file; using default!"
138  #endif
139 
140  #ifndef __MPU_PRESENT
141  #define __MPU_PRESENT 0U
142  #warning "__MPU_PRESENT not defined in device header file; using default!"
143  #endif
144 
145  #ifndef __NVIC_PRIO_BITS
146  #define __NVIC_PRIO_BITS 3U
147  #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
148  #endif
149 
150  #ifndef __Vendor_SysTickConfig
151  #define __Vendor_SysTickConfig 0U
152  #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
153  #endif
154 #endif
155 
156 /* IO definitions (access restrictions to peripheral registers) */
157 /**
158  \defgroup CMSIS_glob_defs CMSIS Global Defines
159 
160  <strong>IO Type Qualifiers</strong> are used
161  \li to specify the access to peripheral variables.
162  \li for automatic generation of peripheral register debug information.
163 */
164 #ifdef __cplusplus
165  #define __I volatile /*!< Defines 'read only' permissions */
166 #else
167  #define __I volatile const /*!< Defines 'read only' permissions */
168 #endif
169 #define __O volatile /*!< Defines 'write only' permissions */
170 #define __IO volatile /*!< Defines 'read / write' permissions */
171 
172 /* following defines should be used for structure members */
173 #define __IM volatile const /*! Defines 'read only' structure member permissions */
174 #define __OM volatile /*! Defines 'write only' structure member permissions */
175 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
176 
177 /*@} end of group Cortex_M3 */
178 
179 
180 
181 /*******************************************************************************
182  * Register Abstraction
183  Core Register contain:
184  - Core Register
185  - Core NVIC Register
186  - Core SCB Register
187  - Core SysTick Register
188  - Core Debug Register
189  - Core MPU Register
190  ******************************************************************************/
191 /**
192  \defgroup CMSIS_core_register Defines and Type Definitions
193  \brief Type definitions and defines for Cortex-M processor based devices.
194 */
195 
196 /**
197  \ingroup CMSIS_core_register
198  \defgroup CMSIS_CORE Status and Control Registers
199  \brief Core Register type definitions.
200  @{
201  */
202 
203 /**
204  \brief Union type to access the Application Program Status Register (APSR).
205  */
206 typedef union
207 {
208  struct
209  {
210  uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
211  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
212  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
213  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
214  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
215  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
216  } b; /*!< Structure used for bit access */
217  uint32_t w; /*!< Type used for word access */
218 } APSR_Type;
219 
220 /* APSR Register Definitions */
221 #define APSR_N_Pos 31U /*!< APSR: N Position */
222 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
223 
224 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
225 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
226 
227 #define APSR_C_Pos 29U /*!< APSR: C Position */
228 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
229 
230 #define APSR_V_Pos 28U /*!< APSR: V Position */
231 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
232 
233 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
234 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
235 
236 
237 /**
238  \brief Union type to access the Interrupt Program Status Register (IPSR).
239  */
240 typedef union
241 {
242  struct
243  {
244  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
245  uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
246  } b; /*!< Structure used for bit access */
247  uint32_t w; /*!< Type used for word access */
248 } IPSR_Type;
249 
250 /* IPSR Register Definitions */
251 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
252 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
253 
254 
255 /**
256  \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
257  */
258 typedef union
259 {
260  struct
261  {
262  uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
263  uint32_t _reserved0:1; /*!< bit: 9 Reserved */
264  uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */
265  uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */
266  uint32_t T:1; /*!< bit: 24 Thumb bit */
267  uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */
268  uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
269  uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
270  uint32_t C:1; /*!< bit: 29 Carry condition code flag */
271  uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
272  uint32_t N:1; /*!< bit: 31 Negative condition code flag */
273  } b; /*!< Structure used for bit access */
274  uint32_t w; /*!< Type used for word access */
275 } xPSR_Type;
276 
277 /* xPSR Register Definitions */
278 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
279 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
280 
281 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
282 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
283 
284 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
285 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
286 
287 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
288 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
289 
290 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
291 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
292 
293 #define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */
294 #define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */
295 
296 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
297 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
298 
299 #define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */
300 #define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */
301 
302 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
304 
305 
306 /**
307  \brief Union type to access the Control Registers (CONTROL).
308  */
309 typedef union
310 {
311  struct
312  {
313  uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
314  uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
315  uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
316  } b; /*!< Structure used for bit access */
317  uint32_t w; /*!< Type used for word access */
318 } CONTROL_Type;
319 
320 /* CONTROL Register Definitions */
321 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
322 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
323 
324 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
325 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
326 
327 /*@} end of group CMSIS_CORE */
328 
329 
330 /**
331  \ingroup CMSIS_core_register
332  \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
333  \brief Type definitions for the NVIC Registers
334  @{
335  */
336 
337 /**
338  \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
339  */
340 typedef struct
341 {
342  __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
343  uint32_t RESERVED0[24U];
344  __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
345  uint32_t RSERVED1[24U];
346  __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
347  uint32_t RESERVED2[24U];
348  __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
349  uint32_t RESERVED3[24U];
350  __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
351  uint32_t RESERVED4[56U];
352  __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
353  uint32_t RESERVED5[644U];
354  __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
355 } NVIC_Type;
356 
357 /* Software Triggered Interrupt Register Definitions */
358 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
359 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
360 
361 /*@} end of group CMSIS_NVIC */
362 
363 
364 /**
365  \ingroup CMSIS_core_register
366  \defgroup CMSIS_SCB System Control Block (SCB)
367  \brief Type definitions for the System Control Block Registers
368  @{
369  */
370 
371 /**
372  \brief Structure type to access the System Control Block (SCB).
373  */
374 typedef struct
375 {
376  __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
377  __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
378  __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
379  __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
380  __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
381  __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
382  __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
383  __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
384  __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
385  __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
386  __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
387  __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
388  __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
389  __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
390  __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
391  __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
392  __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
393  __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
394  __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
395  uint32_t RESERVED0[5U];
396  __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
397 } SCB_Type;
398 
399 /* SCB CPUID Register Definitions */
400 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
401 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
402 
403 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
404 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
405 
406 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
407 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
408 
409 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
410 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
411 
412 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
413 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
414 
415 /* SCB Interrupt Control State Register Definitions */
416 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
417 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
418 
419 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
420 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
421 
422 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
423 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
424 
425 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
426 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
427 
428 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
429 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
430 
431 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
432 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
433 
434 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
435 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
436 
437 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
438 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
439 
440 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
441 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
442 
443 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
444 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
445 
446 /* SCB Vector Table Offset Register Definitions */
447 #if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */
448 #define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */
449 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
450 
451 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
452 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
453 #else
454 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
455 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
456 #endif
457 
458 /* SCB Application Interrupt and Reset Control Register Definitions */
459 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
461 
462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
464 
465 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
467 
468 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
469 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
470 
471 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
472 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
473 
474 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
475 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
476 
477 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
478 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
479 
480 /* SCB System Control Register Definitions */
481 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
482 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
483 
484 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
485 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
486 
487 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
488 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
489 
490 /* SCB Configuration Control Register Definitions */
491 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
492 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
493 
494 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
495 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
496 
497 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
498 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
499 
500 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
501 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
502 
503 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
504 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
505 
506 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
507 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
508 
509 /* SCB System Handler Control and State Register Definitions */
510 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
511 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
512 
513 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
514 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
515 
516 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
517 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
518 
519 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
520 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
521 
522 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
523 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
524 
525 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
526 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
527 
528 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
529 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
530 
531 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
532 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
533 
534 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
535 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
536 
537 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
538 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
539 
540 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
541 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
542 
543 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
544 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
545 
546 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
547 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
548 
549 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
550 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
551 
552 /* SCB Configurable Fault Status Register Definitions */
553 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
554 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
555 
556 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
557 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
558 
559 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
560 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
561 
562 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
563 #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
564 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
565 
566 #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
567 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
568 
569 #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
570 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
571 
572 #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
573 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
574 
575 #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
576 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
577 
578 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
579 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
580 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
581 
582 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
583 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
584 
585 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
586 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
587 
588 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
589 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
590 
591 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
592 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
593 
594 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
595 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
596 
597 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
598 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
599 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
600 
601 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
602 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
603 
604 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
605 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
606 
607 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
608 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
609 
610 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
611 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
612 
613 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
614 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
615 
616 /* SCB Hard Fault Status Register Definitions */
617 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
618 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
619 
620 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
621 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
622 
623 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
624 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
625 
626 /* SCB Debug Fault Status Register Definitions */
627 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
628 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
629 
630 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
631 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
632 
633 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
634 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
635 
636 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
637 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
638 
639 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
640 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
641 
642 /*@} end of group CMSIS_SCB */
643 
644 
645 /**
646  \ingroup CMSIS_core_register
647  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
648  \brief Type definitions for the System Control and ID Register not in the SCB
649  @{
650  */
651 
652 /**
653  \brief Structure type to access the System Control and ID Register not in the SCB.
654  */
655 typedef struct
656 {
657  uint32_t RESERVED0[1U];
658  __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
659 #if defined (__CM3_REV) && (__CM3_REV >= 0x200U)
660  __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
661 #else
662  uint32_t RESERVED1[1U];
663 #endif
664 } SCnSCB_Type;
665 
666 /* Interrupt Controller Type Register Definitions */
667 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
668 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
669 
670 /* Auxiliary Control Register Definitions */
671 
672 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
673 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
674 
675 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
676 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
677 
678 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
679 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
680 
681 /*@} end of group CMSIS_SCnotSCB */
682 
683 
684 /**
685  \ingroup CMSIS_core_register
686  \defgroup CMSIS_SysTick System Tick Timer (SysTick)
687  \brief Type definitions for the System Timer Registers.
688  @{
689  */
690 
691 /**
692  \brief Structure type to access the System Timer (SysTick).
693  */
694 typedef struct
695 {
696  __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
697  __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
698  __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
699  __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
700 } SysTick_Type;
701 
702 /* SysTick Control / Status Register Definitions */
703 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
704 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
705 
706 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
707 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
708 
709 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
710 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
711 
712 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
713 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
714 
715 /* SysTick Reload Register Definitions */
716 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
717 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
718 
719 /* SysTick Current Register Definitions */
720 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
721 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
722 
723 /* SysTick Calibration Register Definitions */
724 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
725 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
726 
727 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
728 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
729 
730 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
731 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
732 
733 /*@} end of group CMSIS_SysTick */
734 
735 
736 /**
737  \ingroup CMSIS_core_register
738  \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
739  \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
740  @{
741  */
742 
743 /**
744  \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
745  */
746 typedef struct
747 {
748  __OM union
749  {
750  __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
751  __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
752  __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
753  } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
754  uint32_t RESERVED0[864U];
755  __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
756  uint32_t RESERVED1[15U];
757  __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
758  uint32_t RESERVED2[15U];
759  __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
760  uint32_t RESERVED3[29U];
761  __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
762  __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
763  __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
764  uint32_t RESERVED4[43U];
765  __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
766  __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
767  uint32_t RESERVED5[6U];
768  __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
769  __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
770  __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
771  __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
772  __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
773  __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
774  __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
775  __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
776  __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
777  __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
778  __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
779  __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
780 } ITM_Type;
781 
782 /* ITM Trace Privilege Register Definitions */
783 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
784 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
785 
786 /* ITM Trace Control Register Definitions */
787 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
788 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
789 
790 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
791 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
792 
793 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
794 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
795 
796 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
797 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
798 
799 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
800 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
801 
802 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
803 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
804 
805 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
806 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
807 
808 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
809 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
810 
811 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
812 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
813 
814 /* ITM Integration Write Register Definitions */
815 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
816 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
817 
818 /* ITM Integration Read Register Definitions */
819 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
820 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
821 
822 /* ITM Integration Mode Control Register Definitions */
823 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
824 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
825 
826 /* ITM Lock Status Register Definitions */
827 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
828 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
829 
830 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
831 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
832 
833 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
834 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
835 
836 /*@}*/ /* end of group CMSIS_ITM */
837 
838 
839 /**
840  \ingroup CMSIS_core_register
841  \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
842  \brief Type definitions for the Data Watchpoint and Trace (DWT)
843  @{
844  */
845 
846 /**
847  \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
848  */
849 typedef struct
850 {
851  __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
852  __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
853  __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
854  __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
855  __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
856  __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
857  __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
858  __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
859  __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
860  __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
861  __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
862  uint32_t RESERVED0[1U];
863  __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
864  __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
865  __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
866  uint32_t RESERVED1[1U];
867  __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
868  __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
869  __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
870  uint32_t RESERVED2[1U];
871  __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
872  __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
873  __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
874 } DWT_Type;
875 
876 /* DWT Control Register Definitions */
877 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
878 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
879 
880 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
881 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
882 
883 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
884 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
885 
886 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
887 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
888 
889 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
890 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
891 
892 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
893 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
894 
895 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
896 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
897 
898 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
899 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
900 
901 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
902 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
903 
904 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
905 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
906 
907 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
908 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
909 
910 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
911 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
912 
913 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
914 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
915 
916 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
917 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
918 
919 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
920 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
921 
922 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
923 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
924 
925 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
926 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
927 
928 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
929 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
930 
931 /* DWT CPI Count Register Definitions */
932 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
933 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
934 
935 /* DWT Exception Overhead Count Register Definitions */
936 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
937 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
938 
939 /* DWT Sleep Count Register Definitions */
940 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
941 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
942 
943 /* DWT LSU Count Register Definitions */
944 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
945 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
946 
947 /* DWT Folded-instruction Count Register Definitions */
948 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
949 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
950 
951 /* DWT Comparator Mask Register Definitions */
952 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
953 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
954 
955 /* DWT Comparator Function Register Definitions */
956 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
957 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
958 
959 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
960 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
961 
962 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
963 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
964 
965 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
966 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
967 
968 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
969 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
970 
971 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
972 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
973 
974 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
975 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
976 
977 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
978 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
979 
980 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
981 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
982 
983 /*@}*/ /* end of group CMSIS_DWT */
984 
985 
986 /**
987  \ingroup CMSIS_core_register
988  \defgroup CMSIS_TPI Trace Port Interface (TPI)
989  \brief Type definitions for the Trace Port Interface (TPI)
990  @{
991  */
992 
993 /**
994  \brief Structure type to access the Trace Port Interface Register (TPI).
995  */
996 typedef struct
997 {
998  __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
999  __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1000  uint32_t RESERVED0[2U];
1001  __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1002  uint32_t RESERVED1[55U];
1003  __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1004  uint32_t RESERVED2[131U];
1005  __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1006  __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1007  __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1008  uint32_t RESERVED3[759U];
1009  __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1010  __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1011  __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1012  uint32_t RESERVED4[1U];
1013  __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1014  __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1015  __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1016  uint32_t RESERVED5[39U];
1017  __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1018  __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1019  uint32_t RESERVED7[8U];
1020  __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1021  __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1022 } TPI_Type;
1023 
1024 /* TPI Asynchronous Clock Prescaler Register Definitions */
1025 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1026 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1027 
1028 /* TPI Selected Pin Protocol Register Definitions */
1029 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1030 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1031 
1032 /* TPI Formatter and Flush Status Register Definitions */
1033 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1034 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1035 
1036 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1037 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1038 
1039 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1040 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1041 
1042 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1043 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1044 
1045 /* TPI Formatter and Flush Control Register Definitions */
1046 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1047 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1048 
1049 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1050 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1051 
1052 /* TPI TRIGGER Register Definitions */
1053 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1054 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1055 
1056 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1057 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1058 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1059 
1060 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1061 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1062 
1063 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1064 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1065 
1066 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1067 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1068 
1069 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1070 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1071 
1072 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1073 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1074 
1075 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1076 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1077 
1078 /* TPI ITATBCTR2 Register Definitions */
1079 #define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */
1080 #define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */
1081 
1082 #define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */
1083 #define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */
1084 
1085 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1086 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1087 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1088 
1089 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1090 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1091 
1092 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1093 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1094 
1095 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1096 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1097 
1098 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1099 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1100 
1101 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1102 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1103 
1104 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1105 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1106 
1107 /* TPI ITATBCTR0 Register Definitions */
1108 #define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */
1109 #define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */
1110 
1111 #define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */
1112 #define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */
1113 
1114 /* TPI Integration Mode Control Register Definitions */
1115 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1116 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1117 
1118 /* TPI DEVID Register Definitions */
1119 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1120 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1121 
1122 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1123 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1124 
1125 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1126 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1127 
1128 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1129 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1130 
1131 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1132 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1133 
1134 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1135 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1136 
1137 /* TPI DEVTYPE Register Definitions */
1138 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1139 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1140 
1141 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1142 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1143 
1144 /*@}*/ /* end of group CMSIS_TPI */
1145 
1146 
1147 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1148 /**
1149  \ingroup CMSIS_core_register
1150  \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1151  \brief Type definitions for the Memory Protection Unit (MPU)
1152  @{
1153  */
1154 
1155 /**
1156  \brief Structure type to access the Memory Protection Unit (MPU).
1157  */
1158 typedef struct
1159 {
1160  __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1161  __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1162  __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1163  __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1164  __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1165  __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1166  __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1167  __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1168  __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1169  __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1170  __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1171 } MPU_Type;
1172 
1173 #define MPU_TYPE_RALIASES 4U
1174 
1175 /* MPU Type Register Definitions */
1176 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1177 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1178 
1179 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1180 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1181 
1182 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1183 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1184 
1185 /* MPU Control Register Definitions */
1186 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1187 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1188 
1189 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1190 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1191 
1192 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1193 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1194 
1195 /* MPU Region Number Register Definitions */
1196 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1197 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1198 
1199 /* MPU Region Base Address Register Definitions */
1200 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1201 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1202 
1203 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1204 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1205 
1206 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1207 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1208 
1209 /* MPU Region Attribute and Size Register Definitions */
1210 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1211 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1212 
1213 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1214 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1215 
1216 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1217 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1218 
1219 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1220 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1221 
1222 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1223 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1224 
1225 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1226 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1227 
1228 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1229 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1230 
1231 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1232 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1233 
1234 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1235 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1236 
1237 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1238 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1239 
1240 /*@} end of group CMSIS_MPU */
1241 #endif
1242 
1243 
1244 /**
1245  \ingroup CMSIS_core_register
1246  \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1247  \brief Type definitions for the Core Debug Registers
1248  @{
1249  */
1250 
1251 /**
1252  \brief Structure type to access the Core Debug Register (CoreDebug).
1253  */
1254 typedef struct
1255 {
1256  __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1257  __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1258  __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1259  __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1260 } CoreDebug_Type;
1261 
1262 /* Debug Halting Control and Status Register Definitions */
1263 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1264 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1265 
1266 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1267 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1268 
1269 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1270 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1271 
1272 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1273 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1274 
1275 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1276 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1277 
1278 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1279 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1280 
1281 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1282 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1283 
1284 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1285 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1286 
1287 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1288 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1289 
1290 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1291 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1292 
1293 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1294 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1295 
1296 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1297 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1298 
1299 /* Debug Core Register Selector Register Definitions */
1300 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1301 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1302 
1303 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1304 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1305 
1306 /* Debug Exception and Monitor Control Register Definitions */
1307 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1308 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1309 
1310 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1311 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1312 
1313 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1314 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1315 
1316 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1317 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1318 
1319 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1320 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1321 
1322 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1323 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1324 
1325 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1326 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1327 
1328 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1329 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1330 
1331 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1332 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1333 
1334 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1335 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1336 
1337 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1338 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1339 
1340 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1341 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1342 
1343 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1344 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1345 
1346 /*@} end of group CMSIS_CoreDebug */
1347 
1348 
1349 /**
1350  \ingroup CMSIS_core_register
1351  \defgroup CMSIS_core_bitfield Core register bit field macros
1352  \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1353  @{
1354  */
1355 
1356 /**
1357  \brief Mask and shift a bit field value for use in a register bit range.
1358  \param[in] field Name of the register bit field.
1359  \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1360  \return Masked and shifted value.
1361 */
1362 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1363 
1364 /**
1365  \brief Mask and shift a register value to extract a bit filed value.
1366  \param[in] field Name of the register bit field.
1367  \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1368  \return Masked and shifted bit field value.
1369 */
1370 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1371 
1372 /*@} end of group CMSIS_core_bitfield */
1373 
1374 
1375 /**
1376  \ingroup CMSIS_core_register
1377  \defgroup CMSIS_core_base Core Definitions
1378  \brief Definitions for base addresses, unions, and structures.
1379  @{
1380  */
1381 
1382 /* Memory mapping of Core Hardware */
1383 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1384 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1385 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1386 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1387 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1388 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1389 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1390 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1391 
1392 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1393 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1394 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1395 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1396 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1397 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1398 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1399 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1400 
1401 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1402  #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1403  #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1404 #endif
1405 
1406 /*@} */
1407 
1408 
1409 
1410 /*******************************************************************************
1411  * Hardware Abstraction Layer
1412  Core Function Interface contains:
1413  - Core NVIC Functions
1414  - Core SysTick Functions
1415  - Core Debug Functions
1416  - Core Register Access Functions
1417  ******************************************************************************/
1418 /**
1419  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1420 */
1421 
1422 
1423 
1424 /* ########################## NVIC functions #################################### */
1425 /**
1426  \ingroup CMSIS_Core_FunctionInterface
1427  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1428  \brief Functions that manage interrupts and exceptions via the NVIC.
1429  @{
1430  */
1431 
1432 #ifdef CMSIS_NVIC_VIRTUAL
1433  #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1434  #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1435  #endif
1436  #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1437 #else
1438  #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
1439  #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
1440  #define NVIC_EnableIRQ __NVIC_EnableIRQ
1441  #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1442  #define NVIC_DisableIRQ __NVIC_DisableIRQ
1443  #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1444  #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1445  #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1446  #define NVIC_GetActive __NVIC_GetActive
1447  #define NVIC_SetPriority __NVIC_SetPriority
1448  #define NVIC_GetPriority __NVIC_GetPriority
1449  #define NVIC_SystemReset __NVIC_SystemReset
1450 #endif /* CMSIS_NVIC_VIRTUAL */
1451 
1452 #ifdef CMSIS_VECTAB_VIRTUAL
1453  #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1454  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1455  #endif
1456  #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1457 #else
1458  #define NVIC_SetVector __NVIC_SetVector
1459  #define NVIC_GetVector __NVIC_GetVector
1460 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1461 
1462 #define NVIC_USER_IRQ_OFFSET 16
1463 
1464 
1465 /* The following EXC_RETURN values are saved the LR on exception entry */
1466 #define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
1467 #define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
1468 #define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
1469 
1470 
1471 /**
1472  \brief Set Priority Grouping
1473  \details Sets the priority grouping field using the required unlock sequence.
1474  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1475  Only values from 0..7 are used.
1476  In case of a conflict between priority grouping and available
1477  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1478  \param [in] PriorityGroup Priority grouping field.
1479  */
1480 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1481 {
1482  uint32_t reg_value;
1483  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1484 
1485  reg_value = SCB->AIRCR; /* read old register configuration */
1486  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1487  reg_value = (reg_value |
1488  ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1489  (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
1490  SCB->AIRCR = reg_value;
1491 }
1492 
1493 
1494 /**
1495  \brief Get Priority Grouping
1496  \details Reads the priority grouping field from the NVIC Interrupt Controller.
1497  \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1498  */
1499 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
1500 {
1501  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1502 }
1503 
1504 
1505 /**
1506  \brief Enable Interrupt
1507  \details Enables a device specific interrupt in the NVIC interrupt controller.
1508  \param [in] IRQn Device specific interrupt number.
1509  \note IRQn must not be negative.
1510  */
1511 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1512 {
1513  if ((int32_t)(IRQn) >= 0)
1514  {
1515  NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1516  }
1517 }
1518 
1519 
1520 /**
1521  \brief Get Interrupt Enable status
1522  \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1523  \param [in] IRQn Device specific interrupt number.
1524  \return 0 Interrupt is not enabled.
1525  \return 1 Interrupt is enabled.
1526  \note IRQn must not be negative.
1527  */
1528 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1529 {
1530  if ((int32_t)(IRQn) >= 0)
1531  {
1532  return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1533  }
1534  else
1535  {
1536  return(0U);
1537  }
1538 }
1539 
1540 
1541 /**
1542  \brief Disable Interrupt
1543  \details Disables a device specific interrupt in the NVIC interrupt controller.
1544  \param [in] IRQn Device specific interrupt number.
1545  \note IRQn must not be negative.
1546  */
1547 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1548 {
1549  if ((int32_t)(IRQn) >= 0)
1550  {
1551  NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1552  __DSB();
1553  __ISB();
1554  }
1555 }
1556 
1557 
1558 /**
1559  \brief Get Pending Interrupt
1560  \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1561  \param [in] IRQn Device specific interrupt number.
1562  \return 0 Interrupt status is not pending.
1563  \return 1 Interrupt status is pending.
1564  \note IRQn must not be negative.
1565  */
1566 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1567 {
1568  if ((int32_t)(IRQn) >= 0)
1569  {
1570  return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1571  }
1572  else
1573  {
1574  return(0U);
1575  }
1576 }
1577 
1578 
1579 /**
1580  \brief Set Pending Interrupt
1581  \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1582  \param [in] IRQn Device specific interrupt number.
1583  \note IRQn must not be negative.
1584  */
1585 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1586 {
1587  if ((int32_t)(IRQn) >= 0)
1588  {
1589  NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1590  }
1591 }
1592 
1593 
1594 /**
1595  \brief Clear Pending Interrupt
1596  \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1597  \param [in] IRQn Device specific interrupt number.
1598  \note IRQn must not be negative.
1599  */
1600 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1601 {
1602  if ((int32_t)(IRQn) >= 0)
1603  {
1604  NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1605  }
1606 }
1607 
1608 
1609 /**
1610  \brief Get Active Interrupt
1611  \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1612  \param [in] IRQn Device specific interrupt number.
1613  \return 0 Interrupt status is not active.
1614  \return 1 Interrupt status is active.
1615  \note IRQn must not be negative.
1616  */
1617 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1618 {
1619  if ((int32_t)(IRQn) >= 0)
1620  {
1621  return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1622  }
1623  else
1624  {
1625  return(0U);
1626  }
1627 }
1628 
1629 
1630 /**
1631  \brief Set Interrupt Priority
1632  \details Sets the priority of a device specific interrupt or a processor exception.
1633  The interrupt number can be positive to specify a device specific interrupt,
1634  or negative to specify a processor exception.
1635  \param [in] IRQn Interrupt number.
1636  \param [in] priority Priority to set.
1637  \note The priority cannot be set for every processor exception.
1638  */
1639 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1640 {
1641  if ((int32_t)(IRQn) >= 0)
1642  {
1643  NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1644  }
1645  else
1646  {
1647  SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1648  }
1649 }
1650 
1651 
1652 /**
1653  \brief Get Interrupt Priority
1654  \details Reads the priority of a device specific interrupt or a processor exception.
1655  The interrupt number can be positive to specify a device specific interrupt,
1656  or negative to specify a processor exception.
1657  \param [in] IRQn Interrupt number.
1658  \return Interrupt Priority.
1659  Value is aligned automatically to the implemented priority bits of the microcontroller.
1660  */
1661 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1662 {
1663 
1664  if ((int32_t)(IRQn) >= 0)
1665  {
1666  return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1667  }
1668  else
1669  {
1670  return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1671  }
1672 }
1673 
1674 
1675 /**
1676  \brief Encode Priority
1677  \details Encodes the priority for an interrupt with the given priority group,
1678  preemptive priority value, and subpriority value.
1679  In case of a conflict between priority grouping and available
1680  priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1681  \param [in] PriorityGroup Used priority group.
1682  \param [in] PreemptPriority Preemptive priority value (starting from 0).
1683  \param [in] SubPriority Subpriority value (starting from 0).
1684  \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1685  */
1686 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1687 {
1688  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1689  uint32_t PreemptPriorityBits;
1690  uint32_t SubPriorityBits;
1691 
1692  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1693  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1694 
1695  return (
1696  ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1697  ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1698  );
1699 }
1700 
1701 
1702 /**
1703  \brief Decode Priority
1704  \details Decodes an interrupt priority value with a given priority group to
1705  preemptive priority value and subpriority value.
1706  In case of a conflict between priority grouping and available
1707  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1708  \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1709  \param [in] PriorityGroup Used priority group.
1710  \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1711  \param [out] pSubPriority Subpriority value (starting from 0).
1712  */
1713 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1714 {
1715  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1716  uint32_t PreemptPriorityBits;
1717  uint32_t SubPriorityBits;
1718 
1719  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1720  SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1721 
1722  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1723  *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1724 }
1725 
1726 
1727 /**
1728  \brief Set Interrupt Vector
1729  \details Sets an interrupt vector in SRAM based interrupt vector table.
1730  The interrupt number can be positive to specify a device specific interrupt,
1731  or negative to specify a processor exception.
1732  VTOR must been relocated to SRAM before.
1733  \param [in] IRQn Interrupt number
1734  \param [in] vector Address of interrupt handler function
1735  */
1736 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1737 {
1738  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1739  vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1740 }
1741 
1742 
1743 /**
1744  \brief Get Interrupt Vector
1745  \details Reads an interrupt vector from interrupt vector table.
1746  The interrupt number can be positive to specify a device specific interrupt,
1747  or negative to specify a processor exception.
1748  \param [in] IRQn Interrupt number.
1749  \return Address of interrupt handler function
1750  */
1751 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1752 {
1753  uint32_t *vectors = (uint32_t *)SCB->VTOR;
1754  return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1755 }
1756 
1757 
1758 /**
1759  \brief System Reset
1760  \details Initiates a system reset request to reset the MCU.
1761  */
1762 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1763 {
1764  __DSB(); /* Ensure all outstanding memory accesses included
1765  buffered write are completed before reset */
1766  SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1767  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1768  SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1769  __DSB(); /* Ensure completion of memory access */
1770 
1771  for(;;) /* wait until reset */
1772  {
1773  __NOP();
1774  }
1775 }
1776 
1777 /*@} end of CMSIS_Core_NVICFunctions */
1778 
1779 /* ########################## MPU functions #################################### */
1780 
1781 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1782 
1783 #include "mpu_armv7.h"
1784 
1785 #endif
1786 
1787 /* ########################## FPU functions #################################### */
1788 /**
1789  \ingroup CMSIS_Core_FunctionInterface
1790  \defgroup CMSIS_Core_FpuFunctions FPU Functions
1791  \brief Function that provides FPU type.
1792  @{
1793  */
1794 
1795 /**
1796  \brief get FPU type
1797  \details returns the FPU type
1798  \returns
1799  - \b 0: No FPU
1800  - \b 1: Single precision FPU
1801  - \b 2: Double + Single precision FPU
1802  */
1803 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
1804 {
1805  return 0U; /* No FPU */
1806 }
1807 
1808 
1809 /*@} end of CMSIS_Core_FpuFunctions */
1810 
1811 
1812 
1813 /* ################################## SysTick function ############################################ */
1814 /**
1815  \ingroup CMSIS_Core_FunctionInterface
1816  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1817  \brief Functions that configure the System.
1818  @{
1819  */
1820 
1821 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
1822 
1823 /**
1824  \brief System Tick Configuration
1825  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1826  Counter is in free running mode to generate periodic interrupts.
1827  \param [in] ticks Number of ticks between two interrupts.
1828  \return 0 Function succeeded.
1829  \return 1 Function failed.
1830  \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1831  function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1832  must contain a vendor-specific implementation of this function.
1833  */
1834 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1835 {
1836  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1837  {
1838  return (1UL); /* Reload value impossible */
1839  }
1840 
1841  SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1842  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1843  SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1844  SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1845  SysTick_CTRL_TICKINT_Msk |
1846  SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1847  return (0UL); /* Function successful */
1848 }
1849 
1850 #endif
1851 
1852 /*@} end of CMSIS_Core_SysTickFunctions */
1853 
1854 
1855 
1856 /* ##################################### Debug In/Output function ########################################### */
1857 /**
1858  \ingroup CMSIS_Core_FunctionInterface
1859  \defgroup CMSIS_core_DebugFunctions ITM Functions
1860  \brief Functions that access the ITM debug interface.
1861  @{
1862  */
1863 
1864 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1865 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1866 
1867 
1868 /**
1869  \brief ITM Send Character
1870  \details Transmits a character via the ITM channel 0, and
1871  \li Just returns when no debugger is connected that has booked the output.
1872  \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1873  \param [in] ch Character to transmit.
1874  \returns Character to transmit.
1875  */
1876 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1877 {
1878  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1879  ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1880  {
1881  while (ITM->PORT[0U].u32 == 0UL)
1882  {
1883  __NOP();
1884  }
1885  ITM->PORT[0U].u8 = (uint8_t)ch;
1886  }
1887  return (ch);
1888 }
1889 
1890 
1891 /**
1892  \brief ITM Receive Character
1893  \details Inputs a character via the external variable \ref ITM_RxBuffer.
1894  \return Received character.
1895  \return -1 No character pending.
1896  */
1897 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1898 {
1899  int32_t ch = -1; /* no character available */
1900 
1901  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1902  {
1903  ch = ITM_RxBuffer;
1904  ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1905  }
1906 
1907  return (ch);
1908 }
1909 
1910 
1911 /**
1912  \brief ITM Check Character
1913  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1914  \return 0 No character available.
1915  \return 1 Character available.
1916  */
1917 __STATIC_INLINE int32_t ITM_CheckChar (void)
1918 {
1919 
1920  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1921  {
1922  return (0); /* no character available */
1923  }
1924  else
1925  {
1926  return (1); /* character available */
1927  }
1928 }
1929 
1930 /*@} end of CMSIS_core_DebugFunctions */
1931 
1932 
1933 
1934 
1935 #ifdef __cplusplus
1936 }
1937 #endif
1938 
1939 #endif /* __CORE_CM3_H_DEPENDANT */
1940 
1941 #endif /* __CMSIS_GENERIC */
TPI_Type::FIFO1
const volatile uint32_t FIFO1
Definition: core_cm3.h:1014
SCB
#define SCB
Definition: core_cm3.h:1393
xPSR_Type::@27::_reserved1
uint32_t _reserved1
Definition: core_cm3.h:265
__NVIC_GetPriority
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
Get Interrupt Priority.
Definition: core_armv8mbl.h:1471
xPSR_Type::@27::N
uint32_t N
Definition: core_cm3.h:272
xPSR_Type::@27::C
uint32_t C
Definition: core_cm3.h:270
mpu_armv7.h
NVIC_DecodePriority
__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, uint32_t *const pSubPriority)
Decode Priority.
Definition: core_armv8mbl.h:1523
SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm3.h:707
__OM
#define __OM
Definition: core_cm3.h:174
xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_armv8mbl.h:281
SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm3.h:472
DWT_Type::MASK1
volatile uint32_t MASK1
Definition: core_cm3.h:864
TPI_Type::FIFO0
const volatile uint32_t FIFO0
Definition: core_cm3.h:1010
APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_armv8mbl.h:233
xPSR_Type::@27::T
uint32_t T
Definition: core_cm3.h:266
ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_armv8mml.h:1086
xPSR_Type::@27::_reserved0
uint32_t _reserved0
Definition: core_cm3.h:263
__IOM
#define __IOM
Definition: core_cm3.h:175
xPSR_Type::@27::ICI_IT_2
uint32_t ICI_IT_2
Definition: core_cm3.h:267
DWT_Type::MASK2
volatile uint32_t MASK2
Definition: core_cm3.h:868
ITM_SendChar
__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch)
ITM Send Character.
Definition: core_armv8mml.h:2862
NVIC_EncodePriority
__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Encode Priority.
Definition: core_armv8mbl.h:1496
DWT_Type::MASK0
volatile uint32_t MASK0
Definition: core_cm3.h:860
DWT_Type::MASK3
volatile uint32_t MASK3
Definition: core_cm3.h:872
ITM_CheckChar
__STATIC_INLINE int32_t ITM_CheckChar(void)
ITM Check Character.
Definition: core_armv8mml.h:2903
__NOP
#define __NOP
No Operation.
Definition: cmsis_armcc.h:387
xPSR_Type::@27::V
uint32_t V
Definition: core_cm3.h:269
ITM_Type::@29::u8
volatile uint8_t u8
Definition: core_cm3.h:750
__NVIC_GetActive
__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
Get Active Interrupt.
Definition: core_armv8mbl.h:1358
__NVIC_SetPendingIRQ
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
Set Pending Interrupt.
Definition: core_armv8mbl.h:1326
APSR_Type::@25::C
uint32_t C
Definition: core_cm3.h:213
APSR_Type::@25::N
uint32_t N
Definition: core_cm3.h:215
IPSR_Type::@26::ISR
uint32_t ISR
Definition: core_cm3.h:244
SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_armv8mbl.h:381
ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm3.h:812
SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm3.h:710
xPSR_Type::@27::ISR
uint32_t ISR
Definition: core_cm3.h:262
APSR_Type::@25::Q
uint32_t Q
Definition: core_cm3.h:211
xPSR_Type::@27::Q
uint32_t Q
Definition: core_cm3.h:268
ITM
#define ITM
Definition: core_cm3.h:1396
DWT_Type
Structure type to access the Data Watchpoint and Trace Register (DWT).
Definition: core_armv8mbl.h:610
__ISB
#define __ISB()
Instruction Synchronization Barrier.
Definition: cmsis_armcc.h:418
__NVIC_EnableIRQ
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
Enable Interrupt.
Definition: core_armv8mbl.h:1252
cmsis_version.h
CMSIS Core(M) Version definitions.
__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: stm32f103xb.h:52
__NVIC_ClearPendingIRQ
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Clear Pending Interrupt.
Definition: core_armv8mbl.h:1341
ITM_RxBuffer
volatile int32_t ITM_RxBuffer
APSR_Type::@25::V
uint32_t V
Definition: core_cm3.h:212
__IM
#define __IM
Definition: core_cm3.h:173
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f103xb.h:80
SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm3.h:717
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
TPI_Type::ITATBCTR2
const volatile uint32_t ITATBCTR2
Definition: core_cm3.h:1011
APSR_Type::@25::Z
uint32_t Z
Definition: core_cm3.h:214
CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_armv8mbl.h:320
__STATIC_INLINE
#define __STATIC_INLINE
Definition: cmsis_armcc.h:59
__NVIC_SetVector
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
Set Interrupt Vector.
Definition: core_armv8mbl.h:1547
APSR_Type::@25::_reserved0
uint32_t _reserved0
Definition: core_cm3.h:210
SCB_Type::ADR
const volatile uint32_t ADR
Definition: core_cm3.h:392
ITM_Type::@29::u16
volatile uint16_t u16
Definition: core_cm3.h:751
SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm3.h:459
TPI_Type::FSCR
const volatile uint32_t FSCR
Definition: core_cm3.h:1007
CONTROL_Type::@28::nPRIV
uint32_t nPRIV
Definition: core_cm3.h:313
__NVIC_SetPriorityGrouping
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Set Priority Grouping.
Definition: core_armv8mml.h:2116
__NVIC_DisableIRQ
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
Disable Interrupt.
Definition: core_armv8mbl.h:1288
NVIC
#define NVIC
Definition: core_cm3.h:1395
ITM_ReceiveChar
__STATIC_INLINE int32_t ITM_ReceiveChar(void)
ITM Receive Character.
Definition: core_armv8mml.h:2883
__NVIC_GetVector
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
Get Interrupt Vector.
Definition: core_armv8mbl.h:1566
ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm3.h:1865
CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_armv8mbl.h:988
IPSR_Type::@26::_reserved0
uint32_t _reserved0
Definition: core_cm3.h:245
SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm3.h:468
NVIC_SetPriority
#define NVIC_SetPriority
Definition: core_cm3.h:1447
TPI_Type
Structure type to access the Trace Port Interface Register (TPI).
Definition: core_armv8mbl.h:725
ITM_Type::@29::u32
volatile uint32_t u32
Definition: core_cm3.h:752
__NO_RETURN
#define __NO_RETURN
Definition: cmsis_armcc.h:65
SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm3.h:713
cmsis_compiler.h
CMSIS compiler generic header file.
NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_armv8mbl.h:351
__NVIC_GetPriorityGrouping
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
Get Priority Grouping.
Definition: core_armv8mml.h:2135
SCB_Type::DFR
const volatile uint32_t DFR
Definition: core_cm3.h:391
SysTick
#define SysTick
Definition: core_cm3.h:1394
NVIC_USER_IRQ_OFFSET
#define NVIC_USER_IRQ_OFFSET
Definition: core_cm3.h:1462
CONTROL_Type::@28::_reserved1
uint32_t _reserved1
Definition: core_cm3.h:315
SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_armv8mml.h:1009
SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm3.h:469
__DSB
#define __DSB()
Data Synchronization Barrier.
Definition: cmsis_armcc.h:429
__NVIC_SystemReset
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
System Reset.
Definition: core_armv8mbl.h:1581
__NVIC_SetPriority
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Set Interrupt Priority.
Definition: core_armv8mbl.h:1447
SCB_GetFPUType
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
get FPU type
Definition: core_armv8mbl.h:1791
__NVIC_GetPendingIRQ
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
Get Pending Interrupt.
Definition: core_armv8mbl.h:1307
xPSR_Type::@27::Z
uint32_t Z
Definition: core_cm3.h:271
xPSR_Type::@27::ICI_IT_1
uint32_t ICI_IT_1
Definition: core_cm3.h:264
SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_armv8mbl.h:558
IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_armv8mbl.h:263
__NVIC_GetEnableIRQ
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
Get Interrupt Enable status.
Definition: core_armv8mbl.h:1269
CONTROL_Type::@28::SPSEL
uint32_t SPSEL
Definition: core_cm3.h:314
SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm3.h:460