Functions that configure the System. More...

Modules
	ITM Functions
	Functions that access the ITM debug interface.

Variables
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t	APSR_Type::w

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t	IPSR_Type::w

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t	xPSR_Type::w

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

uint32_t	CONTROL_Type::w

volatile uint32_t	NVIC_Type::ISER [16U]

uint32_t	NVIC_Type::RESERVED0 [16U]

volatile uint32_t	NVIC_Type::ICER [16U]

uint32_t	NVIC_Type::RSERVED1 [16U]

volatile uint32_t	NVIC_Type::ISPR [16U]

uint32_t	NVIC_Type::RESERVED2 [16U]

volatile uint32_t	NVIC_Type::ICPR [16U]

uint32_t	NVIC_Type::RESERVED3 [16U]

volatile uint32_t	NVIC_Type::IABR [16U]

uint32_t	NVIC_Type::RESERVED4 [16U]

volatile uint32_t	NVIC_Type::ITNS [16U]

uint32_t	NVIC_Type::RESERVED5 [16U]

volatile uint32_t	NVIC_Type::IPR [124U]

const volatile uint32_t	SCB_Type::CPUID

volatile uint32_t	SCB_Type::ICSR

uint32_t	SCB_Type::RESERVED0

volatile uint32_t	SCB_Type::AIRCR

volatile uint32_t	SCB_Type::SCR

volatile uint32_t	SCB_Type::CCR

uint32_t	SCB_Type::RESERVED1

volatile uint32_t	SCB_Type::SHPR [2U]

volatile uint32_t	SCB_Type::SHCSR

volatile uint32_t	SysTick_Type::CTRL

volatile uint32_t	SysTick_Type::LOAD

volatile uint32_t	SysTick_Type::VAL

const volatile uint32_t	SysTick_Type::CALIB

volatile uint32_t	DWT_Type::CTRL

uint32_t	DWT_Type::RESERVED0 [6U]

const volatile uint32_t	DWT_Type::PCSR

volatile uint32_t	DWT_Type::COMP0

uint32_t	DWT_Type::RESERVED1 [1U]

volatile uint32_t	DWT_Type::FUNCTION0

uint32_t	DWT_Type::RESERVED2 [1U]

volatile uint32_t	DWT_Type::COMP1

uint32_t	DWT_Type::RESERVED3 [1U]

volatile uint32_t	DWT_Type::FUNCTION1

uint32_t	DWT_Type::RESERVED4 [1U]

volatile uint32_t	DWT_Type::COMP2

uint32_t	DWT_Type::RESERVED5 [1U]

volatile uint32_t	DWT_Type::FUNCTION2

uint32_t	DWT_Type::RESERVED6 [1U]

volatile uint32_t	DWT_Type::COMP3

uint32_t	DWT_Type::RESERVED7 [1U]

volatile uint32_t	DWT_Type::FUNCTION3

uint32_t	DWT_Type::RESERVED8 [1U]

volatile uint32_t	DWT_Type::COMP4

uint32_t	DWT_Type::RESERVED9 [1U]

volatile uint32_t	DWT_Type::FUNCTION4

uint32_t	DWT_Type::RESERVED10 [1U]

volatile uint32_t	DWT_Type::COMP5

uint32_t	DWT_Type::RESERVED11 [1U]

volatile uint32_t	DWT_Type::FUNCTION5

uint32_t	DWT_Type::RESERVED12 [1U]

volatile uint32_t	DWT_Type::COMP6

uint32_t	DWT_Type::RESERVED13 [1U]

volatile uint32_t	DWT_Type::FUNCTION6

uint32_t	DWT_Type::RESERVED14 [1U]

volatile uint32_t	DWT_Type::COMP7

uint32_t	DWT_Type::RESERVED15 [1U]

volatile uint32_t	DWT_Type::FUNCTION7

uint32_t	DWT_Type::RESERVED16 [1U]

volatile uint32_t	DWT_Type::COMP8

uint32_t	DWT_Type::RESERVED17 [1U]

volatile uint32_t	DWT_Type::FUNCTION8

uint32_t	DWT_Type::RESERVED18 [1U]

volatile uint32_t	DWT_Type::COMP9

uint32_t	DWT_Type::RESERVED19 [1U]

volatile uint32_t	DWT_Type::FUNCTION9

uint32_t	DWT_Type::RESERVED20 [1U]

volatile uint32_t	DWT_Type::COMP10

uint32_t	DWT_Type::RESERVED21 [1U]

volatile uint32_t	DWT_Type::FUNCTION10

uint32_t	DWT_Type::RESERVED22 [1U]

volatile uint32_t	DWT_Type::COMP11

uint32_t	DWT_Type::RESERVED23 [1U]

volatile uint32_t	DWT_Type::FUNCTION11

uint32_t	DWT_Type::RESERVED24 [1U]

volatile uint32_t	DWT_Type::COMP12

uint32_t	DWT_Type::RESERVED25 [1U]

volatile uint32_t	DWT_Type::FUNCTION12

uint32_t	DWT_Type::RESERVED26 [1U]

volatile uint32_t	DWT_Type::COMP13

uint32_t	DWT_Type::RESERVED27 [1U]

volatile uint32_t	DWT_Type::FUNCTION13

uint32_t	DWT_Type::RESERVED28 [1U]

volatile uint32_t	DWT_Type::COMP14

uint32_t	DWT_Type::RESERVED29 [1U]

volatile uint32_t	DWT_Type::FUNCTION14

uint32_t	DWT_Type::RESERVED30 [1U]

volatile uint32_t	DWT_Type::COMP15

uint32_t	DWT_Type::RESERVED31 [1U]

volatile uint32_t	DWT_Type::FUNCTION15

const volatile uint32_t	TPI_Type::SSPSR

volatile uint32_t	TPI_Type::CSPSR

uint32_t	TPI_Type::RESERVED0 [2U]

volatile uint32_t	TPI_Type::ACPR

uint32_t	TPI_Type::RESERVED1 [55U]

volatile uint32_t	TPI_Type::SPPR

uint32_t	TPI_Type::RESERVED2 [131U]

const volatile uint32_t	TPI_Type::FFSR

volatile uint32_t	TPI_Type::FFCR

volatile uint32_t	TPI_Type::PSCR

uint32_t	TPI_Type::RESERVED3 [809U]

volatile uint32_t	TPI_Type::LAR

const volatile uint32_t	TPI_Type::LSR

uint32_t	TPI_Type::RESERVED4 [4U]

const volatile uint32_t	TPI_Type::TYPE

const volatile uint32_t	TPI_Type::DEVTYPE

volatile uint32_t	CoreDebug_Type::DHCSR

volatile uint32_t	CoreDebug_Type::DCRSR

volatile uint32_t	CoreDebug_Type::DCRDR

volatile uint32_t	CoreDebug_Type::DEMCR

uint32_t	CoreDebug_Type::RESERVED4 [1U]

volatile uint32_t	CoreDebug_Type::DAUTHCTRL

volatile uint32_t	CoreDebug_Type::DSCSR

uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

volatile uint32_t	NVIC_Type::IP [8U]

volatile uint32_t	SCB_Type::SHP [2U]

uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::nPRIV:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

const volatile uint32_t	TPI_Type::TRIGGER

const volatile uint32_t	TPI_Type::ITFTTD0

volatile uint32_t	TPI_Type::ITATBCTR2

const volatile uint32_t	TPI_Type::ITATBCTR0

const volatile uint32_t	TPI_Type::ITFTTD1

volatile uint32_t	TPI_Type::ITCTRL

uint32_t	TPI_Type::RESERVED5 [39U]

volatile uint32_t	TPI_Type::CLAIMSET

volatile uint32_t	TPI_Type::CLAIMCLR

uint32_t	TPI_Type::RESERVED7 [8U]

const volatile uint32_t	TPI_Type::DEVID

uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

struct {
uint32_t APSR_Type::_reserved0:28

uint32_t APSR_Type::V:1

uint32_t APSR_Type::C:1

uint32_t APSR_Type::Z:1

uint32_t APSR_Type::N:1

}	APSR_Type::b

uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

struct {
uint32_t IPSR_Type::ISR:9

uint32_t IPSR_Type::_reserved0:23

}	IPSR_Type::b

uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

struct {
uint32_t xPSR_Type::ISR:9

uint32_t xPSR_Type::_reserved0:15

uint32_t xPSR_Type::T:1

uint32_t xPSR_Type::_reserved1:3

uint32_t xPSR_Type::V:1

uint32_t xPSR_Type::C:1

uint32_t xPSR_Type::Z:1

uint32_t xPSR_Type::N:1

}	xPSR_Type::b

uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

struct {
uint32_t CONTROL_Type::_reserved0:1

uint32_t CONTROL_Type::SPSEL:1

uint32_t CONTROL_Type::_reserved1:30

}	CONTROL_Type::b

volatile uint32_t	SCB_Type::SFCR

Detailed Description

Functions that configure the System.

Variable Documentation

◆ _reserved0 [1/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 203 of file core_cm0.h.

◆ _reserved0 [2/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 203 of file core_cm1.h.

◆ _reserved0 [3/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 209 of file core_sc000.h.

◆ _reserved0 [4/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 214 of file core_cm0plus.h.

◆ _reserved0 [5/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 234 of file core_cm0.h.

◆ _reserved0 [6/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 234 of file core_cm1.h.

◆ _reserved0 [7/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 237 of file core_armv8mbl.h.

◆ _reserved0 [8/25]

uint32_t APSR_Type::_reserved0

bit: 0..27 Reserved

bit: 0..15 Reserved

bit: 0..26 Reserved

Definition at line 237 of file core_armv8mbl.h.

◆ _reserved0 [9/25]

uint32_t { ... } ::_reserved0

bit: 0..27 Reserved

Definition at line 237 of file core_cm23.h.

◆ _reserved0 [10/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 240 of file core_sc000.h.

◆ _reserved0 [11/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 245 of file core_cm0plus.h.

◆ _reserved0 [12/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 252 of file core_cm0.h.

◆ _reserved0 [13/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 252 of file core_cm1.h.

◆ _reserved0 [14/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 258 of file core_sc000.h.

◆ _reserved0 [15/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 263 of file core_cm0plus.h.

◆ _reserved0 [16/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 268 of file core_armv8mbl.h.

◆ _reserved0 [17/25]

uint32_t IPSR_Type::_reserved0

bit: 9..31 Reserved

Definition at line 268 of file core_armv8mbl.h.

◆ _reserved0 [18/25]

uint32_t { ... } ::_reserved0

bit: 9..31 Reserved

Definition at line 268 of file core_cm23.h.

◆ _reserved0 [19/25]

uint32_t xPSR_Type::_reserved0

bit: 9..23 Reserved

bit: 9..15 Reserved

bit: 9 Reserved

Definition at line 286 of file core_armv8mbl.h.

◆ _reserved0 [20/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 286 of file core_armv8mbl.h.

◆ _reserved0 [21/25]

uint32_t { ... } ::_reserved0

bit: 9..23 Reserved

Definition at line 286 of file core_cm23.h.

◆ _reserved0 [22/25]

uint32_t CONTROL_Type::_reserved0

bit: 0 Reserved

bit: 3..31 Reserved

Definition at line 290 of file core_cm0.h.

◆ _reserved0 [23/25]

uint32_t { ... } ::_reserved0

bit: 0 Reserved

Definition at line 290 of file core_cm0.h.

◆ _reserved0 [24/25]

uint32_t { ... } ::_reserved0

bit: 0 Reserved

Definition at line 290 of file core_cm1.h.

◆ _reserved0 [25/25]

uint32_t { ... } ::_reserved0

bit: 0 Reserved

Definition at line 296 of file core_sc000.h.

◆ _reserved1 [1/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 254 of file core_cm0.h.

◆ _reserved1 [2/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 254 of file core_cm1.h.

◆ _reserved1 [3/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 260 of file core_sc000.h.

◆ _reserved1 [4/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 265 of file core_cm0plus.h.

◆ _reserved1 [5/14]

uint32_t xPSR_Type::_reserved1

bit: 25..27 Reserved

bit: 20..23 Reserved

bit: 16..23 Reserved

Definition at line 288 of file core_armv8mbl.h.

◆ _reserved1 [6/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 288 of file core_armv8mbl.h.

◆ _reserved1 [7/14]

uint32_t { ... } ::_reserved1

bit: 25..27 Reserved

Definition at line 288 of file core_cm23.h.

◆ _reserved1 [8/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 292 of file core_cm0.h.

◆ _reserved1 [9/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 292 of file core_cm1.h.

◆ _reserved1 [10/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 298 of file core_sc000.h.

◆ _reserved1 [11/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 303 of file core_cm0plus.h.

◆ _reserved1 [12/14]

uint32_t CONTROL_Type::_reserved1

bit: 2..31 Reserved

bit: 4..31 Reserved

Definition at line 326 of file core_armv8mbl.h.

◆ _reserved1 [13/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 326 of file core_armv8mbl.h.

◆ _reserved1 [14/14]

uint32_t { ... } ::_reserved1

bit: 2..31 Reserved

Definition at line 326 of file core_cm23.h.

◆ ACPR

volatile uint32_t TPI_Type::ACPR

Defines 'read / write' structure member permissions Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register

Definition at line 730 of file core_armv8mbl.h.

◆ AIRCR

volatile uint32_t SCB_Type::AIRCR

Defines 'read / write' structure member permissions Offset: 0x00C (R/W) Application Interrupt and Reset Control Register

Definition at line 390 of file core_armv8mbl.h.

◆ b [1/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [2/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [3/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [4/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [5/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [6/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [7/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [8/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [9/24]

struct { ... } APSR_Type::b

Structure used for bit access

◆ b [10/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [11/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [12/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [13/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [14/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [15/24]

struct { ... } IPSR_Type::b

Structure used for bit access

◆ b [16/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [17/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [18/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [19/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [20/24]

struct { ... } xPSR_Type::b

Structure used for bit access

◆ b [21/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [22/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [23/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ b [24/24]

struct { ... } CONTROL_Type::b

Structure used for bit access

◆ C [1/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 205 of file core_cm0.h.

◆ C [2/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 205 of file core_cm1.h.

◆ C [3/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 211 of file core_sc000.h.

◆ C [4/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 216 of file core_cm0plus.h.

◆ C [5/14]

uint32_t APSR_Type::C

bit: 29 Carry condition code flag

Definition at line 239 of file core_armv8mbl.h.

◆ C [6/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 239 of file core_cm23.h.

◆ C [7/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 239 of file core_armv8mbl.h.

◆ C [8/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 256 of file core_cm0.h.

◆ C [9/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 256 of file core_cm1.h.

◆ C [10/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 262 of file core_sc000.h.

◆ C [11/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 267 of file core_cm0plus.h.

◆ C [12/14]

uint32_t xPSR_Type::C

bit: 29 Carry condition code flag

Definition at line 290 of file core_armv8mbl.h.

◆ C [13/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 290 of file core_armv8mbl.h.

◆ C [14/14]

uint32_t { ... } ::C

bit: 29 Carry condition code flag

Definition at line 290 of file core_cm23.h.

◆ CALIB

const volatile uint32_t SysTick_Type::CALIB

Defines 'read only' structure member permissions Offset: 0x00C (R/ ) SysTick Calibration Register

Definition at line 563 of file core_armv8mbl.h.

◆ CCR

volatile uint32_t SCB_Type::CCR

Defines 'read / write' structure member permissions Offset: 0x014 (R/W) Configuration Control Register

Definition at line 392 of file core_armv8mbl.h.

◆ CLAIMCLR

volatile uint32_t TPI_Type::CLAIMCLR

Defines 'read / write' structure member permissions Offset: 0xFA4 (R/W) Claim tag clear

Definition at line 747 of file core_cm23.h.

◆ CLAIMSET

volatile uint32_t TPI_Type::CLAIMSET

Defines 'read / write' structure member permissions Offset: 0xFA0 (R/W) Claim tag set

Definition at line 746 of file core_cm23.h.

◆ COMP0

volatile uint32_t DWT_Type::COMP0

Defines 'read / write' structure member permissions Offset: 0x020 (R/W) Comparator Register 0

Definition at line 615 of file core_armv8mbl.h.

◆ COMP1

volatile uint32_t DWT_Type::COMP1

Defines 'read / write' structure member permissions Offset: 0x030 (R/W) Comparator Register 1

Definition at line 619 of file core_armv8mbl.h.

◆ COMP10

volatile uint32_t DWT_Type::COMP10

Defines 'read / write' structure member permissions Offset: 0x0C0 (R/W) Comparator Register 10

Definition at line 655 of file core_armv8mbl.h.

◆ COMP11

volatile uint32_t DWT_Type::COMP11

Defines 'read / write' structure member permissions Offset: 0x0D0 (R/W) Comparator Register 11

Definition at line 659 of file core_armv8mbl.h.

◆ COMP12

volatile uint32_t DWT_Type::COMP12

Defines 'read / write' structure member permissions Offset: 0x0E0 (R/W) Comparator Register 12

Definition at line 663 of file core_armv8mbl.h.

◆ COMP13

volatile uint32_t DWT_Type::COMP13

Defines 'read / write' structure member permissions Offset: 0x0F0 (R/W) Comparator Register 13

Definition at line 667 of file core_armv8mbl.h.

◆ COMP14

volatile uint32_t DWT_Type::COMP14

Defines 'read / write' structure member permissions Offset: 0x100 (R/W) Comparator Register 14

Definition at line 671 of file core_armv8mbl.h.

◆ COMP15

volatile uint32_t DWT_Type::COMP15

Defines 'read / write' structure member permissions Offset: 0x110 (R/W) Comparator Register 15

Definition at line 675 of file core_armv8mbl.h.

◆ COMP2

volatile uint32_t DWT_Type::COMP2

Defines 'read / write' structure member permissions Offset: 0x040 (R/W) Comparator Register 2

Definition at line 623 of file core_armv8mbl.h.

◆ COMP3

volatile uint32_t DWT_Type::COMP3

Defines 'read / write' structure member permissions Offset: 0x050 (R/W) Comparator Register 3

Definition at line 627 of file core_armv8mbl.h.

◆ COMP4

volatile uint32_t DWT_Type::COMP4

Defines 'read / write' structure member permissions Offset: 0x060 (R/W) Comparator Register 4

Definition at line 631 of file core_armv8mbl.h.

◆ COMP5

volatile uint32_t DWT_Type::COMP5

Defines 'read / write' structure member permissions Offset: 0x070 (R/W) Comparator Register 5

Definition at line 635 of file core_armv8mbl.h.

◆ COMP6

volatile uint32_t DWT_Type::COMP6

Defines 'read / write' structure member permissions Offset: 0x080 (R/W) Comparator Register 6

Definition at line 639 of file core_armv8mbl.h.

◆ COMP7

volatile uint32_t DWT_Type::COMP7

Defines 'read / write' structure member permissions Offset: 0x090 (R/W) Comparator Register 7

Definition at line 643 of file core_armv8mbl.h.

◆ COMP8

volatile uint32_t DWT_Type::COMP8

Defines 'read / write' structure member permissions Offset: 0x0A0 (R/W) Comparator Register 8

Definition at line 647 of file core_armv8mbl.h.

◆ COMP9

volatile uint32_t DWT_Type::COMP9

Defines 'read / write' structure member permissions Offset: 0x0B0 (R/W) Comparator Register 9

Definition at line 651 of file core_armv8mbl.h.

◆ CPUID

const volatile uint32_t SCB_Type::CPUID

Defines 'read only' structure member permissions Offset: 0x000 (R/ ) CPUID Base Register

Definition at line 383 of file core_armv8mbl.h.

◆ CSPSR

volatile uint32_t TPI_Type::CSPSR

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) Current Parallel Port Sizes Register

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) Current Parallel Port Size Register

Definition at line 728 of file core_armv8mbl.h.

◆ CTRL [1/2]

volatile uint32_t SysTick_Type::CTRL

Defines 'read / write' structure member permissions Offset: 0x000 (R/W) SysTick Control and Status Register

Definition at line 560 of file core_armv8mbl.h.

◆ CTRL [2/2]

volatile uint32_t DWT_Type::CTRL

Defines 'read / write' structure member permissions Offset: 0x000 (R/W) Control Register

Definition at line 612 of file core_armv8mbl.h.

◆ DAUTHCTRL

volatile uint32_t CoreDebug_Type::DAUTHCTRL

Defines 'read / write' structure member permissions Offset: 0x014 (R/W) Debug Authentication Control Register

Definition at line 995 of file core_armv8mbl.h.

◆ DCRDR

volatile uint32_t CoreDebug_Type::DCRDR

Defines 'read / write' structure member permissions Offset: 0x008 (R/W) Debug Core Register Data Register

Definition at line 992 of file core_armv8mbl.h.

◆ DCRSR

volatile uint32_t CoreDebug_Type::DCRSR

Defines 'write only' structure member permissions Offset: 0x004 ( /W) Debug Core Register Selector Register

Definition at line 991 of file core_armv8mbl.h.

◆ DEMCR

volatile uint32_t CoreDebug_Type::DEMCR

Defines 'read / write' structure member permissions Offset: 0x00C (R/W) Debug Exception and Monitor Control Register

Definition at line 993 of file core_armv8mbl.h.

◆ DEVID

const volatile uint32_t TPI_Type::DEVID

Defines 'read only' structure member permissions Offset: 0xFC8 (R/ ) Device Configuration Register

Defines 'read only' structure member permissions Offset: 0xFC8 (R/ ) TPIU_DEVID

Definition at line 749 of file core_cm23.h.

◆ DEVTYPE

const volatile uint32_t TPI_Type::DEVTYPE

Defines 'read only' structure member permissions Offset: 0xFCC (R/ ) Device Type Register

Defines 'read only' structure member permissions Offset: 0xFCC (R/ ) Device Type Identifier Register

Defines 'read only' structure member permissions Offset: 0xFCC (R/ ) TPIU_DEVTYPE

Definition at line 742 of file core_armv8mbl.h.

◆ DHCSR

volatile uint32_t CoreDebug_Type::DHCSR

Defines 'read / write' structure member permissions Offset: 0x000 (R/W) Debug Halting Control and Status Register

Definition at line 990 of file core_armv8mbl.h.

◆ DSCSR

volatile uint32_t CoreDebug_Type::DSCSR

Defines 'read / write' structure member permissions Offset: 0x018 (R/W) Debug Security Control and Status Register

Definition at line 996 of file core_armv8mbl.h.

◆ FFCR

volatile uint32_t TPI_Type::FFCR

Defines 'read / write' structure member permissions Offset: 0x304 (R/W) Formatter and Flush Control Register

Definition at line 735 of file core_armv8mbl.h.

◆ FFSR

const volatile uint32_t TPI_Type::FFSR

Defines 'read only' structure member permissions Offset: 0x300 (R/ ) Formatter and Flush Status Register

Definition at line 734 of file core_armv8mbl.h.

◆ FUNCTION0

volatile uint32_t DWT_Type::FUNCTION0

Defines 'read / write' structure member permissions Offset: 0x028 (R/W) Function Register 0

Definition at line 617 of file core_armv8mbl.h.

◆ FUNCTION1

volatile uint32_t DWT_Type::FUNCTION1

Defines 'read / write' structure member permissions Offset: 0x038 (R/W) Function Register 1

Definition at line 621 of file core_armv8mbl.h.

◆ FUNCTION10

volatile uint32_t DWT_Type::FUNCTION10

Defines 'read / write' structure member permissions Offset: 0x0C8 (R/W) Function Register 10

Definition at line 657 of file core_armv8mbl.h.

◆ FUNCTION11

volatile uint32_t DWT_Type::FUNCTION11

Defines 'read / write' structure member permissions Offset: 0x0D8 (R/W) Function Register 11

Definition at line 661 of file core_armv8mbl.h.

◆ FUNCTION12

volatile uint32_t DWT_Type::FUNCTION12

Defines 'read / write' structure member permissions Offset: 0x0E8 (R/W) Function Register 12

Definition at line 665 of file core_armv8mbl.h.

◆ FUNCTION13

volatile uint32_t DWT_Type::FUNCTION13

Defines 'read / write' structure member permissions Offset: 0x0F8 (R/W) Function Register 13

Definition at line 669 of file core_armv8mbl.h.

◆ FUNCTION14

volatile uint32_t DWT_Type::FUNCTION14

Defines 'read / write' structure member permissions Offset: 0x108 (R/W) Function Register 14

Definition at line 673 of file core_armv8mbl.h.

◆ FUNCTION15

volatile uint32_t DWT_Type::FUNCTION15

Defines 'read / write' structure member permissions Offset: 0x118 (R/W) Function Register 15

Definition at line 677 of file core_armv8mbl.h.

◆ FUNCTION2

volatile uint32_t DWT_Type::FUNCTION2

Defines 'read / write' structure member permissions Offset: 0x048 (R/W) Function Register 2

Definition at line 625 of file core_armv8mbl.h.

◆ FUNCTION3

volatile uint32_t DWT_Type::FUNCTION3

Defines 'read / write' structure member permissions Offset: 0x058 (R/W) Function Register 3

Definition at line 629 of file core_armv8mbl.h.

◆ FUNCTION4

volatile uint32_t DWT_Type::FUNCTION4

Defines 'read / write' structure member permissions Offset: 0x068 (R/W) Function Register 4

Definition at line 633 of file core_armv8mbl.h.

◆ FUNCTION5

volatile uint32_t DWT_Type::FUNCTION5

Defines 'read / write' structure member permissions Offset: 0x078 (R/W) Function Register 5

Definition at line 637 of file core_armv8mbl.h.

◆ FUNCTION6

volatile uint32_t DWT_Type::FUNCTION6

Defines 'read / write' structure member permissions Offset: 0x088 (R/W) Function Register 6

Definition at line 641 of file core_armv8mbl.h.

◆ FUNCTION7

volatile uint32_t DWT_Type::FUNCTION7

Defines 'read / write' structure member permissions Offset: 0x098 (R/W) Function Register 7

Definition at line 645 of file core_armv8mbl.h.

◆ FUNCTION8

volatile uint32_t DWT_Type::FUNCTION8

Defines 'read / write' structure member permissions Offset: 0x0A8 (R/W) Function Register 8

Definition at line 649 of file core_armv8mbl.h.

◆ FUNCTION9

volatile uint32_t DWT_Type::FUNCTION9

Defines 'read / write' structure member permissions Offset: 0x0B8 (R/W) Function Register 9

Definition at line 653 of file core_armv8mbl.h.

◆ IABR

volatile uint32_t NVIC_Type::IABR

Defines 'read / write' structure member permissions Offset: 0x200 (R/W) Interrupt Active bit Register

Definition at line 361 of file core_armv8mbl.h.

◆ ICER

volatile uint32_t NVIC_Type::ICER

Defines 'read / write' structure member permissions Offset: 0x080 (R/W) Interrupt Clear Enable Register

Definition at line 355 of file core_armv8mbl.h.

◆ ICPR

volatile uint32_t NVIC_Type::ICPR

Defines 'read / write' structure member permissions Offset: 0x180 (R/W) Interrupt Clear Pending Register

Definition at line 359 of file core_armv8mbl.h.

◆ ICSR

volatile uint32_t SCB_Type::ICSR

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) Interrupt Control and State Register

Definition at line 384 of file core_armv8mbl.h.

◆ IP

volatile uint8_t NVIC_Type::IP

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 325 of file core_cm0.h.

◆ IPR

volatile uint8_t NVIC_Type::IPR

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register

Defines 'read / write' structure member permissions Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)

Definition at line 365 of file core_armv8mbl.h.

◆ ISER

volatile uint32_t NVIC_Type::ISER

Defines 'read / write' structure member permissions Offset: 0x000 (R/W) Interrupt Set Enable Register

Definition at line 353 of file core_armv8mbl.h.

◆ ISPR

volatile uint32_t NVIC_Type::ISPR

Defines 'read / write' structure member permissions Offset: 0x100 (R/W) Interrupt Set Pending Register

Definition at line 357 of file core_armv8mbl.h.

◆ ISR [1/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 233 of file core_cm0.h.

◆ ISR [2/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 233 of file core_cm1.h.

◆ ISR [3/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 239 of file core_sc000.h.

◆ ISR [4/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 244 of file core_cm0plus.h.

◆ ISR [5/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 251 of file core_cm0.h.

◆ ISR [6/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 251 of file core_cm1.h.

◆ ISR [7/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 257 of file core_sc000.h.

◆ ISR [8/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 262 of file core_cm0plus.h.

◆ ISR [9/14]

uint32_t IPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 267 of file core_armv8mbl.h.

◆ ISR [10/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 267 of file core_cm23.h.

◆ ISR [11/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 267 of file core_armv8mbl.h.

◆ ISR [12/14]

uint32_t xPSR_Type::ISR

bit: 0.. 8 Exception number

Definition at line 285 of file core_armv8mbl.h.

◆ ISR [13/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 285 of file core_armv8mbl.h.

◆ ISR [14/14]

uint32_t { ... } ::ISR

bit: 0.. 8 Exception number

Definition at line 285 of file core_cm23.h.

◆ ITATBCTR0

const volatile uint32_t TPI_Type::ITATBCTR0

Defines 'read only' structure member permissions Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0

Defines 'read only' structure member permissions Offset: 0xEF8 (R/ ) ITATBCTR0

Definition at line 742 of file core_cm23.h.

◆ ITATBCTR2

const volatile uint32_t TPI_Type::ITATBCTR2

Defines 'read / write' structure member permissions Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2

Defines 'read only' structure member permissions Offset: 0xEF0 (R/ ) ITATBCTR2

Definition at line 740 of file core_cm23.h.

◆ ITCTRL

volatile uint32_t TPI_Type::ITCTRL

Defines 'read / write' structure member permissions Offset: 0xF00 (R/W) Integration Mode Control

Definition at line 744 of file core_cm23.h.

◆ ITFTTD0

const volatile uint32_t TPI_Type::ITFTTD0

Defines 'read only' structure member permissions Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register

Definition at line 739 of file core_cm23.h.

◆ ITFTTD1

const volatile uint32_t TPI_Type::ITFTTD1

Defines 'read only' structure member permissions Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register

Definition at line 743 of file core_cm23.h.

◆ ITNS

volatile uint32_t NVIC_Type::ITNS

Defines 'read / write' structure member permissions Offset: 0x280 (R/W) Interrupt Non-Secure State Register

Definition at line 363 of file core_armv8mbl.h.

◆ LAR

volatile uint32_t TPI_Type::LAR

Defines 'write only' structure member permissions Offset: 0xFB0 ( /W) Software Lock Access Register

Definition at line 738 of file core_armv8mbl.h.

◆ LOAD

volatile uint32_t SysTick_Type::LOAD

Defines 'read / write' structure member permissions Offset: 0x004 (R/W) SysTick Reload Value Register

Definition at line 561 of file core_armv8mbl.h.

◆ LSR

const volatile uint32_t TPI_Type::LSR

Defines 'read only' structure member permissions Offset: 0xFB4 (R/ ) Software Lock Status Register

Definition at line 739 of file core_armv8mbl.h.

◆ N [1/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 207 of file core_cm0.h.

◆ N [2/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 207 of file core_cm1.h.

◆ N [3/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 213 of file core_sc000.h.

◆ N [4/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 218 of file core_cm0plus.h.

◆ N [5/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 241 of file core_armv8mbl.h.

◆ N [6/14]

uint32_t APSR_Type::N

bit: 31 Negative condition code flag

Definition at line 241 of file core_armv8mbl.h.

◆ N [7/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 241 of file core_cm23.h.

◆ N [8/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 258 of file core_cm0.h.

◆ N [9/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 258 of file core_cm1.h.

◆ N [10/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 264 of file core_sc000.h.

◆ N [11/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 269 of file core_cm0plus.h.

◆ N [12/14]

uint32_t xPSR_Type::N

bit: 31 Negative condition code flag

Definition at line 292 of file core_armv8mbl.h.

◆ N [13/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 292 of file core_armv8mbl.h.

◆ N [14/14]

uint32_t { ... } ::N

bit: 31 Negative condition code flag

Definition at line 292 of file core_cm23.h.

◆ nPRIV [1/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 301 of file core_cm0plus.h.

◆ nPRIV [2/4]

uint32_t CONTROL_Type::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 324 of file core_armv8mbl.h.

◆ nPRIV [3/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 324 of file core_armv8mbl.h.

◆ nPRIV [4/4]

uint32_t { ... } ::nPRIV

bit: 0 Execution privilege in Thread mode

Definition at line 324 of file core_cm23.h.

◆ PCSR

const volatile uint32_t DWT_Type::PCSR

Defines 'read only' structure member permissions Offset: 0x01C (R/ ) Program Counter Sample Register

Definition at line 614 of file core_armv8mbl.h.

◆ PSCR

volatile uint32_t TPI_Type::PSCR

Defines 'read / write' structure member permissions Offset: 0x308 (R/W) Periodic Synchronization Control Register

Definition at line 736 of file core_armv8mbl.h.

◆ RESERVED0 [1/4]

uint32_t SCB_Type::RESERVED0

Definition at line 388 of file core_armv8mbl.h.

◆ RESERVED0 [2/4]

uint32_t NVIC_Type::RESERVED0

Definition at line 354 of file core_armv8mbl.h.

◆ RESERVED0 [3/4]

uint32_t TPI_Type::RESERVED0

Definition at line 729 of file core_armv8mbl.h.

◆ RESERVED0 [4/4]

uint32_t DWT_Type::RESERVED0

Definition at line 613 of file core_armv8mbl.h.

◆ RESERVED1 [1/3]

uint32_t SCB_Type::RESERVED1

Definition at line 393 of file core_armv8mbl.h.

◆ RESERVED1 [2/3]

uint32_t DWT_Type::RESERVED1

Definition at line 616 of file core_armv8mbl.h.

◆ RESERVED1 [3/3]

uint32_t TPI_Type::RESERVED1

Definition at line 731 of file core_armv8mbl.h.

◆ RESERVED10

uint32_t DWT_Type::RESERVED10

Definition at line 634 of file core_armv8mbl.h.

◆ RESERVED11

uint32_t DWT_Type::RESERVED11

Definition at line 636 of file core_armv8mbl.h.

◆ RESERVED12

uint32_t DWT_Type::RESERVED12

Definition at line 638 of file core_armv8mbl.h.

◆ RESERVED13

uint32_t DWT_Type::RESERVED13

Definition at line 640 of file core_armv8mbl.h.

◆ RESERVED14

uint32_t DWT_Type::RESERVED14

Definition at line 642 of file core_armv8mbl.h.

◆ RESERVED15

uint32_t DWT_Type::RESERVED15

Definition at line 644 of file core_armv8mbl.h.

◆ RESERVED16

uint32_t DWT_Type::RESERVED16

Definition at line 646 of file core_armv8mbl.h.

◆ RESERVED17

uint32_t DWT_Type::RESERVED17

Definition at line 648 of file core_armv8mbl.h.

◆ RESERVED18

uint32_t DWT_Type::RESERVED18

Definition at line 650 of file core_armv8mbl.h.

◆ RESERVED19

uint32_t DWT_Type::RESERVED19

Definition at line 652 of file core_armv8mbl.h.

◆ RESERVED2 [1/3]

uint32_t TPI_Type::RESERVED2

Definition at line 733 of file core_armv8mbl.h.

◆ RESERVED2 [2/3]

uint32_t NVIC_Type::RESERVED2

Definition at line 358 of file core_armv8mbl.h.

◆ RESERVED2 [3/3]

uint32_t DWT_Type::RESERVED2

Definition at line 618 of file core_armv8mbl.h.

◆ RESERVED20

uint32_t DWT_Type::RESERVED20

Definition at line 654 of file core_armv8mbl.h.

◆ RESERVED21

uint32_t DWT_Type::RESERVED21

Definition at line 656 of file core_armv8mbl.h.

◆ RESERVED22

uint32_t DWT_Type::RESERVED22

Definition at line 658 of file core_armv8mbl.h.

◆ RESERVED23

uint32_t DWT_Type::RESERVED23

Definition at line 660 of file core_armv8mbl.h.

◆ RESERVED24

uint32_t DWT_Type::RESERVED24

Definition at line 662 of file core_armv8mbl.h.

◆ RESERVED25

uint32_t DWT_Type::RESERVED25

Definition at line 664 of file core_armv8mbl.h.

◆ RESERVED26

uint32_t DWT_Type::RESERVED26

Definition at line 666 of file core_armv8mbl.h.

◆ RESERVED27

uint32_t DWT_Type::RESERVED27

Definition at line 668 of file core_armv8mbl.h.

◆ RESERVED28

uint32_t DWT_Type::RESERVED28

Definition at line 670 of file core_armv8mbl.h.

◆ RESERVED29

uint32_t DWT_Type::RESERVED29

Definition at line 672 of file core_armv8mbl.h.

◆ RESERVED3 [1/3]

uint32_t NVIC_Type::RESERVED3

Definition at line 360 of file core_armv8mbl.h.

◆ RESERVED3 [2/3]

uint32_t DWT_Type::RESERVED3

Definition at line 620 of file core_armv8mbl.h.

◆ RESERVED3 [3/3]

uint32_t TPI_Type::RESERVED3

Definition at line 737 of file core_armv8mbl.h.

◆ RESERVED30

uint32_t DWT_Type::RESERVED30

Definition at line 674 of file core_armv8mbl.h.

◆ RESERVED31

uint32_t DWT_Type::RESERVED31

Definition at line 676 of file core_armv8mbl.h.

◆ RESERVED4 [1/4]

uint32_t NVIC_Type::RESERVED4

Definition at line 362 of file core_armv8mbl.h.

◆ RESERVED4 [2/4]

uint32_t DWT_Type::RESERVED4

Definition at line 622 of file core_armv8mbl.h.

◆ RESERVED4 [3/4]

uint32_t CoreDebug_Type::RESERVED4

Definition at line 994 of file core_armv8mbl.h.

◆ RESERVED4 [4/4]

uint32_t TPI_Type::RESERVED4

Definition at line 740 of file core_armv8mbl.h.

◆ RESERVED5 [1/3]

uint32_t NVIC_Type::RESERVED5

Definition at line 364 of file core_armv8mbl.h.

◆ RESERVED5 [2/3]

uint32_t DWT_Type::RESERVED5

Definition at line 624 of file core_armv8mbl.h.

◆ RESERVED5 [3/3]

uint32_t TPI_Type::RESERVED5

Definition at line 745 of file core_cm23.h.

◆ RESERVED6

uint32_t DWT_Type::RESERVED6

Definition at line 626 of file core_armv8mbl.h.

◆ RESERVED7 [1/2]

uint32_t DWT_Type::RESERVED7

Definition at line 628 of file core_armv8mbl.h.

◆ RESERVED7 [2/2]

uint32_t TPI_Type::RESERVED7

Definition at line 748 of file core_cm23.h.

◆ RESERVED8

uint32_t DWT_Type::RESERVED8

Definition at line 630 of file core_armv8mbl.h.

◆ RESERVED9

uint32_t DWT_Type::RESERVED9

Definition at line 632 of file core_armv8mbl.h.

◆ RSERVED1

uint32_t NVIC_Type::RSERVED1

Definition at line 356 of file core_armv8mbl.h.

◆ SCR

volatile uint32_t SCB_Type::SCR

Defines 'read / write' structure member permissions Offset: 0x010 (R/W) System Control Register

Definition at line 391 of file core_armv8mbl.h.

◆ SFCR

volatile uint32_t SCB_Type::SFCR

Defines 'read / write' structure member permissions Offset: 0x290 (R/W) Security Features Control Register

Definition at line 359 of file core_sc000.h.

◆ SHCSR

volatile uint32_t SCB_Type::SHCSR

Defines 'read / write' structure member permissions Offset: 0x024 (R/W) System Handler Control and State Register

Definition at line 395 of file core_armv8mbl.h.

◆ SHP

volatile uint8_t SCB_Type::SHP

Defines 'read / write' structure member permissions Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Defines 'read / write' structure member permissions Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 350 of file core_cm0.h.

◆ SHPR

volatile uint8_t SCB_Type::SHPR

Defines 'read / write' structure member permissions Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED

Defines 'read / write' structure member permissions Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)

Definition at line 394 of file core_armv8mbl.h.

◆ SPPR

volatile uint32_t TPI_Type::SPPR

Defines 'read / write' structure member permissions Offset: 0x0F0 (R/W) Selected Pin Protocol Register

Definition at line 732 of file core_armv8mbl.h.

◆ SPSEL [1/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 291 of file core_cm0.h.

◆ SPSEL [2/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 291 of file core_cm1.h.

◆ SPSEL [3/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 297 of file core_sc000.h.

◆ SPSEL [4/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack to be used

Definition at line 302 of file core_cm0plus.h.

◆ SPSEL [5/7]

uint32_t CONTROL_Type::SPSEL

bit: 1 Stack-pointer select

bit: 1 Stack to be used

Definition at line 325 of file core_armv8mbl.h.

◆ SPSEL [6/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack-pointer select

Definition at line 325 of file core_armv8mbl.h.

◆ SPSEL [7/7]

uint32_t { ... } ::SPSEL

bit: 1 Stack-pointer select

Definition at line 325 of file core_cm23.h.

◆ SSPSR

const volatile uint32_t TPI_Type::SSPSR

Defines 'read only' structure member permissions Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register

Defines 'read only' structure member permissions Offset: 0x000 (R/ ) Supported Parallel Port Size Register

Definition at line 727 of file core_armv8mbl.h.

◆ T [1/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 253 of file core_cm1.h.

◆ T [2/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 253 of file core_cm0.h.

◆ T [3/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 259 of file core_sc000.h.

◆ T [4/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 264 of file core_cm0plus.h.

◆ T [5/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 287 of file core_armv8mbl.h.

◆ T [6/7]

uint32_t xPSR_Type::T

bit: 24 Thumb bit (read 0)

bit: 24 Thumb bit

Definition at line 287 of file core_armv8mbl.h.

◆ T [7/7]

uint32_t { ... } ::T

bit: 24 Thumb bit (read 0)

Definition at line 287 of file core_cm23.h.

◆ TRIGGER

const volatile uint32_t TPI_Type::TRIGGER

Defines 'read only' structure member permissions Offset: 0xEE8 (R/ ) TRIGGER Register

Definition at line 738 of file core_cm23.h.

◆ TYPE

const volatile uint32_t TPI_Type::TYPE

Defines 'read only' structure member permissions Offset: 0xFC8 (R/ ) Device Identifier Register

Definition at line 741 of file core_armv8mbl.h.

◆ V [1/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 204 of file core_cm1.h.

◆ V [2/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 204 of file core_cm0.h.

◆ V [3/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 210 of file core_sc000.h.

◆ V [4/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 215 of file core_cm0plus.h.

◆ V [5/14]

uint32_t APSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 238 of file core_armv8mbl.h.

◆ V [6/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 238 of file core_armv8mbl.h.

◆ V [7/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 238 of file core_cm23.h.

◆ V [8/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 255 of file core_cm1.h.

◆ V [9/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 255 of file core_cm0.h.

◆ V [10/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 261 of file core_sc000.h.

◆ V [11/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 266 of file core_cm0plus.h.

◆ V [12/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 289 of file core_cm23.h.

◆ V [13/14]

uint32_t xPSR_Type::V

bit: 28 Overflow condition code flag

Definition at line 289 of file core_armv8mbl.h.

◆ V [14/14]

uint32_t { ... } ::V

bit: 28 Overflow condition code flag

Definition at line 289 of file core_armv8mbl.h.

◆ VAL

volatile uint32_t SysTick_Type::VAL

Defines 'read / write' structure member permissions Offset: 0x008 (R/W) SysTick Current Value Register

Definition at line 562 of file core_armv8mbl.h.

◆ w [1/4]

uint32_t APSR_Type::w

Type used for word access

Definition at line 243 of file core_armv8mbl.h.

◆ w [2/4]

uint32_t IPSR_Type::w

Type used for word access

Definition at line 270 of file core_armv8mbl.h.

◆ w [3/4]

uint32_t xPSR_Type::w

Type used for word access

Definition at line 294 of file core_armv8mbl.h.

◆ w [4/4]

uint32_t CONTROL_Type::w

Type used for word access

Definition at line 328 of file core_armv8mbl.h.