Access to dedicated instructions. More...

Modules
	CMSIS SIMD Intrinsics
	Access to dedicated SIMD instructions.

Macros
#define	__NOP __nop
	No Operation. More...

#define	__WFI __wfi
	Wait For Interrupt. More...

#define	__WFE __wfe
	Wait For Event. More...

#define	__SEV __sev
	Send Event. More...

#define	__ISB()
	Instruction Synchronization Barrier. More...

#define	__DSB()
	Data Synchronization Barrier. More...

#define	__DMB()
	Data Memory Barrier. More...

#define	__REV __rev
	Reverse byte order (32 bit) More...

#define	__ROR __ror
	Rotate Right in unsigned value (32 bit) More...

#define	__BKPT(value) __breakpoint(value)
	Breakpoint. More...

#define	__CLZ __clz
	Count leading zeros. More...

#define	__CMSIS_GCC_OUT_REG(r) "=r" (r)

#define	__CMSIS_GCC_USE_REG(r) "r" (r)

#define	__NOP __builtin_arm_nop
	No Operation. More...

#define	__WFI __builtin_arm_wfi
	Wait For Interrupt. More...

#define	__WFE __builtin_arm_wfe
	Wait For Event. More...

#define	__SEV __builtin_arm_sev
	Send Event. More...

#define	__ISB() __builtin_arm_isb(0xF);
	Instruction Synchronization Barrier. More...

#define	__DSB() __builtin_arm_dsb(0xF);
	Data Synchronization Barrier. More...

#define	__DMB() __builtin_arm_dmb(0xF);
	Data Memory Barrier. More...

#define	__REV(value) __builtin_bswap32(value)
	Reverse byte order (32 bit) More...

#define	__REV16(value) __ROR(__REV(value), 16)
	Reverse byte order (16 bit) More...

#define	__REVSH(value) (int16_t)__builtin_bswap16(value)
	Reverse byte order (16 bit) More...

#define	__BKPT(value) __ASM volatile ("bkpt "#value)
	Breakpoint. More...

#define	__RBIT __builtin_arm_rbit
	Reverse bit order of value. More...

#define	__CLZ (uint8_t)__builtin_clz
	Count leading zeros. More...

#define	__CMSIS_GCC_OUT_REG(r) "=r" (r)

#define	__CMSIS_GCC_RW_REG(r) "+r" (r)

#define	__CMSIS_GCC_USE_REG(r) "r" (r)

#define	__NOP() __ASM volatile ("nop")
	No Operation. More...

#define	__WFI() __ASM volatile ("wfi")
	Wait For Interrupt. More...

#define	__WFE() __ASM volatile ("wfe")
	Wait For Event. More...

#define	__SEV() __ASM volatile ("sev")
	Send Event. More...

#define	__BKPT(value) __ASM volatile ("bkpt "#value)
	Breakpoint. More...

#define	__CLZ (uint8_t)__builtin_clz
	Count leading zeros. More...

Functions
	__attribute__ ((section(".rev16_text"))) static __inline __asm uint32_t __REV16(uint32_t value)
	Reverse byte order (16 bit) More...

	__attribute__ ((section(".revsh_text"))) static __inline __asm int16_t __REVSH(int16_t value)
	Reverse byte order (16 bit) More...

	__attribute__ ((always_inline)) static __inline uint32_t __RBIT(uint32_t value)
	Reverse bit order of value. More...

	if (op2==0U)

	return (op1 >> op2)\|(op1<<(32U - op2))

Variables
uint32_t	sat

uint32_t	op2

uint32_t	sat

uint32_t	op2

uint32_t	sat

Detailed Description

Access to dedicated instructions.

Macro Definition Documentation

◆ __BKPT [1/3]

#define __BKPT ( value ) __breakpoint(value)

Breakpoint.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Parameters

[in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.

Definition at line 503 of file cmsis_armcc.h.

◆ __BKPT [2/3]

#define __BKPT ( value ) __ASM volatile ("bkpt "#value)

Breakpoint.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Parameters

[in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.

Definition at line 894 of file cmsis_armclang.h.

◆ __BKPT [3/3]

#define __BKPT ( value ) __ASM volatile ("bkpt "#value)

Breakpoint.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Parameters

[in] value is ignored by the processor. If required, a debugger can use it to store additional information about the breakpoint.

Definition at line 972 of file cmsis_gcc.h.

◆ __CLZ [1/3]

#define __CLZ __clz

Count leading zeros.

Counts the number of leading zeros of a data value.

Parameters

[in] value Value to count the leading zeros

Returns: number of leading zeros in value

Definition at line 540 of file cmsis_armcc.h.

◆ __CLZ [2/3]

#define __CLZ (uint8_t)__builtin_clz

Count leading zeros.

Counts the number of leading zeros of a data value.

Parameters

[in] value Value to count the leading zeros

Returns: number of leading zeros in value

Definition at line 911 of file cmsis_armclang.h.

◆ __CLZ [3/3]

#define __CLZ (uint8_t)__builtin_clz

Count leading zeros.

Counts the number of leading zeros of a data value.

Parameters

[in] value Value to count the leading zeros

Returns: number of leading zeros in value

Definition at line 1011 of file cmsis_gcc.h.

◆ __CMSIS_GCC_OUT_REG [1/2]

#define __CMSIS_GCC_OUT_REG ( r ) "=r" (r)

Definition at line 786 of file cmsis_armclang.h.

◆ __CMSIS_GCC_OUT_REG [2/2]

#define __CMSIS_GCC_OUT_REG ( r ) "=r" (r)

Definition at line 827 of file cmsis_gcc.h.

◆ __CMSIS_GCC_RW_REG

#define __CMSIS_GCC_RW_REG ( r ) "+r" (r)

Definition at line 828 of file cmsis_gcc.h.

◆ __CMSIS_GCC_USE_REG [1/2]

#define __CMSIS_GCC_USE_REG ( r ) "r" (r)

Definition at line 787 of file cmsis_armclang.h.

◆ __CMSIS_GCC_USE_REG [2/2]

#define __CMSIS_GCC_USE_REG ( r ) "r" (r)

Definition at line 829 of file cmsis_gcc.h.

◆ __DMB [1/2]

#define __DMB ( )

Value:

                   do {\
                   __schedule_barrier();\
                   __dmb(0xF);\
                   __schedule_barrier();\
                } while (0U)

Data Memory Barrier.

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Definition at line 440 of file cmsis_armcc.h.

◆ __DMB [2/2]

#define __DMB ( ) __builtin_arm_dmb(0xF);

Data Memory Barrier.

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Definition at line 839 of file cmsis_armclang.h.

◆ __DSB [1/2]

#define __DSB ( )

Value:

                   do {\
                   __schedule_barrier();\
                   __dsb(0xF);\
                   __schedule_barrier();\
                } while (0U)

Data Synchronization Barrier.

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

Definition at line 429 of file cmsis_armcc.h.

◆ __DSB [2/2]

#define __DSB ( ) __builtin_arm_dsb(0xF);

Data Synchronization Barrier.

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

Definition at line 831 of file cmsis_armclang.h.

◆ __ISB [1/2]

#define __ISB ( )

Value:

                   do {\
                   __schedule_barrier();\
                   __isb(0xF);\
                   __schedule_barrier();\
                } while (0U)

Instruction Synchronization Barrier.

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

Definition at line 418 of file cmsis_armcc.h.

◆ __ISB [2/2]

#define __ISB ( ) __builtin_arm_isb(0xF);

Instruction Synchronization Barrier.

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

Definition at line 824 of file cmsis_armclang.h.

◆ __NOP [1/3]

#define __NOP __nop

No Operation.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 387 of file cmsis_armcc.h.

◆ __NOP [2/3]

#define __NOP __builtin_arm_nop

No Operation.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 794 of file cmsis_armclang.h.

◆ __NOP [3/3]

#define __NOP ( ) __ASM volatile ("nop")

No Operation.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 836 of file cmsis_gcc.h.

◆ __RBIT

#define __RBIT __builtin_arm_rbit

Reverse bit order of value.

Reverses the bit order of the given value.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 903 of file cmsis_armclang.h.

◆ __REV [1/2]

#define __REV __rev

Reverse byte order (32 bit)

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 453 of file cmsis_armcc.h.

◆ __REV [2/2]

#define __REV ( value ) __builtin_bswap32(value)

Reverse byte order (32 bit)

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 848 of file cmsis_armclang.h.

◆ __REV16

#define __REV16 ( value ) __ROR(__REV(value), 16)

Reverse byte order (16 bit)

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 857 of file cmsis_armclang.h.

◆ __REVSH

#define __REVSH ( value ) (int16_t)__builtin_bswap16(value)

Reverse byte order (16 bit)

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 866 of file cmsis_armclang.h.

◆ __ROR

#define __ROR __ror

Rotate Right in unsigned value (32 bit)

Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

Parameters

[in]	op1	Value to rotate
[in]	op2	Number of Bits to rotate

Returns: Rotated value

Definition at line 493 of file cmsis_armcc.h.

◆ __SEV [1/3]

#define __SEV __sev

Send Event.

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

Definition at line 409 of file cmsis_armcc.h.

◆ __SEV [2/3]

#define __SEV __builtin_arm_sev

Send Event.

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

Definition at line 815 of file cmsis_armclang.h.

◆ __SEV [3/3]

#define __SEV ( ) __ASM volatile ("sev")

Send Event.

Send Event is a hint instruction. It causes an event to be signaled to the CPU.

Definition at line 857 of file cmsis_gcc.h.

◆ __WFE [1/3]

#define __WFE __wfe

Wait For Event.

Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs.

Definition at line 402 of file cmsis_armcc.h.

◆ __WFE [2/3]

#define __WFE __builtin_arm_wfe

Wait For Event.

Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs.

Definition at line 808 of file cmsis_armclang.h.

◆ __WFE [3/3]

#define __WFE ( ) __ASM volatile ("wfe")

Wait For Event.

Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs.

Definition at line 850 of file cmsis_gcc.h.

◆ __WFI [1/3]

#define __WFI __wfi

Wait For Interrupt.

Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

Definition at line 394 of file cmsis_armcc.h.

◆ __WFI [2/3]

#define __WFI __builtin_arm_wfi

Wait For Interrupt.

Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

Definition at line 800 of file cmsis_armclang.h.

◆ __WFI [3/3]

#define __WFI ( ) __ASM volatile ("wfi")

Wait For Interrupt.

Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.

Definition at line 842 of file cmsis_gcc.h.

Function Documentation

◆ attribute() [1/3]

__attribute__ ( (always_inline) )

Reverse bit order of value.

Set FPSCR.

Get FPSCR.

Get Control Register.

Disable IRQ Interrupts.

Enable IRQ Interrupts.

Set Priority Mask.

Get Priority Mask.

Set Main Stack Pointer.

Get Main Stack Pointer.

Set Process Stack Pointer.

Get Process Stack Pointer.

Get xPSR Register.

Get APSR Register.

Get IPSR Register.

Set Control Register.

Reverse byte order (16 bit)

Reverse byte order (32 bit)

Data Memory Barrier.

Data Synchronization Barrier.

Instruction Synchronization Barrier.

Rotate Right in unsigned value (32 bit)

Unsigned Saturate.

Signed Saturate.

Reverses the bit order of the given value.

Parameters

[in] value Value to reverse

Returns: Reversed value

Saturates a signed value.

Parameters

[in]	value	Value to be saturated
[in]	sat	Bit position to saturate to (1..32)

Returns: Saturated value

Saturates an unsigned value.

Parameters

[in]	value	Value to be saturated
[in]	sat	Bit position to saturate to (0..31)

Returns: Saturated value

Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.

Parameters

[in]	op1	Value to rotate
[in]	op2	Number of Bits to rotate

Returns: Rotated value

Instruction Synchronization Barrier flushes the pipeline in the processor, so that all instructions following the ISB are fetched from cache or memory, after the instruction has been completed.

Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete.

Ensures the apparent order of the explicit memory operations before and after the instruction, without ensuring their completion.

Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.

Parameters

[in] value Value to reverse

Returns: Reversed value

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

Parameters

[in] value Value to reverse

Returns: Reversed value

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

Parameters

[in] value Value to reverse

Returns: Reversed value

Writes the given value to the Control Register.

Parameters

[in] control Control Register value to set

Returns the content of the IPSR Register.

Returns: IPSR Register value

Returns the content of the APSR Register.

Returns: APSR Register value

Returns the content of the xPSR Register.

Returns: xPSR Register value

Returns the current value of the Process Stack Pointer (PSP).

Returns: PSP Register value

Assigns the given value to the Process Stack Pointer (PSP).

Parameters

[in] topOfProcStack Process Stack Pointer value to set

Returns the current value of the Main Stack Pointer (MSP).

Returns: MSP Register value

Assigns the given value to the Main Stack Pointer (MSP).

Parameters

[in] topOfMainStack Main Stack Pointer value to set

Returns the current state of the priority mask bit from the Priority Mask Register.

Returns: Priority Mask value

Assigns the given value to the Priority Mask Register.

Parameters

[in] priMask Priority Mask

Enables IRQ interrupts by clearing the I-bit in the CPSR. Can only be executed in Privileged modes.

Disables IRQ interrupts by setting the I-bit in the CPSR. Can only be executed in Privileged modes.

Returns the content of the Control Register.

Returns: Control Register value

Returns the current value of the Floating Point Status/Control register.

Returns: Floating Point Status/Control register value

Assigns the given value to the Floating Point Status/Control register.

Parameters

[in] fpscr Floating Point Status/Control value to set

Definition at line 516 of file cmsis_armcc.h.

 {
   uint32_t result;
   uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
  
   result = value;                      /* r will be reversed bits of v; first get LSB of v */
   for (value >>= 1U; value != 0U; value >>= 1U)
   {
     result <<= 1U;
     result |= value & 1U;
     s--;
   }
   result <<= s;                        /* shift when v's highest bits are zero */
   return result;
 }

◆ attribute() [2/3]

__attribute__ ( (section(".rev16_text")) )

Reverse byte order (16 bit)

Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 463 of file cmsis_armcc.h.

 {
   rev16 r0, r0
   bx lr
 }

◆ attribute() [3/3]

__attribute__ ( (section(".revsh_text")) )

Reverse byte order (16 bit)

Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.

Parameters

[in] value Value to reverse

Returns: Reversed value

Definition at line 478 of file cmsis_armcc.h.

 {
   revsh r0, r0
   bx lr
 }

◆ if()

if ( op2 = = 0U )

Definition at line 879 of file cmsis_armclang.h.

   {
     return op1;
   }

◆ return()

return ( op1 >> op2 )

Variable Documentation

◆ op2 [1/2]

uint32_t op2

Initial value:

{

op2 %= 32U

Definition at line 877 of file cmsis_armclang.h.

◆ op2 [2/2]

uint32_t op2

Initial value:

{

op2 %= 32U

Definition at line 955 of file cmsis_gcc.h.

◆ sat [1/3]

uint32_t sat

Initial value:

{
  if ((sat >= 1U) && (sat <= 32U))
  {
    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
    const int32_t min = -1 - max ;
    if (val > max)
    {
      return max;
    }
    else if (val < min)
    {
      return min;
    }
  }
  return val

Definition at line 737 of file cmsis_armcc.h.

◆ sat [2/3]

uint32_t sat

Initial value:

{
  if ((sat >= 1U) && (sat <= 32U))
  {
    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
    const int32_t min = -1 - max ;
    if (val > max)
    {
      return max;
    }
    else if (val < min)
    {
      return min;
    }
  }
  return val

Definition at line 1122 of file cmsis_armclang.h.

◆ sat [3/3]

uint32_t sat

Initial value:

{
  if ((sat >= 1U) && (sat <= 32U))
  {
    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
    const int32_t min = -1 - max ;
    if (val > max)
    {
      return max;
    }
    else if (val < min)
    {
      return min;
    }
  }
  return val

Definition at line 1300 of file cmsis_gcc.h.

Modules

Macros

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ __BKPT [1/3]

◆ __BKPT [2/3]

◆ __BKPT [3/3]

◆ __CLZ [1/3]

◆ __CLZ [2/3]

◆ __CLZ [3/3]

◆ __CMSIS_GCC_OUT_REG [1/2]

◆ __CMSIS_GCC_OUT_REG [2/2]

◆ __CMSIS_GCC_RW_REG

◆ __CMSIS_GCC_USE_REG [1/2]

◆ __CMSIS_GCC_USE_REG [2/2]

◆ __DMB [1/2]

◆ __DMB [2/2]

◆ __DSB [1/2]

◆ __DSB [2/2]

◆ __ISB [1/2]

◆ __ISB [2/2]

◆ __NOP [1/3]

◆ __NOP [2/3]

◆ __NOP [3/3]

◆ __RBIT

◆ __REV [1/2]

◆ __REV [2/2]

◆ __REV16

◆ __REVSH

◆ __ROR

◆ __SEV [1/3]

◆ __SEV [2/3]

◆ __SEV [3/3]

◆ __WFE [1/3]

◆ __WFE [2/3]

◆ __WFE [3/3]

◆ __WFI [1/3]

◆ __WFI [2/3]

◆ __WFI [3/3]

Function Documentation

◆ __attribute__() [1/3]

◆ __attribute__() [2/3]

◆ __attribute__() [3/3]

◆ if()

◆ return()

Variable Documentation

◆ op2 [1/2]

◆ op2 [2/2]

◆ sat [1/3]

◆ sat [2/3]

◆ sat [3/3]

◆ attribute() [1/3]

◆ attribute() [2/3]

◆ attribute() [3/3]