Type definitions for the Trace Port Interface (TPI) More...

Modules
	Core Debug Registers (CoreDebug)
	Type definitions for the Core Debug Registers.

	Floating Point Unit (FPU)
	Type definitions for the Floating Point Unit (FPU)

Data Structures
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_SWOSCALER_Pos 0U

#define	TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /<< TPI_ACPR_SWOSCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_PSCR_PSCount_Pos 0U

#define	TPI_PSCR_PSCount_Msk (0x1FUL /<< TPI_PSCR_PSCount_Pos/)

#define	TPI_LSR_nTT_Pos 1U

#define	TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos)

#define	TPI_LSR_SLK_Pos 1U

#define	TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos)

#define	TPI_LSR_SLI_Pos 0U

#define	TPI_LSR_SLI_Msk (0x1UL /<< TPI_LSR_SLI_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_FIFO0_ITM_ATVALID_Pos 29U

#define	TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)

#define	TPI_FIFO0_ITM_bytecount_Pos 27U

#define	TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)

#define	TPI_FIFO0_ETM_ATVALID_Pos 26U

#define	TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)

#define	TPI_FIFO0_ETM_bytecount_Pos 24U

#define	TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)

#define	TPI_FIFO0_ETM2_Pos 16U

#define	TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos)

#define	TPI_FIFO0_ETM1_Pos 8U

#define	TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos)

#define	TPI_FIFO0_ETM0_Pos 0U

#define	TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/)

#define	TPI_ITATBCTR2_ATREADY2_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2_Pos/)

#define	TPI_ITATBCTR2_ATREADY1_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1_Pos/)

#define	TPI_FIFO1_ITM_ATVALID_Pos 29U

#define	TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)

#define	TPI_FIFO1_ITM_bytecount_Pos 27U

#define	TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)

#define	TPI_FIFO1_ETM_ATVALID_Pos 26U

#define	TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)

#define	TPI_FIFO1_ETM_bytecount_Pos 24U

#define	TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)

#define	TPI_FIFO1_ITM2_Pos 16U

#define	TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos)

#define	TPI_FIFO1_ITM1_Pos 8U

#define	TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos)

#define	TPI_FIFO1_ITM0_Pos 0U

#define	TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/)

#define	TPI_ITATBCTR0_ATREADY2_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2_Pos/)

#define	TPI_ITATBCTR0_ATREADY1_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_MinBufSz_Pos 6U

#define	TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

#define	TPI_DEVID_AsynClkIn_Pos 5U

#define	TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Macro Definition Documentation

◆ TPI_ACPR_PRESCALER_Msk [1/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 755 of file core_cm23.h.

◆ TPI_ACPR_PRESCALER_Msk [2/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1008 of file core_sc300.h.

◆ TPI_ACPR_PRESCALER_Msk [3/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1026 of file core_cm3.h.

◆ TPI_ACPR_PRESCALER_Msk [4/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1091 of file core_cm4.h.

◆ TPI_ACPR_PRESCALER_Msk [5/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1296 of file core_cm7.h.

◆ TPI_ACPR_PRESCALER_Msk [6/6]

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

Definition at line 1417 of file core_cm33.h.

◆ TPI_ACPR_PRESCALER_Pos [1/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 754 of file core_cm23.h.

◆ TPI_ACPR_PRESCALER_Pos [2/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1007 of file core_sc300.h.

◆ TPI_ACPR_PRESCALER_Pos [3/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1025 of file core_cm3.h.

◆ TPI_ACPR_PRESCALER_Pos [4/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1090 of file core_cm4.h.

◆ TPI_ACPR_PRESCALER_Pos [5/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1295 of file core_cm7.h.

◆ TPI_ACPR_PRESCALER_Pos [6/6]

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

Definition at line 1416 of file core_cm33.h.

◆ TPI_ACPR_SWOSCALER_Msk [1/2]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 747 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Msk [2/2]

#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/)

TPI ACPR: SWOSCALER Mask

Definition at line 1409 of file core_armv8mml.h.

◆ TPI_ACPR_SWOSCALER_Pos [1/2]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 746 of file core_armv8mbl.h.

◆ TPI_ACPR_SWOSCALER_Pos [2/2]

#define TPI_ACPR_SWOSCALER_Pos 0U

TPI ACPR: SWOSCALER Position

Definition at line 1408 of file core_armv8mml.h.

◆ TPI_DEVID_AsynClkIn_Msk [1/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1114 of file core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Msk [2/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1132 of file core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Msk [3/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1197 of file core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Msk [4/4]

#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos)

TPI DEVID: AsynClkIn Mask

Definition at line 1402 of file core_cm7.h.

◆ TPI_DEVID_AsynClkIn_Pos [1/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1113 of file core_sc300.h.

◆ TPI_DEVID_AsynClkIn_Pos [2/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1131 of file core_cm3.h.

◆ TPI_DEVID_AsynClkIn_Pos [3/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1196 of file core_cm4.h.

◆ TPI_DEVID_AsynClkIn_Pos [4/4]

#define TPI_DEVID_AsynClkIn_Pos 5U

TPI DEVID: AsynClkIn Position

Definition at line 1401 of file core_cm7.h.

◆ TPI_DEVID_FIFOSZ_Msk [1/4]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 801 of file core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Msk [2/4]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 873 of file core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Msk [3/4]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFO depth Mask

Definition at line 1463 of file core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Msk [4/4]

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

Definition at line 1535 of file core_cm33.h.

◆ TPI_DEVID_FIFOSZ_Pos [1/4]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 800 of file core_armv8mbl.h.

◆ TPI_DEVID_FIFOSZ_Pos [2/4]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 872 of file core_cm23.h.

◆ TPI_DEVID_FIFOSZ_Pos [3/4]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFO depth Position

Definition at line 1462 of file core_armv8mml.h.

◆ TPI_DEVID_FIFOSZ_Pos [4/4]

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

Definition at line 1534 of file core_cm33.h.

◆ TPI_DEVID_MANCVALID_Msk [1/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 795 of file core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Msk [2/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 867 of file core_cm23.h.

◆ TPI_DEVID_MANCVALID_Msk [3/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1105 of file core_sc300.h.

◆ TPI_DEVID_MANCVALID_Msk [4/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1123 of file core_cm3.h.

◆ TPI_DEVID_MANCVALID_Msk [5/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1188 of file core_cm4.h.

◆ TPI_DEVID_MANCVALID_Msk [6/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1393 of file core_cm7.h.

◆ TPI_DEVID_MANCVALID_Msk [7/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1457 of file core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Msk [8/8]

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

Definition at line 1529 of file core_cm33.h.

◆ TPI_DEVID_MANCVALID_Pos [1/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 794 of file core_armv8mbl.h.

◆ TPI_DEVID_MANCVALID_Pos [2/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 866 of file core_cm23.h.

◆ TPI_DEVID_MANCVALID_Pos [3/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1104 of file core_sc300.h.

◆ TPI_DEVID_MANCVALID_Pos [4/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1122 of file core_cm3.h.

◆ TPI_DEVID_MANCVALID_Pos [5/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1187 of file core_cm4.h.

◆ TPI_DEVID_MANCVALID_Pos [6/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1392 of file core_cm7.h.

◆ TPI_DEVID_MANCVALID_Pos [7/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1456 of file core_armv8mml.h.

◆ TPI_DEVID_MANCVALID_Pos [8/8]

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

Definition at line 1528 of file core_cm33.h.

◆ TPI_DEVID_MinBufSz_Msk [1/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1111 of file core_sc300.h.

◆ TPI_DEVID_MinBufSz_Msk [2/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1129 of file core_cm3.h.

◆ TPI_DEVID_MinBufSz_Msk [3/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1194 of file core_cm4.h.

◆ TPI_DEVID_MinBufSz_Msk [4/4]

#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos)

TPI DEVID: MinBufSz Mask

Definition at line 1399 of file core_cm7.h.

◆ TPI_DEVID_MinBufSz_Pos [1/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1110 of file core_sc300.h.

◆ TPI_DEVID_MinBufSz_Pos [2/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1128 of file core_cm3.h.

◆ TPI_DEVID_MinBufSz_Pos [3/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1193 of file core_cm4.h.

◆ TPI_DEVID_MinBufSz_Pos [4/4]

#define TPI_DEVID_MinBufSz_Pos 6U

TPI DEVID: MinBufSz Position

Definition at line 1398 of file core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [1/6]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 876 of file core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Msk [2/6]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1117 of file core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Msk [3/6]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1135 of file core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Msk [4/6]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1200 of file core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Msk [5/6]

#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1405 of file core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Msk [6/6]

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

Definition at line 1538 of file core_cm33.h.

◆ TPI_DEVID_NrTraceInput_Pos [1/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 875 of file core_cm23.h.

◆ TPI_DEVID_NrTraceInput_Pos [2/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1116 of file core_sc300.h.

◆ TPI_DEVID_NrTraceInput_Pos [3/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1134 of file core_cm3.h.

◆ TPI_DEVID_NrTraceInput_Pos [4/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1199 of file core_cm4.h.

◆ TPI_DEVID_NrTraceInput_Pos [5/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1404 of file core_cm7.h.

◆ TPI_DEVID_NrTraceInput_Pos [6/6]

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

Definition at line 1537 of file core_cm33.h.

◆ TPI_DEVID_NRZVALID_Msk [1/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 792 of file core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Msk [2/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 864 of file core_cm23.h.

◆ TPI_DEVID_NRZVALID_Msk [3/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1102 of file core_sc300.h.

◆ TPI_DEVID_NRZVALID_Msk [4/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1120 of file core_cm3.h.

◆ TPI_DEVID_NRZVALID_Msk [5/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1185 of file core_cm4.h.

◆ TPI_DEVID_NRZVALID_Msk [6/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1390 of file core_cm7.h.

◆ TPI_DEVID_NRZVALID_Msk [7/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1454 of file core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Msk [8/8]

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

Definition at line 1526 of file core_cm33.h.

◆ TPI_DEVID_NRZVALID_Pos [1/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 791 of file core_armv8mbl.h.

◆ TPI_DEVID_NRZVALID_Pos [2/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 863 of file core_cm23.h.

◆ TPI_DEVID_NRZVALID_Pos [3/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1101 of file core_sc300.h.

◆ TPI_DEVID_NRZVALID_Pos [4/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1119 of file core_cm3.h.

◆ TPI_DEVID_NRZVALID_Pos [5/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1184 of file core_cm4.h.

◆ TPI_DEVID_NRZVALID_Pos [6/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1389 of file core_cm7.h.

◆ TPI_DEVID_NRZVALID_Pos [7/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1453 of file core_armv8mml.h.

◆ TPI_DEVID_NRZVALID_Pos [8/8]

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

Definition at line 1525 of file core_cm33.h.

◆ TPI_DEVID_PTINVALID_Msk [1/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 798 of file core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Msk [2/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 870 of file core_cm23.h.

◆ TPI_DEVID_PTINVALID_Msk [3/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1108 of file core_sc300.h.

◆ TPI_DEVID_PTINVALID_Msk [4/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1126 of file core_cm3.h.

◆ TPI_DEVID_PTINVALID_Msk [5/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1191 of file core_cm4.h.

◆ TPI_DEVID_PTINVALID_Msk [6/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1396 of file core_cm7.h.

◆ TPI_DEVID_PTINVALID_Msk [7/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1460 of file core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Msk [8/8]

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

Definition at line 1532 of file core_cm33.h.

◆ TPI_DEVID_PTINVALID_Pos [1/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 797 of file core_armv8mbl.h.

◆ TPI_DEVID_PTINVALID_Pos [2/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 869 of file core_cm23.h.

◆ TPI_DEVID_PTINVALID_Pos [3/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1107 of file core_sc300.h.

◆ TPI_DEVID_PTINVALID_Pos [4/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1125 of file core_cm3.h.

◆ TPI_DEVID_PTINVALID_Pos [5/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1190 of file core_cm4.h.

◆ TPI_DEVID_PTINVALID_Pos [6/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1395 of file core_cm7.h.

◆ TPI_DEVID_PTINVALID_Pos [7/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1459 of file core_armv8mml.h.

◆ TPI_DEVID_PTINVALID_Pos [8/8]

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

Definition at line 1531 of file core_cm33.h.

◆ TPI_DEVTYPE_MajorType_Msk [1/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 808 of file core_armv8mbl.h.

◆ TPI_DEVTYPE_MajorType_Msk [2/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 883 of file core_cm23.h.

◆ TPI_DEVTYPE_MajorType_Msk [3/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1124 of file core_sc300.h.

◆ TPI_DEVTYPE_MajorType_Msk [4/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1142 of file core_cm3.h.

◆ TPI_DEVTYPE_MajorType_Msk [5/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1207 of file core_cm4.h.

◆ TPI_DEVTYPE_MajorType_Msk [6/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1412 of file core_cm7.h.

◆ TPI_DEVTYPE_MajorType_Msk [7/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1470 of file core_armv8mml.h.

◆ TPI_DEVTYPE_MajorType_Msk [8/8]

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

Definition at line 1545 of file core_cm33.h.