DIY Logging Volt/Ampmeter
stm32f103xb.h
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1 /**
2  ******************************************************************************
3  * @file stm32f103xb.h
4  * @author MCD Application Team
5  * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6  * This file contains all the peripheral register's definitions, bits
7  * definitions and memory mapping for STM32F1xx devices.
8  *
9  * This file contains:
10  * - Data structures and the address mapping for all peripherals
11  * - Peripheral's registers declarations and bits definition
12  * - Macros to access peripheral’s registers hardware
13  *
14  ******************************************************************************
15  * @attention
16  *
17  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
18  * All rights reserved.</center></h2>
19  *
20  * This software component is licensed by ST under BSD 3-Clause license,
21  * the "License"; You may not use this file except in compliance with the
22  * License. You may obtain a copy of the License at:
23  * opensource.org/licenses/BSD-3-Clause
24  *
25  ******************************************************************************
26  */
27 
28 
29 /** @addtogroup CMSIS
30  * @{
31  */
32 
33 /** @addtogroup stm32f103xb
34  * @{
35  */
36 
37 #ifndef __STM32F103xB_H
38 #define __STM32F103xB_H
39 
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 /** @addtogroup Configuration_section_for_CMSIS
45  * @{
46  */
47 /**
48  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
49  */
50 #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */
51  #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */
52 #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */
53 #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
54 
55 /**
56  * @}
57  */
58 
59 /** @addtogroup Peripheral_interrupt_number_definition
60  * @{
61  */
62 
63 /**
64  * @brief STM32F10x Interrupt Number Definition, according to the selected device
65  * in @ref Library_configuration_section
66  */
67 
68  /*!< Interrupt Number Definition */
69 typedef enum
70 {
71 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
72  NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
73  HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */
74  MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
75  BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
76  UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
77  SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
78  DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
79  PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
80  SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
81 
82 /****** STM32 specific Interrupt Numbers *********************************************************/
83  WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
84  PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
85  TAMPER_IRQn = 2, /*!< Tamper Interrupt */
86  RTC_IRQn = 3, /*!< RTC global Interrupt */
87  FLASH_IRQn = 4, /*!< FLASH global Interrupt */
88  RCC_IRQn = 5, /*!< RCC global Interrupt */
89  EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
90  EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
91  EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
92  EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
93  EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
94  DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
95  DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
96  DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
97  DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
98  DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
99  DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
100  DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
101  ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */
102  USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
103  USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
104  CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
105  CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
106  EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
107  TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
108  TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
109  TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
110  TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
111  TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
112  TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
113  TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
114  I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
115  I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
116  I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
117  I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
118  SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
119  SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
120  USART1_IRQn = 37, /*!< USART1 global Interrupt */
121  USART2_IRQn = 38, /*!< USART2 global Interrupt */
122  USART3_IRQn = 39, /*!< USART3 global Interrupt */
123  EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
124  RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
125  USBWakeUp_IRQn = 42, /*!< USB Device WakeUp from suspend through EXTI Line Interrupt */
126 } IRQn_Type;
127 
128 /**
129  * @}
130  */
131 
132 #include "core_cm3.h"
133 #include "system_stm32f1xx.h"
134 #include <stdint.h>
135 
136 /** @addtogroup Peripheral_registers_structures
137  * @{
138  */
139 
140 /**
141  * @brief Analog to Digital Converter
142  */
143 
144 typedef struct
145 {
146  __IO uint32_t SR;
147  __IO uint32_t CR1;
148  __IO uint32_t CR2;
149  __IO uint32_t SMPR1;
150  __IO uint32_t SMPR2;
151  __IO uint32_t JOFR1;
152  __IO uint32_t JOFR2;
153  __IO uint32_t JOFR3;
154  __IO uint32_t JOFR4;
155  __IO uint32_t HTR;
156  __IO uint32_t LTR;
157  __IO uint32_t SQR1;
158  __IO uint32_t SQR2;
159  __IO uint32_t SQR3;
160  __IO uint32_t JSQR;
161  __IO uint32_t JDR1;
162  __IO uint32_t JDR2;
163  __IO uint32_t JDR3;
164  __IO uint32_t JDR4;
165  __IO uint32_t DR;
166 } ADC_TypeDef;
167 
168 typedef struct
169 {
170  __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */
171  __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */
172  __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */
173  uint32_t RESERVED[16];
174  __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */
175 } ADC_Common_TypeDef;
176 
177 /**
178  * @brief Backup Registers
179  */
180 
181 typedef struct
182 {
183  uint32_t RESERVED0;
184  __IO uint32_t DR1;
185  __IO uint32_t DR2;
186  __IO uint32_t DR3;
187  __IO uint32_t DR4;
188  __IO uint32_t DR5;
189  __IO uint32_t DR6;
190  __IO uint32_t DR7;
191  __IO uint32_t DR8;
192  __IO uint32_t DR9;
193  __IO uint32_t DR10;
194  __IO uint32_t RTCCR;
195  __IO uint32_t CR;
196  __IO uint32_t CSR;
197 } BKP_TypeDef;
198 
199 /**
200  * @brief Controller Area Network TxMailBox
201  */
202 
203 typedef struct
204 {
205  __IO uint32_t TIR;
206  __IO uint32_t TDTR;
207  __IO uint32_t TDLR;
208  __IO uint32_t TDHR;
209 } CAN_TxMailBox_TypeDef;
210 
211 /**
212  * @brief Controller Area Network FIFOMailBox
213  */
214 
215 typedef struct
216 {
217  __IO uint32_t RIR;
218  __IO uint32_t RDTR;
219  __IO uint32_t RDLR;
220  __IO uint32_t RDHR;
221 } CAN_FIFOMailBox_TypeDef;
222 
223 /**
224  * @brief Controller Area Network FilterRegister
225  */
226 
227 typedef struct
228 {
229  __IO uint32_t FR1;
230  __IO uint32_t FR2;
231 } CAN_FilterRegister_TypeDef;
232 
233 /**
234  * @brief Controller Area Network
235  */
236 
237 typedef struct
238 {
239  __IO uint32_t MCR;
240  __IO uint32_t MSR;
241  __IO uint32_t TSR;
242  __IO uint32_t RF0R;
243  __IO uint32_t RF1R;
244  __IO uint32_t IER;
245  __IO uint32_t ESR;
246  __IO uint32_t BTR;
247  uint32_t RESERVED0[88];
248  CAN_TxMailBox_TypeDef sTxMailBox[3];
249  CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
250  uint32_t RESERVED1[12];
251  __IO uint32_t FMR;
252  __IO uint32_t FM1R;
253  uint32_t RESERVED2;
254  __IO uint32_t FS1R;
255  uint32_t RESERVED3;
256  __IO uint32_t FFA1R;
257  uint32_t RESERVED4;
258  __IO uint32_t FA1R;
259  uint32_t RESERVED5[8];
260  CAN_FilterRegister_TypeDef sFilterRegister[14];
261 } CAN_TypeDef;
262 
263 /**
264  * @brief CRC calculation unit
265  */
266 
267 typedef struct
268 {
269  __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
270  __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
271  uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */
272  uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */
273  __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
274 } CRC_TypeDef;
275 
276 
277 /**
278  * @brief Debug MCU
279  */
280 
281 typedef struct
282 {
283  __IO uint32_t IDCODE;
284  __IO uint32_t CR;
285 }DBGMCU_TypeDef;
286 
287 /**
288  * @brief DMA Controller
289  */
290 
291 typedef struct
292 {
293  __IO uint32_t CCR;
294  __IO uint32_t CNDTR;
295  __IO uint32_t CPAR;
296  __IO uint32_t CMAR;
297 } DMA_Channel_TypeDef;
298 
299 typedef struct
300 {
301  __IO uint32_t ISR;
302  __IO uint32_t IFCR;
303 } DMA_TypeDef;
304 
305 
306 
307 /**
308  * @brief External Interrupt/Event Controller
309  */
310 
311 typedef struct
312 {
313  __IO uint32_t IMR;
314  __IO uint32_t EMR;
315  __IO uint32_t RTSR;
316  __IO uint32_t FTSR;
317  __IO uint32_t SWIER;
318  __IO uint32_t PR;
319 } EXTI_TypeDef;
320 
321 /**
322  * @brief FLASH Registers
323  */
324 
325 typedef struct
326 {
327  __IO uint32_t ACR;
328  __IO uint32_t KEYR;
329  __IO uint32_t OPTKEYR;
330  __IO uint32_t SR;
331  __IO uint32_t CR;
332  __IO uint32_t AR;
333  __IO uint32_t RESERVED;
334  __IO uint32_t OBR;
335  __IO uint32_t WRPR;
336 } FLASH_TypeDef;
337 
338 /**
339  * @brief Option Bytes Registers
340  */
341 
342 typedef struct
343 {
344  __IO uint16_t RDP;
345  __IO uint16_t USER;
346  __IO uint16_t Data0;
347  __IO uint16_t Data1;
348  __IO uint16_t WRP0;
349  __IO uint16_t WRP1;
350  __IO uint16_t WRP2;
351  __IO uint16_t WRP3;
352 } OB_TypeDef;
353 
354 /**
355  * @brief General Purpose I/O
356  */
357 
358 typedef struct
359 {
360  __IO uint32_t CRL;
361  __IO uint32_t CRH;
362  __IO uint32_t IDR;
363  __IO uint32_t ODR;
364  __IO uint32_t BSRR;
365  __IO uint32_t BRR;
366  __IO uint32_t LCKR;
367 } GPIO_TypeDef;
368 
369 /**
370  * @brief Alternate Function I/O
371  */
372 
373 typedef struct
374 {
375  __IO uint32_t EVCR;
376  __IO uint32_t MAPR;
377  __IO uint32_t EXTICR[4];
378  uint32_t RESERVED0;
379  __IO uint32_t MAPR2;
380 } AFIO_TypeDef;
381 /**
382  * @brief Inter Integrated Circuit Interface
383  */
384 
385 typedef struct
386 {
387  __IO uint32_t CR1;
388  __IO uint32_t CR2;
389  __IO uint32_t OAR1;
390  __IO uint32_t OAR2;
391  __IO uint32_t DR;
392  __IO uint32_t SR1;
393  __IO uint32_t SR2;
394  __IO uint32_t CCR;
395  __IO uint32_t TRISE;
396 } I2C_TypeDef;
397 
398 /**
399  * @brief Independent WATCHDOG
400  */
401 
402 typedef struct
403 {
404  __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
405  __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
406  __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
407  __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
408 } IWDG_TypeDef;
409 
410 /**
411  * @brief Power Control
412  */
413 
414 typedef struct
415 {
416  __IO uint32_t CR;
417  __IO uint32_t CSR;
418 } PWR_TypeDef;
419 
420 /**
421  * @brief Reset and Clock Control
422  */
423 
424 typedef struct
425 {
426  __IO uint32_t CR;
427  __IO uint32_t CFGR;
428  __IO uint32_t CIR;
429  __IO uint32_t APB2RSTR;
430  __IO uint32_t APB1RSTR;
431  __IO uint32_t AHBENR;
432  __IO uint32_t APB2ENR;
433  __IO uint32_t APB1ENR;
434  __IO uint32_t BDCR;
435  __IO uint32_t CSR;
436 
437 
438 } RCC_TypeDef;
439 
440 /**
441  * @brief Real-Time Clock
442  */
443 
444 typedef struct
445 {
446  __IO uint32_t CRH;
447  __IO uint32_t CRL;
448  __IO uint32_t PRLH;
449  __IO uint32_t PRLL;
450  __IO uint32_t DIVH;
451  __IO uint32_t DIVL;
452  __IO uint32_t CNTH;
453  __IO uint32_t CNTL;
454  __IO uint32_t ALRH;
455  __IO uint32_t ALRL;
456 } RTC_TypeDef;
457 
458 /**
459  * @brief Serial Peripheral Interface
460  */
461 
462 typedef struct
463 {
464  __IO uint32_t CR1;
465  __IO uint32_t CR2;
466  __IO uint32_t SR;
467  __IO uint32_t DR;
468  __IO uint32_t CRCPR;
469  __IO uint32_t RXCRCR;
470  __IO uint32_t TXCRCR;
471  __IO uint32_t I2SCFGR;
472 } SPI_TypeDef;
473 
474 /**
475  * @brief TIM Timers
476  */
477 typedef struct
478 {
479  __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
480  __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
481  __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
482  __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
483  __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
484  __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
485  __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
486  __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
487  __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
488  __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
489  __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
490  __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
491  __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
492  __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
493  __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
494  __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
495  __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
496  __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
497  __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
498  __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
499  __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
500 }TIM_TypeDef;
501 
502 
503 /**
504  * @brief Universal Synchronous Asynchronous Receiver Transmitter
505  */
506 
507 typedef struct
508 {
509  __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */
510  __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */
511  __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
512  __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
513  __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
514  __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
515  __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
516 } USART_TypeDef;
517 
518 /**
519  * @brief Universal Serial Bus Full Speed Device
520  */
521 
522 typedef struct
523 {
524  __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
525  __IO uint16_t RESERVED0; /*!< Reserved */
526  __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
527  __IO uint16_t RESERVED1; /*!< Reserved */
528  __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
529  __IO uint16_t RESERVED2; /*!< Reserved */
530  __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
531  __IO uint16_t RESERVED3; /*!< Reserved */
532  __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
533  __IO uint16_t RESERVED4; /*!< Reserved */
534  __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
535  __IO uint16_t RESERVED5; /*!< Reserved */
536  __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
537  __IO uint16_t RESERVED6; /*!< Reserved */
538  __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
539  __IO uint16_t RESERVED7[17]; /*!< Reserved */
540  __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
541  __IO uint16_t RESERVED8; /*!< Reserved */
542  __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
543  __IO uint16_t RESERVED9; /*!< Reserved */
544  __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
545  __IO uint16_t RESERVEDA; /*!< Reserved */
546  __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
547  __IO uint16_t RESERVEDB; /*!< Reserved */
548  __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
549  __IO uint16_t RESERVEDC; /*!< Reserved */
550 } USB_TypeDef;
551 
552 
553 /**
554  * @brief Window WATCHDOG
555  */
556 
557 typedef struct
558 {
559  __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
560  __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
561  __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
562 } WWDG_TypeDef;
563 
564 /**
565  * @}
566  */
567 
568 /** @addtogroup Peripheral_memory_map
569  * @{
570  */
571 
572 
573 #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */
574 #define FLASH_BANK1_END 0x0801FFFFUL /*!< FLASH END address of bank1 */
575 #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */
576 #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */
577 
578 #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */
579 #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */
580 
581 
582 /*!< Peripheral memory map */
583 #define APB1PERIPH_BASE PERIPH_BASE
584 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
585 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)
586 
587 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)
588 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)
589 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)
590 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)
591 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)
592 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)
593 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)
594 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)
595 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)
596 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)
597 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)
598 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)
599 #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)
600 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)
601 #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)
602 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)
603 #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)
604 #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)
605 #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)
606 #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)
607 #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)
608 #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)
609 #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)
610 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)
611 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)
612 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)
613 
614 
615 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)
616 #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)
617 #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)
618 #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)
619 #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)
620 #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)
621 #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)
622 #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)
623 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)
624 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)
625 
626 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */
627 #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */
628 #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */
629 #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */
630 
631 
632 
633 #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */
634 
635 /* USB device FS */
636 #define USB_BASE (APB1PERIPH_BASE + 0x00005C00UL) /*!< USB_IP Peripheral Registers base address */
637 #define USB_PMAADDR (APB1PERIPH_BASE + 0x00006000UL) /*!< USB_IP Packet Memory Area base address */
638 
639 
640 /**
641  * @}
642  */
643 
644 /** @addtogroup Peripheral_declaration
645  * @{
646  */
647 
648 #define TIM2 ((TIM_TypeDef *)TIM2_BASE)
649 #define TIM3 ((TIM_TypeDef *)TIM3_BASE)
650 #define TIM4 ((TIM_TypeDef *)TIM4_BASE)
651 #define RTC ((RTC_TypeDef *)RTC_BASE)
652 #define WWDG ((WWDG_TypeDef *)WWDG_BASE)
653 #define IWDG ((IWDG_TypeDef *)IWDG_BASE)
654 #define SPI2 ((SPI_TypeDef *)SPI2_BASE)
655 #define USART2 ((USART_TypeDef *)USART2_BASE)
656 #define USART3 ((USART_TypeDef *)USART3_BASE)
657 #define I2C1 ((I2C_TypeDef *)I2C1_BASE)
658 #define I2C2 ((I2C_TypeDef *)I2C2_BASE)
659 #define USB ((USB_TypeDef *)USB_BASE)
660 #define CAN1 ((CAN_TypeDef *)CAN1_BASE)
661 #define BKP ((BKP_TypeDef *)BKP_BASE)
662 #define PWR ((PWR_TypeDef *)PWR_BASE)
663 #define AFIO ((AFIO_TypeDef *)AFIO_BASE)
664 #define EXTI ((EXTI_TypeDef *)EXTI_BASE)
665 #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
666 #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE)
667 #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
668 #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
669 #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
670 #define ADC1 ((ADC_TypeDef *)ADC1_BASE)
671 #define ADC2 ((ADC_TypeDef *)ADC2_BASE)
672 #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)
673 #define TIM1 ((TIM_TypeDef *)TIM1_BASE)
674 #define SPI1 ((SPI_TypeDef *)SPI1_BASE)
675 #define USART1 ((USART_TypeDef *)USART1_BASE)
676 #define DMA1 ((DMA_TypeDef *)DMA1_BASE)
677 #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
678 #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
679 #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
680 #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
681 #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
682 #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
683 #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
684 #define RCC ((RCC_TypeDef *)RCC_BASE)
685 #define CRC ((CRC_TypeDef *)CRC_BASE)
686 #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
687 #define OB ((OB_TypeDef *)OB_BASE)
688 #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
689 
690 
691 /**
692  * @}
693  */
694 
695 /** @addtogroup Exported_constants
696  * @{
697  */
698 
699  /** @addtogroup Peripheral_Registers_Bits_Definition
700  * @{
701  */
702 
703 /******************************************************************************/
704 /* Peripheral Registers_Bits_Definition */
705 /******************************************************************************/
706 
707 /******************************************************************************/
708 /* */
709 /* CRC calculation unit (CRC) */
710 /* */
711 /******************************************************************************/
712 
713 /******************* Bit definition for CRC_DR register *********************/
714 #define CRC_DR_DR_Pos (0U)
715 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
716 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
717 
718 /******************* Bit definition for CRC_IDR register ********************/
719 #define CRC_IDR_IDR_Pos (0U)
720 #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */
721 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */
722 
723 /******************** Bit definition for CRC_CR register ********************/
724 #define CRC_CR_RESET_Pos (0U)
725 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
726 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */
727 
728 /******************************************************************************/
729 /* */
730 /* Power Control */
731 /* */
732 /******************************************************************************/
733 
734 /******************** Bit definition for PWR_CR register ********************/
735 #define PWR_CR_LPDS_Pos (0U)
736 #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
737 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */
738 #define PWR_CR_PDDS_Pos (1U)
739 #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
740 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
741 #define PWR_CR_CWUF_Pos (2U)
742 #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
743 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
744 #define PWR_CR_CSBF_Pos (3U)
745 #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
746 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
747 #define PWR_CR_PVDE_Pos (4U)
748 #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
749 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
750 
751 #define PWR_CR_PLS_Pos (5U)
752 #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
753 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
754 #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */
755 #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */
756 #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */
757 
758 /*!< PVD level configuration */
759 #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */
760 #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */
761 #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */
762 #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */
763 #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */
764 #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */
765 #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */
766 #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */
767 
768 /* Legacy defines */
769 #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0
770 #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1
771 #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2
772 #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3
773 #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4
774 #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5
775 #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6
776 #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7
777 
778 #define PWR_CR_DBP_Pos (8U)
779 #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */
780 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
781 
782 
783 /******************* Bit definition for PWR_CSR register ********************/
784 #define PWR_CSR_WUF_Pos (0U)
785 #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
786 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
787 #define PWR_CSR_SBF_Pos (1U)
788 #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
789 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
790 #define PWR_CSR_PVDO_Pos (2U)
791 #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
792 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
793 #define PWR_CSR_EWUP_Pos (8U)
794 #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */
795 #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */
796 
797 /******************************************************************************/
798 /* */
799 /* Backup registers */
800 /* */
801 /******************************************************************************/
802 
803 /******************* Bit definition for BKP_DR1 register ********************/
804 #define BKP_DR1_D_Pos (0U)
805 #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */
806 #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */
807 
808 /******************* Bit definition for BKP_DR2 register ********************/
809 #define BKP_DR2_D_Pos (0U)
810 #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */
811 #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */
812 
813 /******************* Bit definition for BKP_DR3 register ********************/
814 #define BKP_DR3_D_Pos (0U)
815 #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */
816 #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */
817 
818 /******************* Bit definition for BKP_DR4 register ********************/
819 #define BKP_DR4_D_Pos (0U)
820 #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */
821 #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */
822 
823 /******************* Bit definition for BKP_DR5 register ********************/
824 #define BKP_DR5_D_Pos (0U)
825 #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */
826 #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */
827 
828 /******************* Bit definition for BKP_DR6 register ********************/
829 #define BKP_DR6_D_Pos (0U)
830 #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */
831 #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */
832 
833 /******************* Bit definition for BKP_DR7 register ********************/
834 #define BKP_DR7_D_Pos (0U)
835 #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */
836 #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */
837 
838 /******************* Bit definition for BKP_DR8 register ********************/
839 #define BKP_DR8_D_Pos (0U)
840 #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */
841 #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */
842 
843 /******************* Bit definition for BKP_DR9 register ********************/
844 #define BKP_DR9_D_Pos (0U)
845 #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */
846 #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */
847 
848 /******************* Bit definition for BKP_DR10 register *******************/
849 #define BKP_DR10_D_Pos (0U)
850 #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */
851 #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */
852 
853 #define RTC_BKP_NUMBER 10
854 
855 /****************** Bit definition for BKP_RTCCR register *******************/
856 #define BKP_RTCCR_CAL_Pos (0U)
857 #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */
858 #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */
859 #define BKP_RTCCR_CCO_Pos (7U)
860 #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */
861 #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */
862 #define BKP_RTCCR_ASOE_Pos (8U)
863 #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */
864 #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */
865 #define BKP_RTCCR_ASOS_Pos (9U)
866 #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */
867 #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */
868 
869 /******************** Bit definition for BKP_CR register ********************/
870 #define BKP_CR_TPE_Pos (0U)
871 #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */
872 #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */
873 #define BKP_CR_TPAL_Pos (1U)
874 #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */
875 #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */
876 
877 /******************* Bit definition for BKP_CSR register ********************/
878 #define BKP_CSR_CTE_Pos (0U)
879 #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */
880 #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */
881 #define BKP_CSR_CTI_Pos (1U)
882 #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */
883 #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */
884 #define BKP_CSR_TPIE_Pos (2U)
885 #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */
886 #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */
887 #define BKP_CSR_TEF_Pos (8U)
888 #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */
889 #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */
890 #define BKP_CSR_TIF_Pos (9U)
891 #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */
892 #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */
893 
894 /******************************************************************************/
895 /* */
896 /* Reset and Clock Control */
897 /* */
898 /******************************************************************************/
899 
900 /******************** Bit definition for RCC_CR register ********************/
901 #define RCC_CR_HSION_Pos (0U)
902 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
903 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
904 #define RCC_CR_HSIRDY_Pos (1U)
905 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
906 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
907 #define RCC_CR_HSITRIM_Pos (3U)
908 #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
909 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
910 #define RCC_CR_HSICAL_Pos (8U)
911 #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
912 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
913 #define RCC_CR_HSEON_Pos (16U)
914 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
915 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
916 #define RCC_CR_HSERDY_Pos (17U)
917 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
918 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
919 #define RCC_CR_HSEBYP_Pos (18U)
920 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
921 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
922 #define RCC_CR_CSSON_Pos (19U)
923 #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
924 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
925 #define RCC_CR_PLLON_Pos (24U)
926 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
927 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
928 #define RCC_CR_PLLRDY_Pos (25U)
929 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
930 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
931 
932 
933 /******************* Bit definition for RCC_CFGR register *******************/
934 /*!< SW configuration */
935 #define RCC_CFGR_SW_Pos (0U)
936 #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
937 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
938 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
939 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
940 
941 #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */
942 #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */
943 #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */
944 
945 /*!< SWS configuration */
946 #define RCC_CFGR_SWS_Pos (2U)
947 #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
948 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
949 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
950 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
951 
952 #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */
953 #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */
954 #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */
955 
956 /*!< HPRE configuration */
957 #define RCC_CFGR_HPRE_Pos (4U)
958 #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
959 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
960 #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
961 #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
962 #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
963 #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
964 
965 #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */
966 #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */
967 #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */
968 #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */
969 #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */
970 #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */
971 #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */
972 #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */
973 #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */
974 
975 /*!< PPRE1 configuration */
976 #define RCC_CFGR_PPRE1_Pos (8U)
977 #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */
978 #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */
979 #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */
980 #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */
981 #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */
982 
983 #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */
984 #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */
985 #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */
986 #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */
987 #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */
988 
989 /*!< PPRE2 configuration */
990 #define RCC_CFGR_PPRE2_Pos (11U)
991 #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */
992 #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */
993 #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */
994 #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */
995 #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */
996 
997 #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */
998 #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */
999 #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */
1000 #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */
1001 #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */
1002 
1003 /*!< ADCPPRE configuration */
1004 #define RCC_CFGR_ADCPRE_Pos (14U)
1005 #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */
1006 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */
1007 #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
1008 #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */
1009 
1010 #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */
1011 #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */
1012 #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */
1013 #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */
1014 
1015 #define RCC_CFGR_PLLSRC_Pos (16U)
1016 #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
1017 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
1018 
1019 #define RCC_CFGR_PLLXTPRE_Pos (17U)
1020 #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
1021 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
1022 
1023 /*!< PLLMUL configuration */
1024 #define RCC_CFGR_PLLMULL_Pos (18U)
1025 #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */
1026 #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
1027 #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */
1028 #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */
1029 #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */
1030 #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */
1031 
1032 #define RCC_CFGR_PLLXTPRE_HSE 0x00000000U /*!< HSE clock not divided for PLL entry */
1033 #define RCC_CFGR_PLLXTPRE_HSE_DIV2 0x00020000U /*!< HSE clock divided by 2 for PLL entry */
1034 
1035 #define RCC_CFGR_PLLMULL2 0x00000000U /*!< PLL input clock*2 */
1036 #define RCC_CFGR_PLLMULL3_Pos (18U)
1037 #define RCC_CFGR_PLLMULL3_Msk (0x1UL << RCC_CFGR_PLLMULL3_Pos) /*!< 0x00040000 */
1038 #define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMULL3_Msk /*!< PLL input clock*3 */
1039 #define RCC_CFGR_PLLMULL4_Pos (19U)
1040 #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */
1041 #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock*4 */
1042 #define RCC_CFGR_PLLMULL5_Pos (18U)
1043 #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */
1044 #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock*5 */
1045 #define RCC_CFGR_PLLMULL6_Pos (20U)
1046 #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */
1047 #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock*6 */
1048 #define RCC_CFGR_PLLMULL7_Pos (18U)
1049 #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */
1050 #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock*7 */
1051 #define RCC_CFGR_PLLMULL8_Pos (19U)
1052 #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */
1053 #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock*8 */
1054 #define RCC_CFGR_PLLMULL9_Pos (18U)
1055 #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */
1056 #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock*9 */
1057 #define RCC_CFGR_PLLMULL10_Pos (21U)
1058 #define RCC_CFGR_PLLMULL10_Msk (0x1UL << RCC_CFGR_PLLMULL10_Pos) /*!< 0x00200000 */
1059 #define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMULL10_Msk /*!< PLL input clock10 */
1060 #define RCC_CFGR_PLLMULL11_Pos (18U)
1061 #define RCC_CFGR_PLLMULL11_Msk (0x9UL << RCC_CFGR_PLLMULL11_Pos) /*!< 0x00240000 */
1062 #define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMULL11_Msk /*!< PLL input clock*11 */
1063 #define RCC_CFGR_PLLMULL12_Pos (19U)
1064 #define RCC_CFGR_PLLMULL12_Msk (0x5UL << RCC_CFGR_PLLMULL12_Pos) /*!< 0x00280000 */
1065 #define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMULL12_Msk /*!< PLL input clock*12 */
1066 #define RCC_CFGR_PLLMULL13_Pos (18U)
1067 #define RCC_CFGR_PLLMULL13_Msk (0xBUL << RCC_CFGR_PLLMULL13_Pos) /*!< 0x002C0000 */
1068 #define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMULL13_Msk /*!< PLL input clock*13 */
1069 #define RCC_CFGR_PLLMULL14_Pos (20U)
1070 #define RCC_CFGR_PLLMULL14_Msk (0x3UL << RCC_CFGR_PLLMULL14_Pos) /*!< 0x00300000 */
1071 #define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMULL14_Msk /*!< PLL input clock*14 */
1072 #define RCC_CFGR_PLLMULL15_Pos (18U)
1073 #define RCC_CFGR_PLLMULL15_Msk (0xDUL << RCC_CFGR_PLLMULL15_Pos) /*!< 0x00340000 */
1074 #define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMULL15_Msk /*!< PLL input clock*15 */
1075 #define RCC_CFGR_PLLMULL16_Pos (19U)
1076 #define RCC_CFGR_PLLMULL16_Msk (0x7UL << RCC_CFGR_PLLMULL16_Pos) /*!< 0x00380000 */
1077 #define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMULL16_Msk /*!< PLL input clock*16 */
1078 #define RCC_CFGR_USBPRE_Pos (22U)
1079 #define RCC_CFGR_USBPRE_Msk (0x1UL << RCC_CFGR_USBPRE_Pos) /*!< 0x00400000 */
1080 #define RCC_CFGR_USBPRE RCC_CFGR_USBPRE_Msk /*!< USB Device prescaler */
1081 
1082 /*!< MCO configuration */
1083 #define RCC_CFGR_MCO_Pos (24U)
1084 #define RCC_CFGR_MCO_Msk (0x7UL << RCC_CFGR_MCO_Pos) /*!< 0x07000000 */
1085 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[2:0] bits (Microcontroller Clock Output) */
1086 #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
1087 #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
1088 #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
1089 
1090 #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */
1091 #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */
1092 #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */
1093 #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */
1094 #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */
1095 
1096  /* Reference defines */
1097  #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
1098  #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
1099  #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
1100  #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
1101  #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
1102  #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
1103  #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
1104  #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
1105  #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2
1106 
1107 /*!<****************** Bit definition for RCC_CIR register ********************/
1108 #define RCC_CIR_LSIRDYF_Pos (0U)
1109 #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
1110 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
1111 #define RCC_CIR_LSERDYF_Pos (1U)
1112 #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
1113 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
1114 #define RCC_CIR_HSIRDYF_Pos (2U)
1115 #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
1116 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
1117 #define RCC_CIR_HSERDYF_Pos (3U)
1118 #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
1119 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
1120 #define RCC_CIR_PLLRDYF_Pos (4U)
1121 #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
1122 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
1123 #define RCC_CIR_CSSF_Pos (7U)
1124 #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
1125 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
1126 #define RCC_CIR_LSIRDYIE_Pos (8U)
1127 #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
1128 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
1129 #define RCC_CIR_LSERDYIE_Pos (9U)
1130 #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
1131 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
1132 #define RCC_CIR_HSIRDYIE_Pos (10U)
1133 #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
1134 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
1135 #define RCC_CIR_HSERDYIE_Pos (11U)
1136 #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
1137 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
1138 #define RCC_CIR_PLLRDYIE_Pos (12U)
1139 #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
1140 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
1141 #define RCC_CIR_LSIRDYC_Pos (16U)
1142 #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
1143 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
1144 #define RCC_CIR_LSERDYC_Pos (17U)
1145 #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
1146 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
1147 #define RCC_CIR_HSIRDYC_Pos (18U)
1148 #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
1149 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
1150 #define RCC_CIR_HSERDYC_Pos (19U)
1151 #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
1152 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
1153 #define RCC_CIR_PLLRDYC_Pos (20U)
1154 #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
1155 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
1156 #define RCC_CIR_CSSC_Pos (23U)
1157 #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
1158 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
1159 
1160 
1161 /***************** Bit definition for RCC_APB2RSTR register *****************/
1162 #define RCC_APB2RSTR_AFIORST_Pos (0U)
1163 #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */
1164 #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */
1165 #define RCC_APB2RSTR_IOPARST_Pos (2U)
1166 #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */
1167 #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */
1168 #define RCC_APB2RSTR_IOPBRST_Pos (3U)
1169 #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */
1170 #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */
1171 #define RCC_APB2RSTR_IOPCRST_Pos (4U)
1172 #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */
1173 #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */
1174 #define RCC_APB2RSTR_IOPDRST_Pos (5U)
1175 #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */
1176 #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */
1177 #define RCC_APB2RSTR_ADC1RST_Pos (9U)
1178 #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
1179 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */
1180 
1181 #define RCC_APB2RSTR_ADC2RST_Pos (10U)
1182 #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */
1183 #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */
1184 
1185 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
1186 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
1187 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */
1188 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
1189 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
1190 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */
1191 #define RCC_APB2RSTR_USART1RST_Pos (14U)
1192 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
1193 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
1194 
1195 
1196 #define RCC_APB2RSTR_IOPERST_Pos (6U)
1197 #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */
1198 #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */
1199 
1200 
1201 
1202 
1203 /***************** Bit definition for RCC_APB1RSTR register *****************/
1204 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
1205 #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
1206 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
1207 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
1208 #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
1209 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
1210 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
1211 #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
1212 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
1213 #define RCC_APB1RSTR_USART2RST_Pos (17U)
1214 #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
1215 #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */
1216 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
1217 #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
1218 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
1219 
1220 #define RCC_APB1RSTR_CAN1RST_Pos (25U)
1221 #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */
1222 #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */
1223 
1224 #define RCC_APB1RSTR_BKPRST_Pos (27U)
1225 #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */
1226 #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */
1227 #define RCC_APB1RSTR_PWRRST_Pos (28U)
1228 #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
1229 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */
1230 
1231 #define RCC_APB1RSTR_TIM4RST_Pos (2U)
1232 #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
1233 #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */
1234 #define RCC_APB1RSTR_SPI2RST_Pos (14U)
1235 #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
1236 #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */
1237 #define RCC_APB1RSTR_USART3RST_Pos (18U)
1238 #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
1239 #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */
1240 #define RCC_APB1RSTR_I2C2RST_Pos (22U)
1241 #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
1242 #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */
1243 
1244 #define RCC_APB1RSTR_USBRST_Pos (23U)
1245 #define RCC_APB1RSTR_USBRST_Msk (0x1UL << RCC_APB1RSTR_USBRST_Pos) /*!< 0x00800000 */
1246 #define RCC_APB1RSTR_USBRST RCC_APB1RSTR_USBRST_Msk /*!< USB Device reset */
1247 
1248 
1249 
1250 
1251 
1252 
1253 /****************** Bit definition for RCC_AHBENR register ******************/
1254 #define RCC_AHBENR_DMA1EN_Pos (0U)
1255 #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */
1256 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */
1257 #define RCC_AHBENR_SRAMEN_Pos (2U)
1258 #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
1259 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
1260 #define RCC_AHBENR_FLITFEN_Pos (4U)
1261 #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
1262 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
1263 #define RCC_AHBENR_CRCEN_Pos (6U)
1264 #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
1265 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
1266 
1267 
1268 
1269 
1270 /****************** Bit definition for RCC_APB2ENR register *****************/
1271 #define RCC_APB2ENR_AFIOEN_Pos (0U)
1272 #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */
1273 #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */
1274 #define RCC_APB2ENR_IOPAEN_Pos (2U)
1275 #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */
1276 #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */
1277 #define RCC_APB2ENR_IOPBEN_Pos (3U)
1278 #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */
1279 #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */
1280 #define RCC_APB2ENR_IOPCEN_Pos (4U)
1281 #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */
1282 #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */
1283 #define RCC_APB2ENR_IOPDEN_Pos (5U)
1284 #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */
1285 #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */
1286 #define RCC_APB2ENR_ADC1EN_Pos (9U)
1287 #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */
1288 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */
1289 
1290 #define RCC_APB2ENR_ADC2EN_Pos (10U)
1291 #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */
1292 #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */
1293 
1294 #define RCC_APB2ENR_TIM1EN_Pos (11U)
1295 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
1296 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */
1297 #define RCC_APB2ENR_SPI1EN_Pos (12U)
1298 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
1299 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */
1300 #define RCC_APB2ENR_USART1EN_Pos (14U)
1301 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
1302 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
1303 
1304 
1305 #define RCC_APB2ENR_IOPEEN_Pos (6U)
1306 #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */
1307 #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */
1308 
1309 
1310 
1311 
1312 /***************** Bit definition for RCC_APB1ENR register ******************/
1313 #define RCC_APB1ENR_TIM2EN_Pos (0U)
1314 #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
1315 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/
1316 #define RCC_APB1ENR_TIM3EN_Pos (1U)
1317 #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
1318 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
1319 #define RCC_APB1ENR_WWDGEN_Pos (11U)
1320 #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
1321 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
1322 #define RCC_APB1ENR_USART2EN_Pos (17U)
1323 #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
1324 #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */
1325 #define RCC_APB1ENR_I2C1EN_Pos (21U)
1326 #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
1327 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */
1328 
1329 #define RCC_APB1ENR_CAN1EN_Pos (25U)
1330 #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */
1331 #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */
1332 
1333 #define RCC_APB1ENR_BKPEN_Pos (27U)
1334 #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */
1335 #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */
1336 #define RCC_APB1ENR_PWREN_Pos (28U)
1337 #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
1338 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */
1339 
1340 #define RCC_APB1ENR_TIM4EN_Pos (2U)
1341 #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */
1342 #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */
1343 #define RCC_APB1ENR_SPI2EN_Pos (14U)
1344 #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */
1345 #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */
1346 #define RCC_APB1ENR_USART3EN_Pos (18U)
1347 #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
1348 #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */
1349 #define RCC_APB1ENR_I2C2EN_Pos (22U)
1350 #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */
1351 #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */
1352 
1353 #define RCC_APB1ENR_USBEN_Pos (23U)
1354 #define RCC_APB1ENR_USBEN_Msk (0x1UL << RCC_APB1ENR_USBEN_Pos) /*!< 0x00800000 */
1355 #define RCC_APB1ENR_USBEN RCC_APB1ENR_USBEN_Msk /*!< USB Device clock enable */
1356 
1357 
1358 
1359 
1360 
1361 
1362 /******************* Bit definition for RCC_BDCR register *******************/
1363 #define RCC_BDCR_LSEON_Pos (0U)
1364 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
1365 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
1366 #define RCC_BDCR_LSERDY_Pos (1U)
1367 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
1368 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
1369 #define RCC_BDCR_LSEBYP_Pos (2U)
1370 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
1371 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
1372 
1373 #define RCC_BDCR_RTCSEL_Pos (8U)
1374 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
1375 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
1376 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
1377 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
1378 
1379 /*!< RTC congiguration */
1380 #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */
1381 #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */
1382 #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */
1383 #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */
1384 
1385 #define RCC_BDCR_RTCEN_Pos (15U)
1386 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
1387 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
1388 #define RCC_BDCR_BDRST_Pos (16U)
1389 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
1390 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
1391 
1392 /******************* Bit definition for RCC_CSR register ********************/
1393 #define RCC_CSR_LSION_Pos (0U)
1394 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
1395 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
1396 #define RCC_CSR_LSIRDY_Pos (1U)
1397 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
1398 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
1399 #define RCC_CSR_RMVF_Pos (24U)
1400 #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
1401 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
1402 #define RCC_CSR_PINRSTF_Pos (26U)
1403 #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
1404 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
1405 #define RCC_CSR_PORRSTF_Pos (27U)
1406 #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
1407 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
1408 #define RCC_CSR_SFTRSTF_Pos (28U)
1409 #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
1410 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
1411 #define RCC_CSR_IWDGRSTF_Pos (29U)
1412 #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
1413 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
1414 #define RCC_CSR_WWDGRSTF_Pos (30U)
1415 #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
1416 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
1417 #define RCC_CSR_LPWRRSTF_Pos (31U)
1418 #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
1419 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
1420 
1421 
1422 
1423 /******************************************************************************/
1424 /* */
1425 /* General Purpose and Alternate Function I/O */
1426 /* */
1427 /******************************************************************************/
1428 
1429 /******************* Bit definition for GPIO_CRL register *******************/
1430 #define GPIO_CRL_MODE_Pos (0U)
1431 #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */
1432 #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */
1433 
1434 #define GPIO_CRL_MODE0_Pos (0U)
1435 #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */
1436 #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */
1437 #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */
1438 #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */
1439 
1440 #define GPIO_CRL_MODE1_Pos (4U)
1441 #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */
1442 #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */
1443 #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */
1444 #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */
1445 
1446 #define GPIO_CRL_MODE2_Pos (8U)
1447 #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */
1448 #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */
1449 #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */
1450 #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */
1451 
1452 #define GPIO_CRL_MODE3_Pos (12U)
1453 #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */
1454 #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */
1455 #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */
1456 #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */
1457 
1458 #define GPIO_CRL_MODE4_Pos (16U)
1459 #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */
1460 #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */
1461 #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */
1462 #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */
1463 
1464 #define GPIO_CRL_MODE5_Pos (20U)
1465 #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */
1466 #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */
1467 #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */
1468 #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */
1469 
1470 #define GPIO_CRL_MODE6_Pos (24U)
1471 #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */
1472 #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */
1473 #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */
1474 #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */
1475 
1476 #define GPIO_CRL_MODE7_Pos (28U)
1477 #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */
1478 #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */
1479 #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */
1480 #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */
1481 
1482 #define GPIO_CRL_CNF_Pos (2U)
1483 #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */
1484 #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */
1485 
1486 #define GPIO_CRL_CNF0_Pos (2U)
1487 #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */
1488 #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */
1489 #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */
1490 #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */
1491 
1492 #define GPIO_CRL_CNF1_Pos (6U)
1493 #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */
1494 #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */
1495 #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */
1496 #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */
1497 
1498 #define GPIO_CRL_CNF2_Pos (10U)
1499 #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */
1500 #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */
1501 #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */
1502 #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */
1503 
1504 #define GPIO_CRL_CNF3_Pos (14U)
1505 #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */
1506 #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */
1507 #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */
1508 #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */
1509 
1510 #define GPIO_CRL_CNF4_Pos (18U)
1511 #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */
1512 #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */
1513 #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */
1514 #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */
1515 
1516 #define GPIO_CRL_CNF5_Pos (22U)
1517 #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */
1518 #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */
1519 #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */
1520 #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */
1521 
1522 #define GPIO_CRL_CNF6_Pos (26U)
1523 #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */
1524 #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */
1525 #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */
1526 #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */
1527 
1528 #define GPIO_CRL_CNF7_Pos (30U)
1529 #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */
1530 #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */
1531 #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */
1532 #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */
1533 
1534 /******************* Bit definition for GPIO_CRH register *******************/
1535 #define GPIO_CRH_MODE_Pos (0U)
1536 #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */
1537 #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */
1538 
1539 #define GPIO_CRH_MODE8_Pos (0U)
1540 #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */
1541 #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */
1542 #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */
1543 #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */
1544 
1545 #define GPIO_CRH_MODE9_Pos (4U)
1546 #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */
1547 #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */
1548 #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */
1549 #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */
1550 
1551 #define GPIO_CRH_MODE10_Pos (8U)
1552 #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */
1553 #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */
1554 #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */
1555 #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */
1556 
1557 #define GPIO_CRH_MODE11_Pos (12U)
1558 #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */
1559 #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */
1560 #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */
1561 #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */
1562 
1563 #define GPIO_CRH_MODE12_Pos (16U)
1564 #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */
1565 #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */
1566 #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */
1567 #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */
1568 
1569 #define GPIO_CRH_MODE13_Pos (20U)
1570 #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */
1571 #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */
1572 #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */
1573 #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */
1574 
1575 #define GPIO_CRH_MODE14_Pos (24U)
1576 #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */
1577 #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */
1578 #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */
1579 #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */
1580 
1581 #define GPIO_CRH_MODE15_Pos (28U)
1582 #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */
1583 #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */
1584 #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */
1585 #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */
1586 
1587 #define GPIO_CRH_CNF_Pos (2U)
1588 #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */
1589 #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */
1590 
1591 #define GPIO_CRH_CNF8_Pos (2U)
1592 #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */
1593 #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */
1594 #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */
1595 #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */
1596 
1597 #define GPIO_CRH_CNF9_Pos (6U)
1598 #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */
1599 #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */
1600 #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */
1601 #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */
1602 
1603 #define GPIO_CRH_CNF10_Pos (10U)
1604 #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */
1605 #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */
1606 #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */
1607 #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */
1608 
1609 #define GPIO_CRH_CNF11_Pos (14U)
1610 #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */
1611 #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */
1612 #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */
1613 #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */
1614 
1615 #define GPIO_CRH_CNF12_Pos (18U)
1616 #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */
1617 #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */
1618 #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */
1619 #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */
1620 
1621 #define GPIO_CRH_CNF13_Pos (22U)
1622 #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */
1623 #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */
1624 #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */
1625 #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */
1626 
1627 #define GPIO_CRH_CNF14_Pos (26U)
1628 #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */
1629 #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */
1630 #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */
1631 #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */
1632 
1633 #define GPIO_CRH_CNF15_Pos (30U)
1634 #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */
1635 #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */
1636 #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */
1637 #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */
1638 
1639 /*!<****************** Bit definition for GPIO_IDR register *******************/
1640 #define GPIO_IDR_IDR0_Pos (0U)
1641 #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */
1642 #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */
1643 #define GPIO_IDR_IDR1_Pos (1U)
1644 #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */
1645 #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */
1646 #define GPIO_IDR_IDR2_Pos (2U)
1647 #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */
1648 #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */
1649 #define GPIO_IDR_IDR3_Pos (3U)
1650 #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */
1651 #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */
1652 #define GPIO_IDR_IDR4_Pos (4U)
1653 #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */
1654 #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */
1655 #define GPIO_IDR_IDR5_Pos (5U)
1656 #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */
1657 #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */
1658 #define GPIO_IDR_IDR6_Pos (6U)
1659 #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */
1660 #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */
1661 #define GPIO_IDR_IDR7_Pos (7U)
1662 #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */
1663 #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */
1664 #define GPIO_IDR_IDR8_Pos (8U)
1665 #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */
1666 #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */
1667 #define GPIO_IDR_IDR9_Pos (9U)
1668 #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */
1669 #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */
1670 #define GPIO_IDR_IDR10_Pos (10U)
1671 #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */
1672 #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */
1673 #define GPIO_IDR_IDR11_Pos (11U)
1674 #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */
1675 #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */
1676 #define GPIO_IDR_IDR12_Pos (12U)
1677 #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */
1678 #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */
1679 #define GPIO_IDR_IDR13_Pos (13U)
1680 #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */
1681 #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */
1682 #define GPIO_IDR_IDR14_Pos (14U)
1683 #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */
1684 #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */
1685 #define GPIO_IDR_IDR15_Pos (15U)
1686 #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */
1687 #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */
1688 
1689 /******************* Bit definition for GPIO_ODR register *******************/
1690 #define GPIO_ODR_ODR0_Pos (0U)
1691 #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */
1692 #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */
1693 #define GPIO_ODR_ODR1_Pos (1U)
1694 #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */
1695 #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */
1696 #define GPIO_ODR_ODR2_Pos (2U)
1697 #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */
1698 #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */
1699 #define GPIO_ODR_ODR3_Pos (3U)
1700 #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */
1701 #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */
1702 #define GPIO_ODR_ODR4_Pos (4U)
1703 #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */
1704 #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */
1705 #define GPIO_ODR_ODR5_Pos (5U)
1706 #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */
1707 #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */
1708 #define GPIO_ODR_ODR6_Pos (6U)
1709 #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */
1710 #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */
1711 #define GPIO_ODR_ODR7_Pos (7U)
1712 #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */
1713 #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */
1714 #define GPIO_ODR_ODR8_Pos (8U)
1715 #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */
1716 #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */
1717 #define GPIO_ODR_ODR9_Pos (9U)
1718 #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */
1719 #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */
1720 #define GPIO_ODR_ODR10_Pos (10U)
1721 #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */
1722 #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */
1723 #define GPIO_ODR_ODR11_Pos (11U)
1724 #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */
1725 #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */
1726 #define GPIO_ODR_ODR12_Pos (12U)
1727 #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */
1728 #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */
1729 #define GPIO_ODR_ODR13_Pos (13U)
1730 #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */
1731 #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */
1732 #define GPIO_ODR_ODR14_Pos (14U)
1733 #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */
1734 #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */
1735 #define GPIO_ODR_ODR15_Pos (15U)
1736 #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */
1737 #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */
1738 
1739 /****************** Bit definition for GPIO_BSRR register *******************/
1740 #define GPIO_BSRR_BS0_Pos (0U)
1741 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
1742 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */
1743 #define GPIO_BSRR_BS1_Pos (1U)
1744 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
1745 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */
1746 #define GPIO_BSRR_BS2_Pos (2U)
1747 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
1748 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */
1749 #define GPIO_BSRR_BS3_Pos (3U)
1750 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
1751 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */
1752 #define GPIO_BSRR_BS4_Pos (4U)
1753 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
1754 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */
1755 #define GPIO_BSRR_BS5_Pos (5U)
1756 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
1757 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */
1758 #define GPIO_BSRR_BS6_Pos (6U)
1759 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
1760 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */
1761 #define GPIO_BSRR_BS7_Pos (7U)
1762 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
1763 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */
1764 #define GPIO_BSRR_BS8_Pos (8U)
1765 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
1766 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */
1767 #define GPIO_BSRR_BS9_Pos (9U)
1768 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
1769 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */
1770 #define GPIO_BSRR_BS10_Pos (10U)
1771 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
1772 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */
1773 #define GPIO_BSRR_BS11_Pos (11U)
1774 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
1775 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */
1776 #define GPIO_BSRR_BS12_Pos (12U)
1777 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
1778 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */
1779 #define GPIO_BSRR_BS13_Pos (13U)
1780 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
1781 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */
1782 #define GPIO_BSRR_BS14_Pos (14U)
1783 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
1784 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */
1785 #define GPIO_BSRR_BS15_Pos (15U)
1786 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
1787 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */
1788 
1789 #define GPIO_BSRR_BR0_Pos (16U)
1790 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
1791 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */
1792 #define GPIO_BSRR_BR1_Pos (17U)
1793 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
1794 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */
1795 #define GPIO_BSRR_BR2_Pos (18U)
1796 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
1797 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */
1798 #define GPIO_BSRR_BR3_Pos (19U)
1799 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
1800 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */
1801 #define GPIO_BSRR_BR4_Pos (20U)
1802 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
1803 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */
1804 #define GPIO_BSRR_BR5_Pos (21U)
1805 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
1806 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */
1807 #define GPIO_BSRR_BR6_Pos (22U)
1808 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
1809 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */
1810 #define GPIO_BSRR_BR7_Pos (23U)
1811 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
1812 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */
1813 #define GPIO_BSRR_BR8_Pos (24U)
1814 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
1815 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */
1816 #define GPIO_BSRR_BR9_Pos (25U)
1817 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
1818 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */
1819 #define GPIO_BSRR_BR10_Pos (26U)
1820 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
1821 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */
1822 #define GPIO_BSRR_BR11_Pos (27U)
1823 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
1824 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */
1825 #define GPIO_BSRR_BR12_Pos (28U)
1826 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
1827 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */
1828 #define GPIO_BSRR_BR13_Pos (29U)
1829 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
1830 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */
1831 #define GPIO_BSRR_BR14_Pos (30U)
1832 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
1833 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */
1834 #define GPIO_BSRR_BR15_Pos (31U)
1835 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
1836 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */
1837 
1838 /******************* Bit definition for GPIO_BRR register *******************/
1839 #define GPIO_BRR_BR0_Pos (0U)
1840 #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */
1841 #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */
1842 #define GPIO_BRR_BR1_Pos (1U)
1843 #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */
1844 #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */
1845 #define GPIO_BRR_BR2_Pos (2U)
1846 #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */
1847 #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */
1848 #define GPIO_BRR_BR3_Pos (3U)
1849 #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */
1850 #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */
1851 #define GPIO_BRR_BR4_Pos (4U)
1852 #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */
1853 #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */
1854 #define GPIO_BRR_BR5_Pos (5U)
1855 #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */
1856 #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */
1857 #define GPIO_BRR_BR6_Pos (6U)
1858 #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */
1859 #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */
1860 #define GPIO_BRR_BR7_Pos (7U)
1861 #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */
1862 #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */
1863 #define GPIO_BRR_BR8_Pos (8U)
1864 #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */
1865 #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */
1866 #define GPIO_BRR_BR9_Pos (9U)
1867 #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */
1868 #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */
1869 #define GPIO_BRR_BR10_Pos (10U)
1870 #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */
1871 #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */
1872 #define GPIO_BRR_BR11_Pos (11U)
1873 #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */
1874 #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */
1875 #define GPIO_BRR_BR12_Pos (12U)
1876 #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */
1877 #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */
1878 #define GPIO_BRR_BR13_Pos (13U)
1879 #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */
1880 #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */
1881 #define GPIO_BRR_BR14_Pos (14U)
1882 #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */
1883 #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */
1884 #define GPIO_BRR_BR15_Pos (15U)
1885 #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */
1886 #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */
1887 
1888 /****************** Bit definition for GPIO_LCKR register *******************/
1889 #define GPIO_LCKR_LCK0_Pos (0U)
1890 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
1891 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */
1892 #define GPIO_LCKR_LCK1_Pos (1U)
1893 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
1894 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */
1895 #define GPIO_LCKR_LCK2_Pos (2U)
1896 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
1897 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */
1898 #define GPIO_LCKR_LCK3_Pos (3U)
1899 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
1900 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */
1901 #define GPIO_LCKR_LCK4_Pos (4U)
1902 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
1903 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */
1904 #define GPIO_LCKR_LCK5_Pos (5U)
1905 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
1906 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */
1907 #define GPIO_LCKR_LCK6_Pos (6U)
1908 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
1909 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */
1910 #define GPIO_LCKR_LCK7_Pos (7U)
1911 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
1912 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */
1913 #define GPIO_LCKR_LCK8_Pos (8U)
1914 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
1915 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */
1916 #define GPIO_LCKR_LCK9_Pos (9U)
1917 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
1918 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */
1919 #define GPIO_LCKR_LCK10_Pos (10U)
1920 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
1921 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */
1922 #define GPIO_LCKR_LCK11_Pos (11U)
1923 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
1924 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */
1925 #define GPIO_LCKR_LCK12_Pos (12U)
1926 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
1927 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */
1928 #define GPIO_LCKR_LCK13_Pos (13U)
1929 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
1930 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */
1931 #define GPIO_LCKR_LCK14_Pos (14U)
1932 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
1933 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */
1934 #define GPIO_LCKR_LCK15_Pos (15U)
1935 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
1936 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */
1937 #define GPIO_LCKR_LCKK_Pos (16U)
1938 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
1939 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */
1940 
1941 /*----------------------------------------------------------------------------*/
1942 
1943 /****************** Bit definition for AFIO_EVCR register *******************/
1944 #define AFIO_EVCR_PIN_Pos (0U)
1945 #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */
1946 #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */
1947 #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */
1948 #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */
1949 #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */
1950 #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */
1951 
1952 /*!< PIN configuration */
1953 #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */
1954 #define AFIO_EVCR_PIN_PX1_Pos (0U)
1955 #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */
1956 #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */
1957 #define AFIO_EVCR_PIN_PX2_Pos (1U)
1958 #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */
1959 #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */
1960 #define AFIO_EVCR_PIN_PX3_Pos (0U)
1961 #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */
1962 #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */
1963 #define AFIO_EVCR_PIN_PX4_Pos (2U)
1964 #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */
1965 #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */
1966 #define AFIO_EVCR_PIN_PX5_Pos (0U)
1967 #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */
1968 #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */
1969 #define AFIO_EVCR_PIN_PX6_Pos (1U)
1970 #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */
1971 #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */
1972 #define AFIO_EVCR_PIN_PX7_Pos (0U)
1973 #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */
1974 #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */
1975 #define AFIO_EVCR_PIN_PX8_Pos (3U)
1976 #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */
1977 #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */
1978 #define AFIO_EVCR_PIN_PX9_Pos (0U)
1979 #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */
1980 #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */
1981 #define AFIO_EVCR_PIN_PX10_Pos (1U)
1982 #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */
1983 #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */
1984 #define AFIO_EVCR_PIN_PX11_Pos (0U)
1985 #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */
1986 #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */
1987 #define AFIO_EVCR_PIN_PX12_Pos (2U)
1988 #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */
1989 #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */
1990 #define AFIO_EVCR_PIN_PX13_Pos (0U)
1991 #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */
1992 #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */
1993 #define AFIO_EVCR_PIN_PX14_Pos (1U)
1994 #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */
1995 #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */
1996 #define AFIO_EVCR_PIN_PX15_Pos (0U)
1997 #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */
1998 #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */
1999 
2000 #define AFIO_EVCR_PORT_Pos (4U)
2001 #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */
2002 #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */
2003 #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */
2004 #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */
2005 #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */
2006 
2007 /*!< PORT configuration */
2008 #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */
2009 #define AFIO_EVCR_PORT_PB_Pos (4U)
2010 #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */
2011 #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */
2012 #define AFIO_EVCR_PORT_PC_Pos (5U)
2013 #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */
2014 #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */
2015 #define AFIO_EVCR_PORT_PD_Pos (4U)
2016 #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */
2017 #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */
2018 #define AFIO_EVCR_PORT_PE_Pos (6U)
2019 #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */
2020 #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */
2021 
2022 #define AFIO_EVCR_EVOE_Pos (7U)
2023 #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */
2024 #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */
2025 
2026 /****************** Bit definition for AFIO_MAPR register *******************/
2027 #define AFIO_MAPR_SPI1_REMAP_Pos (0U)
2028 #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */
2029 #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */
2030 #define AFIO_MAPR_I2C1_REMAP_Pos (1U)
2031 #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */
2032 #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */
2033 #define AFIO_MAPR_USART1_REMAP_Pos (2U)
2034 #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */
2035 #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */
2036 #define AFIO_MAPR_USART2_REMAP_Pos (3U)
2037 #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */
2038 #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */
2039 
2040 #define AFIO_MAPR_USART3_REMAP_Pos (4U)
2041 #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */
2042 #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */
2043 #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */
2044 #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */
2045 
2046 /* USART3_REMAP configuration */
2047 #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
2048 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)
2049 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */
2050 #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
2051 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)
2052 #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */
2053 #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
2054 
2055 #define AFIO_MAPR_TIM1_REMAP_Pos (6U)
2056 #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */
2057 #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */
2058 #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */
2059 #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */
2060 
2061 /*!< TIM1_REMAP configuration */
2062 #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
2063 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)
2064 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */
2065 #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
2066 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)
2067 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */
2068 #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
2069 
2070 #define AFIO_MAPR_TIM2_REMAP_Pos (8U)
2071 #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */
2072 #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */
2073 #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */
2074 #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */
2075 
2076 /*!< TIM2_REMAP configuration */
2077 #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
2078 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)
2079 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */
2080 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
2081 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)
2082 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */
2083 #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
2084 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)
2085 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */
2086 #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
2087 
2088 #define AFIO_MAPR_TIM3_REMAP_Pos (10U)
2089 #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */
2090 #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */
2091 #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */
2092 #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */
2093 
2094 /*!< TIM3_REMAP configuration */
2095 #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
2096 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)
2097 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */
2098 #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
2099 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)
2100 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */
2101 #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
2102 
2103 #define AFIO_MAPR_TIM4_REMAP_Pos (12U)
2104 #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */
2105 #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */
2106 
2107 #define AFIO_MAPR_CAN_REMAP_Pos (13U)
2108 #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */
2109 #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
2110 #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */
2111 #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */
2112 
2113 /*!< CAN_REMAP configuration */
2114 #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */
2115 #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)
2116 #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */
2117 #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */
2118 #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)
2119 #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */
2120 #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */
2121 
2122 #define AFIO_MAPR_PD01_REMAP_Pos (15U)
2123 #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */
2124 #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
2125 
2126 /*!< SWJ_CFG configuration */
2127 #define AFIO_MAPR_SWJ_CFG_Pos (24U)
2128 #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */
2129 #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
2130 #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */
2131 #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */
2132 #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */
2133 
2134 #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */
2135 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)
2136 #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */
2137 #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
2138 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)
2139 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */
2140 #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */
2141 #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)
2142 #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */
2143 #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */
2144 
2145 
2146 /***************** Bit definition for AFIO_EXTICR1 register *****************/
2147 #define AFIO_EXTICR1_EXTI0_Pos (0U)
2148 #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
2149 #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
2150 #define AFIO_EXTICR1_EXTI1_Pos (4U)
2151 #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
2152 #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
2153 #define AFIO_EXTICR1_EXTI2_Pos (8U)
2154 #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
2155 #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
2156 #define AFIO_EXTICR1_EXTI3_Pos (12U)
2157 #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
2158 #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
2159 
2160 /*!< EXTI0 configuration */
2161 #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */
2162 #define AFIO_EXTICR1_EXTI0_PB_Pos (0U)
2163 #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */
2164 #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */
2165 #define AFIO_EXTICR1_EXTI0_PC_Pos (1U)
2166 #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */
2167 #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */
2168 #define AFIO_EXTICR1_EXTI0_PD_Pos (0U)
2169 #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */
2170 #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */
2171 #define AFIO_EXTICR1_EXTI0_PE_Pos (2U)
2172 #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */
2173 #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */
2174 #define AFIO_EXTICR1_EXTI0_PF_Pos (0U)
2175 #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */
2176 #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */
2177 #define AFIO_EXTICR1_EXTI0_PG_Pos (1U)
2178 #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */
2179 #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */
2180 
2181 /*!< EXTI1 configuration */
2182 #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */
2183 #define AFIO_EXTICR1_EXTI1_PB_Pos (4U)
2184 #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */
2185 #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */
2186 #define AFIO_EXTICR1_EXTI1_PC_Pos (5U)
2187 #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */
2188 #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */
2189 #define AFIO_EXTICR1_EXTI1_PD_Pos (4U)
2190 #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */
2191 #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */
2192 #define AFIO_EXTICR1_EXTI1_PE_Pos (6U)
2193 #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */
2194 #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */
2195 #define AFIO_EXTICR1_EXTI1_PF_Pos (4U)
2196 #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */
2197 #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */
2198 #define AFIO_EXTICR1_EXTI1_PG_Pos (5U)
2199 #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */
2200 #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */
2201 
2202 /*!< EXTI2 configuration */
2203 #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */
2204 #define AFIO_EXTICR1_EXTI2_PB_Pos (8U)
2205 #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */
2206 #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */
2207 #define AFIO_EXTICR1_EXTI2_PC_Pos (9U)
2208 #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */
2209 #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */
2210 #define AFIO_EXTICR1_EXTI2_PD_Pos (8U)
2211 #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */
2212 #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */
2213 #define AFIO_EXTICR1_EXTI2_PE_Pos (10U)
2214 #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */
2215 #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */
2216 #define AFIO_EXTICR1_EXTI2_PF_Pos (8U)
2217 #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */
2218 #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */
2219 #define AFIO_EXTICR1_EXTI2_PG_Pos (9U)
2220 #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */
2221 #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */
2222 
2223 /*!< EXTI3 configuration */
2224 #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */
2225 #define AFIO_EXTICR1_EXTI3_PB_Pos (12U)
2226 #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */
2227 #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */
2228 #define AFIO_EXTICR1_EXTI3_PC_Pos (13U)
2229 #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */
2230 #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */
2231 #define AFIO_EXTICR1_EXTI3_PD_Pos (12U)
2232 #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */
2233 #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */
2234 #define AFIO_EXTICR1_EXTI3_PE_Pos (14U)
2235 #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */
2236 #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */
2237 #define AFIO_EXTICR1_EXTI3_PF_Pos (12U)
2238 #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */
2239 #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */
2240 #define AFIO_EXTICR1_EXTI3_PG_Pos (13U)
2241 #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */
2242 #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */
2243 
2244 /***************** Bit definition for AFIO_EXTICR2 register *****************/
2245 #define AFIO_EXTICR2_EXTI4_Pos (0U)
2246 #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
2247 #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
2248 #define AFIO_EXTICR2_EXTI5_Pos (4U)
2249 #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
2250 #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
2251 #define AFIO_EXTICR2_EXTI6_Pos (8U)
2252 #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
2253 #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
2254 #define AFIO_EXTICR2_EXTI7_Pos (12U)
2255 #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
2256 #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
2257 
2258 /*!< EXTI4 configuration */
2259 #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */
2260 #define AFIO_EXTICR2_EXTI4_PB_Pos (0U)
2261 #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */
2262 #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */
2263 #define AFIO_EXTICR2_EXTI4_PC_Pos (1U)
2264 #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */
2265 #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */
2266 #define AFIO_EXTICR2_EXTI4_PD_Pos (0U)
2267 #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */
2268 #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */
2269 #define AFIO_EXTICR2_EXTI4_PE_Pos (2U)
2270 #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */
2271 #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */
2272 #define AFIO_EXTICR2_EXTI4_PF_Pos (0U)
2273 #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */
2274 #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */
2275 #define AFIO_EXTICR2_EXTI4_PG_Pos (1U)
2276 #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */
2277 #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */
2278 
2279 /* EXTI5 configuration */
2280 #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */
2281 #define AFIO_EXTICR2_EXTI5_PB_Pos (4U)
2282 #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */
2283 #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */
2284 #define AFIO_EXTICR2_EXTI5_PC_Pos (5U)
2285 #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */
2286 #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */
2287 #define AFIO_EXTICR2_EXTI5_PD_Pos (4U)
2288 #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */
2289 #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */
2290 #define AFIO_EXTICR2_EXTI5_PE_Pos (6U)
2291 #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */
2292 #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */
2293 #define AFIO_EXTICR2_EXTI5_PF_Pos (4U)
2294 #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */
2295 #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */
2296 #define AFIO_EXTICR2_EXTI5_PG_Pos (5U)
2297 #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */
2298 #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */
2299 
2300 /*!< EXTI6 configuration */
2301 #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */
2302 #define AFIO_EXTICR2_EXTI6_PB_Pos (8U)
2303 #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */
2304 #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */
2305 #define AFIO_EXTICR2_EXTI6_PC_Pos (9U)
2306 #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */
2307 #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */
2308 #define AFIO_EXTICR2_EXTI6_PD_Pos (8U)
2309 #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */
2310 #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */
2311 #define AFIO_EXTICR2_EXTI6_PE_Pos (10U)
2312 #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */
2313 #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */
2314 #define AFIO_EXTICR2_EXTI6_PF_Pos (8U)
2315 #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */
2316 #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */
2317 #define AFIO_EXTICR2_EXTI6_PG_Pos (9U)
2318 #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */
2319 #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */
2320 
2321 /*!< EXTI7 configuration */
2322 #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */
2323 #define AFIO_EXTICR2_EXTI7_PB_Pos (12U)
2324 #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */
2325 #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */
2326 #define AFIO_EXTICR2_EXTI7_PC_Pos (13U)
2327 #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */
2328 #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */
2329 #define AFIO_EXTICR2_EXTI7_PD_Pos (12U)
2330 #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */
2331 #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */
2332 #define AFIO_EXTICR2_EXTI7_PE_Pos (14U)
2333 #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */
2334 #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */
2335 #define AFIO_EXTICR2_EXTI7_PF_Pos (12U)
2336 #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */
2337 #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */
2338 #define AFIO_EXTICR2_EXTI7_PG_Pos (13U)
2339 #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */
2340 #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */
2341 
2342 /***************** Bit definition for AFIO_EXTICR3 register *****************/
2343 #define AFIO_EXTICR3_EXTI8_Pos (0U)
2344 #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
2345 #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
2346 #define AFIO_EXTICR3_EXTI9_Pos (4U)
2347 #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
2348 #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
2349 #define AFIO_EXTICR3_EXTI10_Pos (8U)
2350 #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
2351 #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
2352 #define AFIO_EXTICR3_EXTI11_Pos (12U)
2353 #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
2354 #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
2355 
2356 /*!< EXTI8 configuration */
2357 #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */
2358 #define AFIO_EXTICR3_EXTI8_PB_Pos (0U)
2359 #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */
2360 #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */
2361 #define AFIO_EXTICR3_EXTI8_PC_Pos (1U)
2362 #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */
2363 #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */
2364 #define AFIO_EXTICR3_EXTI8_PD_Pos (0U)
2365 #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */
2366 #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */
2367 #define AFIO_EXTICR3_EXTI8_PE_Pos (2U)
2368 #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */
2369 #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */
2370 #define AFIO_EXTICR3_EXTI8_PF_Pos (0U)
2371 #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */
2372 #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */
2373 #define AFIO_EXTICR3_EXTI8_PG_Pos (1U)
2374 #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */
2375 #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */
2376 
2377 /*!< EXTI9 configuration */
2378 #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */
2379 #define AFIO_EXTICR3_EXTI9_PB_Pos (4U)
2380 #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */
2381 #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */
2382 #define AFIO_EXTICR3_EXTI9_PC_Pos (5U)
2383 #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */
2384 #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */
2385 #define AFIO_EXTICR3_EXTI9_PD_Pos (4U)
2386 #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */
2387 #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */
2388 #define AFIO_EXTICR3_EXTI9_PE_Pos (6U)
2389 #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */
2390 #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */
2391 #define AFIO_EXTICR3_EXTI9_PF_Pos (4U)
2392 #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */
2393 #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */
2394 #define AFIO_EXTICR3_EXTI9_PG_Pos (5U)
2395 #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */
2396 #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */
2397 
2398 /*!< EXTI10 configuration */
2399 #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */
2400 #define AFIO_EXTICR3_EXTI10_PB_Pos (8U)
2401 #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */
2402 #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */
2403 #define AFIO_EXTICR3_EXTI10_PC_Pos (9U)
2404 #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */
2405 #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */
2406 #define AFIO_EXTICR3_EXTI10_PD_Pos (8U)
2407 #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */
2408 #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */
2409 #define AFIO_EXTICR3_EXTI10_PE_Pos (10U)
2410 #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */
2411 #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */
2412 #define AFIO_EXTICR3_EXTI10_PF_Pos (8U)
2413 #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */
2414 #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */
2415 #define AFIO_EXTICR3_EXTI10_PG_Pos (9U)
2416 #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */
2417 #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */
2418 
2419 /*!< EXTI11 configuration */
2420 #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */
2421 #define AFIO_EXTICR3_EXTI11_PB_Pos (12U)
2422 #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */
2423 #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */
2424 #define AFIO_EXTICR3_EXTI11_PC_Pos (13U)
2425 #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */
2426 #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */
2427 #define AFIO_EXTICR3_EXTI11_PD_Pos (12U)
2428 #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */
2429 #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */
2430 #define AFIO_EXTICR3_EXTI11_PE_Pos (14U)
2431 #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */
2432 #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */
2433 #define AFIO_EXTICR3_EXTI11_PF_Pos (12U)
2434 #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */
2435 #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */
2436 #define AFIO_EXTICR3_EXTI11_PG_Pos (13U)
2437 #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */
2438 #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */
2439 
2440 /***************** Bit definition for AFIO_EXTICR4 register *****************/
2441 #define AFIO_EXTICR4_EXTI12_Pos (0U)
2442 #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
2443 #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
2444 #define AFIO_EXTICR4_EXTI13_Pos (4U)
2445 #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
2446 #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
2447 #define AFIO_EXTICR4_EXTI14_Pos (8U)
2448 #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
2449 #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
2450 #define AFIO_EXTICR4_EXTI15_Pos (12U)
2451 #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
2452 #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
2453 
2454 /* EXTI12 configuration */
2455 #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */
2456 #define AFIO_EXTICR4_EXTI12_PB_Pos (0U)
2457 #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */
2458 #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */
2459 #define AFIO_EXTICR4_EXTI12_PC_Pos (1U)
2460 #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */
2461 #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */
2462 #define AFIO_EXTICR4_EXTI12_PD_Pos (0U)
2463 #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */
2464 #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */
2465 #define AFIO_EXTICR4_EXTI12_PE_Pos (2U)
2466 #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */
2467 #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */
2468 #define AFIO_EXTICR4_EXTI12_PF_Pos (0U)
2469 #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */
2470 #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */
2471 #define AFIO_EXTICR4_EXTI12_PG_Pos (1U)
2472 #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */
2473 #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */
2474 
2475 /* EXTI13 configuration */
2476 #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */
2477 #define AFIO_EXTICR4_EXTI13_PB_Pos (4U)
2478 #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */
2479 #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */
2480 #define AFIO_EXTICR4_EXTI13_PC_Pos (5U)
2481 #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */
2482 #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */
2483 #define AFIO_EXTICR4_EXTI13_PD_Pos (4U)
2484 #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */
2485 #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */
2486 #define AFIO_EXTICR4_EXTI13_PE_Pos (6U)
2487 #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */
2488 #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */
2489 #define AFIO_EXTICR4_EXTI13_PF_Pos (4U)
2490 #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */
2491 #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */
2492 #define AFIO_EXTICR4_EXTI13_PG_Pos (5U)
2493 #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */
2494 #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */
2495 
2496 /*!< EXTI14 configuration */
2497 #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */
2498 #define AFIO_EXTICR4_EXTI14_PB_Pos (8U)
2499 #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */
2500 #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */
2501 #define AFIO_EXTICR4_EXTI14_PC_Pos (9U)
2502 #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */
2503 #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */
2504 #define AFIO_EXTICR4_EXTI14_PD_Pos (8U)
2505 #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */
2506 #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */
2507 #define AFIO_EXTICR4_EXTI14_PE_Pos (10U)
2508 #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */
2509 #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */
2510 #define AFIO_EXTICR4_EXTI14_PF_Pos (8U)
2511 #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */
2512 #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */
2513 #define AFIO_EXTICR4_EXTI14_PG_Pos (9U)
2514 #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */
2515 #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */
2516 
2517 /*!< EXTI15 configuration */
2518 #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */
2519 #define AFIO_EXTICR4_EXTI15_PB_Pos (12U)
2520 #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */
2521 #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */
2522 #define AFIO_EXTICR4_EXTI15_PC_Pos (13U)
2523 #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */
2524 #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */
2525 #define AFIO_EXTICR4_EXTI15_PD_Pos (12U)
2526 #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */
2527 #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */
2528 #define AFIO_EXTICR4_EXTI15_PE_Pos (14U)
2529 #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */
2530 #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */
2531 #define AFIO_EXTICR4_EXTI15_PF_Pos (12U)
2532 #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */
2533 #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */
2534 #define AFIO_EXTICR4_EXTI15_PG_Pos (13U)
2535 #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */
2536 #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */
2537 
2538 /****************** Bit definition for AFIO_MAPR2 register ******************/
2539 
2540 
2541 
2542 /******************************************************************************/
2543 /* */
2544 /* External Interrupt/Event Controller */
2545 /* */
2546 /******************************************************************************/
2547 
2548 /******************* Bit definition for EXTI_IMR register *******************/
2549 #define EXTI_IMR_MR0_Pos (0U)
2550 #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
2551 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
2552 #define EXTI_IMR_MR1_Pos (1U)
2553 #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
2554 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
2555 #define EXTI_IMR_MR2_Pos (2U)
2556 #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
2557 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
2558 #define EXTI_IMR_MR3_Pos (3U)
2559 #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
2560 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
2561 #define EXTI_IMR_MR4_Pos (4U)
2562 #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
2563 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
2564 #define EXTI_IMR_MR5_Pos (5U)
2565 #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
2566 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
2567 #define EXTI_IMR_MR6_Pos (6U)
2568 #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
2569 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
2570 #define EXTI_IMR_MR7_Pos (7U)
2571 #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
2572 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
2573 #define EXTI_IMR_MR8_Pos (8U)
2574 #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
2575 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
2576 #define EXTI_IMR_MR9_Pos (9U)
2577 #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
2578 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
2579 #define EXTI_IMR_MR10_Pos (10U)
2580 #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
2581 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
2582 #define EXTI_IMR_MR11_Pos (11U)
2583 #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
2584 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
2585 #define EXTI_IMR_MR12_Pos (12U)
2586 #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
2587 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
2588 #define EXTI_IMR_MR13_Pos (13U)
2589 #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
2590 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
2591 #define EXTI_IMR_MR14_Pos (14U)
2592 #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
2593 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
2594 #define EXTI_IMR_MR15_Pos (15U)
2595 #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
2596 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
2597 #define EXTI_IMR_MR16_Pos (16U)
2598 #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
2599 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
2600 #define EXTI_IMR_MR17_Pos (17U)
2601 #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
2602 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
2603 #define EXTI_IMR_MR18_Pos (18U)
2604 #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
2605 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
2606 
2607 /* References Defines */
2608 #define EXTI_IMR_IM0 EXTI_IMR_MR0
2609 #define EXTI_IMR_IM1 EXTI_IMR_MR1
2610 #define EXTI_IMR_IM2 EXTI_IMR_MR2
2611 #define EXTI_IMR_IM3 EXTI_IMR_MR3
2612 #define EXTI_IMR_IM4 EXTI_IMR_MR4
2613 #define EXTI_IMR_IM5 EXTI_IMR_MR5
2614 #define EXTI_IMR_IM6 EXTI_IMR_MR6
2615 #define EXTI_IMR_IM7 EXTI_IMR_MR7
2616 #define EXTI_IMR_IM8 EXTI_IMR_MR8
2617 #define EXTI_IMR_IM9 EXTI_IMR_MR9
2618 #define EXTI_IMR_IM10 EXTI_IMR_MR10
2619 #define EXTI_IMR_IM11 EXTI_IMR_MR11
2620 #define EXTI_IMR_IM12 EXTI_IMR_MR12
2621 #define EXTI_IMR_IM13 EXTI_IMR_MR13
2622 #define EXTI_IMR_IM14 EXTI_IMR_MR14
2623 #define EXTI_IMR_IM15 EXTI_IMR_MR15
2624 #define EXTI_IMR_IM16 EXTI_IMR_MR16
2625 #define EXTI_IMR_IM17 EXTI_IMR_MR17
2626 #define EXTI_IMR_IM18 EXTI_IMR_MR18
2627 #define EXTI_IMR_IM 0x0007FFFFU /*!< Interrupt Mask All */
2628 
2629 /******************* Bit definition for EXTI_EMR register *******************/
2630 #define EXTI_EMR_MR0_Pos (0U)
2631 #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
2632 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
2633 #define EXTI_EMR_MR1_Pos (1U)
2634 #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
2635 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
2636 #define EXTI_EMR_MR2_Pos (2U)
2637 #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
2638 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
2639 #define EXTI_EMR_MR3_Pos (3U)
2640 #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
2641 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
2642 #define EXTI_EMR_MR4_Pos (4U)
2643 #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
2644 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
2645 #define EXTI_EMR_MR5_Pos (5U)
2646 #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
2647 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
2648 #define EXTI_EMR_MR6_Pos (6U)
2649 #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
2650 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
2651 #define EXTI_EMR_MR7_Pos (7U)
2652 #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
2653 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
2654 #define EXTI_EMR_MR8_Pos (8U)
2655 #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
2656 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
2657 #define EXTI_EMR_MR9_Pos (9U)
2658 #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
2659 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
2660 #define EXTI_EMR_MR10_Pos (10U)
2661 #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
2662 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
2663 #define EXTI_EMR_MR11_Pos (11U)
2664 #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
2665 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
2666 #define EXTI_EMR_MR12_Pos (12U)
2667 #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
2668 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
2669 #define EXTI_EMR_MR13_Pos (13U)
2670 #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
2671 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
2672 #define EXTI_EMR_MR14_Pos (14U)
2673 #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
2674 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
2675 #define EXTI_EMR_MR15_Pos (15U)
2676 #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
2677 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
2678 #define EXTI_EMR_MR16_Pos (16U)
2679 #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
2680 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
2681 #define EXTI_EMR_MR17_Pos (17U)
2682 #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
2683 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
2684 #define EXTI_EMR_MR18_Pos (18U)
2685 #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
2686 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
2687 
2688 /* References Defines */
2689 #define EXTI_EMR_EM0 EXTI_EMR_MR0
2690 #define EXTI_EMR_EM1 EXTI_EMR_MR1
2691 #define EXTI_EMR_EM2 EXTI_EMR_MR2
2692 #define EXTI_EMR_EM3 EXTI_EMR_MR3
2693 #define EXTI_EMR_EM4 EXTI_EMR_MR4
2694 #define EXTI_EMR_EM5 EXTI_EMR_MR5
2695 #define EXTI_EMR_EM6 EXTI_EMR_MR6
2696 #define EXTI_EMR_EM7 EXTI_EMR_MR7
2697 #define EXTI_EMR_EM8 EXTI_EMR_MR8
2698 #define EXTI_EMR_EM9 EXTI_EMR_MR9
2699 #define EXTI_EMR_EM10 EXTI_EMR_MR10
2700 #define EXTI_EMR_EM11 EXTI_EMR_MR11
2701 #define EXTI_EMR_EM12 EXTI_EMR_MR12
2702 #define EXTI_EMR_EM13 EXTI_EMR_MR13
2703 #define EXTI_EMR_EM14 EXTI_EMR_MR14
2704 #define EXTI_EMR_EM15 EXTI_EMR_MR15
2705 #define EXTI_EMR_EM16 EXTI_EMR_MR16
2706 #define EXTI_EMR_EM17 EXTI_EMR_MR17
2707 #define EXTI_EMR_EM18 EXTI_EMR_MR18
2708 
2709 /****************** Bit definition for EXTI_RTSR register *******************/
2710 #define EXTI_RTSR_TR0_Pos (0U)
2711 #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
2712 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
2713 #define EXTI_RTSR_TR1_Pos (1U)
2714 #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
2715 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
2716 #define EXTI_RTSR_TR2_Pos (2U)
2717 #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
2718 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
2719 #define EXTI_RTSR_TR3_Pos (3U)
2720 #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
2721 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
2722 #define EXTI_RTSR_TR4_Pos (4U)
2723 #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
2724 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
2725 #define EXTI_RTSR_TR5_Pos (5U)
2726 #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
2727 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
2728 #define EXTI_RTSR_TR6_Pos (6U)
2729 #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
2730 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
2731 #define EXTI_RTSR_TR7_Pos (7U)
2732 #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
2733 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
2734 #define EXTI_RTSR_TR8_Pos (8U)
2735 #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
2736 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
2737 #define EXTI_RTSR_TR9_Pos (9U)
2738 #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
2739 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
2740 #define EXTI_RTSR_TR10_Pos (10U)
2741 #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
2742 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
2743 #define EXTI_RTSR_TR11_Pos (11U)
2744 #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
2745 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
2746 #define EXTI_RTSR_TR12_Pos (12U)
2747 #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
2748 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
2749 #define EXTI_RTSR_TR13_Pos (13U)
2750 #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
2751 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
2752 #define EXTI_RTSR_TR14_Pos (14U)
2753 #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
2754 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
2755 #define EXTI_RTSR_TR15_Pos (15U)
2756 #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
2757 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
2758 #define EXTI_RTSR_TR16_Pos (16U)
2759 #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
2760 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
2761 #define EXTI_RTSR_TR17_Pos (17U)
2762 #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
2763 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
2764 #define EXTI_RTSR_TR18_Pos (18U)
2765 #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */
2766 #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
2767 
2768 /* References Defines */
2769 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
2770 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
2771 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
2772 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
2773 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
2774 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
2775 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
2776 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
2777 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
2778 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
2779 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
2780 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
2781 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
2782 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
2783 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
2784 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
2785 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
2786 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
2787 #define EXTI_RTSR_RT18 EXTI_RTSR_TR18
2788 
2789 /****************** Bit definition for EXTI_FTSR register *******************/
2790 #define EXTI_FTSR_TR0_Pos (0U)
2791 #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
2792 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
2793 #define EXTI_FTSR_TR1_Pos (1U)
2794 #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
2795 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
2796 #define EXTI_FTSR_TR2_Pos (2U)
2797 #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
2798 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
2799 #define EXTI_FTSR_TR3_Pos (3U)
2800 #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
2801 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
2802 #define EXTI_FTSR_TR4_Pos (4U)
2803 #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
2804 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
2805 #define EXTI_FTSR_TR5_Pos (5U)
2806 #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
2807 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
2808 #define EXTI_FTSR_TR6_Pos (6U)
2809 #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
2810 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
2811 #define EXTI_FTSR_TR7_Pos (7U)
2812 #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
2813 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
2814 #define EXTI_FTSR_TR8_Pos (8U)
2815 #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
2816 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
2817 #define EXTI_FTSR_TR9_Pos (9U)
2818 #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
2819 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
2820 #define EXTI_FTSR_TR10_Pos (10U)
2821 #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
2822 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
2823 #define EXTI_FTSR_TR11_Pos (11U)
2824 #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
2825 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
2826 #define EXTI_FTSR_TR12_Pos (12U)
2827 #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
2828 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
2829 #define EXTI_FTSR_TR13_Pos (13U)
2830 #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
2831 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
2832 #define EXTI_FTSR_TR14_Pos (14U)
2833 #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
2834 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
2835 #define EXTI_FTSR_TR15_Pos (15U)
2836 #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
2837 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
2838 #define EXTI_FTSR_TR16_Pos (16U)
2839 #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
2840 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
2841 #define EXTI_FTSR_TR17_Pos (17U)
2842 #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
2843 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
2844 #define EXTI_FTSR_TR18_Pos (18U)
2845 #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */
2846 #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
2847 
2848 /* References Defines */
2849 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
2850 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
2851 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
2852 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
2853 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
2854 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
2855 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
2856 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
2857 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
2858 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
2859 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
2860 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
2861 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
2862 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
2863 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
2864 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
2865 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
2866 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
2867 #define EXTI_FTSR_FT18 EXTI_FTSR_TR18
2868 
2869 /****************** Bit definition for EXTI_SWIER register ******************/
2870 #define EXTI_SWIER_SWIER0_Pos (0U)
2871 #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
2872 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
2873 #define EXTI_SWIER_SWIER1_Pos (1U)
2874 #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
2875 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
2876 #define EXTI_SWIER_SWIER2_Pos (2U)
2877 #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
2878 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
2879 #define EXTI_SWIER_SWIER3_Pos (3U)
2880 #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
2881 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
2882 #define EXTI_SWIER_SWIER4_Pos (4U)
2883 #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
2884 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
2885 #define EXTI_SWIER_SWIER5_Pos (5U)
2886 #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
2887 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
2888 #define EXTI_SWIER_SWIER6_Pos (6U)
2889 #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
2890 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
2891 #define EXTI_SWIER_SWIER7_Pos (7U)
2892 #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
2893 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
2894 #define EXTI_SWIER_SWIER8_Pos (8U)
2895 #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
2896 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
2897 #define EXTI_SWIER_SWIER9_Pos (9U)
2898 #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
2899 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
2900 #define EXTI_SWIER_SWIER10_Pos (10U)
2901 #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
2902 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
2903 #define EXTI_SWIER_SWIER11_Pos (11U)
2904 #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
2905 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
2906 #define EXTI_SWIER_SWIER12_Pos (12U)
2907 #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
2908 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
2909 #define EXTI_SWIER_SWIER13_Pos (13U)
2910 #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
2911 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
2912 #define EXTI_SWIER_SWIER14_Pos (14U)
2913 #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
2914 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
2915 #define EXTI_SWIER_SWIER15_Pos (15U)
2916 #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
2917 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
2918 #define EXTI_SWIER_SWIER16_Pos (16U)
2919 #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
2920 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
2921 #define EXTI_SWIER_SWIER17_Pos (17U)
2922 #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
2923 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
2924 #define EXTI_SWIER_SWIER18_Pos (18U)
2925 #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */
2926 #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */
2927 
2928 /* References Defines */
2929 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2930 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2931 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2932 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2933 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2934 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2935 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2936 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2937 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2938 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2939 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2940 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2941 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2942 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2943 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2944 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2945 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2946 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2947 #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
2948 
2949 /******************* Bit definition for EXTI_PR register ********************/
2950 #define EXTI_PR_PR0_Pos (0U)
2951 #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
2952 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */
2953 #define EXTI_PR_PR1_Pos (1U)
2954 #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
2955 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */
2956 #define EXTI_PR_PR2_Pos (2U)
2957 #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
2958 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */
2959 #define EXTI_PR_PR3_Pos (3U)
2960 #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
2961 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */
2962 #define EXTI_PR_PR4_Pos (4U)
2963 #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
2964 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */
2965 #define EXTI_PR_PR5_Pos (5U)
2966 #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
2967 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */
2968 #define EXTI_PR_PR6_Pos (6U)
2969 #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
2970 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */
2971 #define EXTI_PR_PR7_Pos (7U)
2972 #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
2973 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */
2974 #define EXTI_PR_PR8_Pos (8U)
2975 #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
2976 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */
2977 #define EXTI_PR_PR9_Pos (9U)
2978 #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
2979 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */
2980 #define EXTI_PR_PR10_Pos (10U)
2981 #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
2982 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */
2983 #define EXTI_PR_PR11_Pos (11U)
2984 #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
2985 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */
2986 #define EXTI_PR_PR12_Pos (12U)
2987 #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
2988 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */
2989 #define EXTI_PR_PR13_Pos (13U)
2990 #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
2991 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */
2992 #define EXTI_PR_PR14_Pos (14U)
2993 #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
2994 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */
2995 #define EXTI_PR_PR15_Pos (15U)
2996 #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
2997 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */
2998 #define EXTI_PR_PR16_Pos (16U)
2999 #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
3000 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */
3001 #define EXTI_PR_PR17_Pos (17U)
3002 #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
3003 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */
3004 #define EXTI_PR_PR18_Pos (18U)
3005 #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */
3006 #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */
3007 
3008 /* References Defines */
3009 #define EXTI_PR_PIF0 EXTI_PR_PR0
3010 #define EXTI_PR_PIF1 EXTI_PR_PR1
3011 #define EXTI_PR_PIF2 EXTI_PR_PR2
3012 #define EXTI_PR_PIF3 EXTI_PR_PR3
3013 #define EXTI_PR_PIF4 EXTI_PR_PR4
3014 #define EXTI_PR_PIF5 EXTI_PR_PR5
3015 #define EXTI_PR_PIF6 EXTI_PR_PR6
3016 #define EXTI_PR_PIF7 EXTI_PR_PR7
3017 #define EXTI_PR_PIF8 EXTI_PR_PR8
3018 #define EXTI_PR_PIF9 EXTI_PR_PR9
3019 #define EXTI_PR_PIF10 EXTI_PR_PR10
3020 #define EXTI_PR_PIF11 EXTI_PR_PR11
3021 #define EXTI_PR_PIF12 EXTI_PR_PR12
3022 #define EXTI_PR_PIF13 EXTI_PR_PR13
3023 #define EXTI_PR_PIF14 EXTI_PR_PR14
3024 #define EXTI_PR_PIF15 EXTI_PR_PR15
3025 #define EXTI_PR_PIF16 EXTI_PR_PR16
3026 #define EXTI_PR_PIF17 EXTI_PR_PR17
3027 #define EXTI_PR_PIF18 EXTI_PR_PR18
3028 
3029 /******************************************************************************/
3030 /* */
3031 /* DMA Controller */
3032 /* */
3033 /******************************************************************************/
3034 
3035 /******************* Bit definition for DMA_ISR register ********************/
3036 #define DMA_ISR_GIF1_Pos (0U)
3037 #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
3038 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
3039 #define DMA_ISR_TCIF1_Pos (1U)
3040 #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
3041 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
3042 #define DMA_ISR_HTIF1_Pos (2U)
3043 #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
3044 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
3045 #define DMA_ISR_TEIF1_Pos (3U)
3046 #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
3047 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
3048 #define DMA_ISR_GIF2_Pos (4U)
3049 #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
3050 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
3051 #define DMA_ISR_TCIF2_Pos (5U)
3052 #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
3053 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
3054 #define DMA_ISR_HTIF2_Pos (6U)
3055 #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
3056 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
3057 #define DMA_ISR_TEIF2_Pos (7U)
3058 #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
3059 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
3060 #define DMA_ISR_GIF3_Pos (8U)
3061 #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
3062 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
3063 #define DMA_ISR_TCIF3_Pos (9U)
3064 #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
3065 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
3066 #define DMA_ISR_HTIF3_Pos (10U)
3067 #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
3068 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
3069 #define DMA_ISR_TEIF3_Pos (11U)
3070 #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
3071 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
3072 #define DMA_ISR_GIF4_Pos (12U)
3073 #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
3074 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
3075 #define DMA_ISR_TCIF4_Pos (13U)
3076 #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
3077 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
3078 #define DMA_ISR_HTIF4_Pos (14U)
3079 #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
3080 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
3081 #define DMA_ISR_TEIF4_Pos (15U)
3082 #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
3083 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
3084 #define DMA_ISR_GIF5_Pos (16U)
3085 #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
3086 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
3087 #define DMA_ISR_TCIF5_Pos (17U)
3088 #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
3089 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
3090 #define DMA_ISR_HTIF5_Pos (18U)
3091 #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
3092 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
3093 #define DMA_ISR_TEIF5_Pos (19U)
3094 #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
3095 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
3096 #define DMA_ISR_GIF6_Pos (20U)
3097 #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */
3098 #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
3099 #define DMA_ISR_TCIF6_Pos (21U)
3100 #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */
3101 #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
3102 #define DMA_ISR_HTIF6_Pos (22U)
3103 #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */
3104 #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
3105 #define DMA_ISR_TEIF6_Pos (23U)
3106 #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */
3107 #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
3108 #define DMA_ISR_GIF7_Pos (24U)
3109 #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */
3110 #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
3111 #define DMA_ISR_TCIF7_Pos (25U)
3112 #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */
3113 #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
3114 #define DMA_ISR_HTIF7_Pos (26U)
3115 #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */
3116 #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
3117 #define DMA_ISR_TEIF7_Pos (27U)
3118 #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */
3119 #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
3120 
3121 /******************* Bit definition for DMA_IFCR register *******************/
3122 #define DMA_IFCR_CGIF1_Pos (0U)
3123 #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
3124 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
3125 #define DMA_IFCR_CTCIF1_Pos (1U)
3126 #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
3127 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
3128 #define DMA_IFCR_CHTIF1_Pos (2U)
3129 #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
3130 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
3131 #define DMA_IFCR_CTEIF1_Pos (3U)
3132 #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
3133 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
3134 #define DMA_IFCR_CGIF2_Pos (4U)
3135 #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
3136 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
3137 #define DMA_IFCR_CTCIF2_Pos (5U)
3138 #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
3139 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
3140 #define DMA_IFCR_CHTIF2_Pos (6U)
3141 #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
3142 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
3143 #define DMA_IFCR_CTEIF2_Pos (7U)
3144 #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
3145 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
3146 #define DMA_IFCR_CGIF3_Pos (8U)
3147 #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
3148 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
3149 #define DMA_IFCR_CTCIF3_Pos (9U)
3150 #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
3151 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
3152 #define DMA_IFCR_CHTIF3_Pos (10U)
3153 #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
3154 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
3155 #define DMA_IFCR_CTEIF3_Pos (11U)
3156 #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
3157 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
3158 #define DMA_IFCR_CGIF4_Pos (12U)
3159 #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
3160 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
3161 #define DMA_IFCR_CTCIF4_Pos (13U)
3162 #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
3163 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
3164 #define DMA_IFCR_CHTIF4_Pos (14U)
3165 #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
3166 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
3167 #define DMA_IFCR_CTEIF4_Pos (15U)
3168 #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
3169 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
3170 #define DMA_IFCR_CGIF5_Pos (16U)
3171 #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
3172 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
3173 #define DMA_IFCR_CTCIF5_Pos (17U)
3174 #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
3175 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
3176 #define DMA_IFCR_CHTIF5_Pos (18U)
3177 #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
3178 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
3179 #define DMA_IFCR_CTEIF5_Pos (19U)
3180 #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
3181 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
3182 #define DMA_IFCR_CGIF6_Pos (20U)
3183 #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */
3184 #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
3185 #define DMA_IFCR_CTCIF6_Pos (21U)
3186 #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */
3187 #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
3188 #define DMA_IFCR_CHTIF6_Pos (22U)
3189 #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */
3190 #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
3191 #define DMA_IFCR_CTEIF6_Pos (23U)
3192 #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */
3193 #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
3194 #define DMA_IFCR_CGIF7_Pos (24U)
3195 #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */
3196 #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
3197 #define DMA_IFCR_CTCIF7_Pos (25U)
3198 #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */
3199 #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
3200 #define DMA_IFCR_CHTIF7_Pos (26U)
3201 #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */
3202 #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
3203 #define DMA_IFCR_CTEIF7_Pos (27U)
3204 #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */
3205 #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
3206 
3207 /******************* Bit definition for DMA_CCR register *******************/
3208 #define DMA_CCR_EN_Pos (0U)
3209 #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */
3210 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
3211 #define DMA_CCR_TCIE_Pos (1U)
3212 #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
3213 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
3214 #define DMA_CCR_HTIE_Pos (2U)
3215 #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
3216 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
3217 #define DMA_CCR_TEIE_Pos (3U)
3218 #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
3219 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
3220 #define DMA_CCR_DIR_Pos (4U)
3221 #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
3222 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
3223 #define DMA_CCR_CIRC_Pos (5U)
3224 #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
3225 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
3226 #define DMA_CCR_PINC_Pos (6U)
3227 #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
3228 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
3229 #define DMA_CCR_MINC_Pos (7U)
3230 #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
3231 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
3232 
3233 #define DMA_CCR_PSIZE_Pos (8U)
3234 #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
3235 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
3236 #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
3237 #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
3238 
3239 #define DMA_CCR_MSIZE_Pos (10U)
3240 #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
3241 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
3242 #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
3243 #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
3244 
3245 #define DMA_CCR_PL_Pos (12U)
3246 #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */
3247 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */
3248 #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */
3249 #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */
3250 
3251 #define DMA_CCR_MEM2MEM_Pos (14U)
3252 #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
3253 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
3254 
3255 /****************** Bit definition for DMA_CNDTR register ******************/
3256 #define DMA_CNDTR_NDT_Pos (0U)
3257 #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
3258 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
3259 
3260 /****************** Bit definition for DMA_CPAR register *******************/
3261 #define DMA_CPAR_PA_Pos (0U)
3262 #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
3263 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
3264 
3265 /****************** Bit definition for DMA_CMAR register *******************/
3266 #define DMA_CMAR_MA_Pos (0U)
3267 #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
3268 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
3269 
3270 /******************************************************************************/
3271 /* */
3272 /* Analog to Digital Converter (ADC) */
3273 /* */
3274 /******************************************************************************/
3275 
3276 /*
3277  * @brief Specific device feature definitions (not present on all devices in the STM32F1 family)
3278  */
3279 #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */
3280 
3281 /******************** Bit definition for ADC_SR register ********************/
3282 #define ADC_SR_AWD_Pos (0U)
3283 #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */
3284 #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */
3285 #define ADC_SR_EOS_Pos (1U)
3286 #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */
3287 #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
3288 #define ADC_SR_JEOS_Pos (2U)
3289 #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */
3290 #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
3291 #define ADC_SR_JSTRT_Pos (3U)
3292 #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */
3293 #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */
3294 #define ADC_SR_STRT_Pos (4U)
3295 #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */
3296 #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */
3297 
3298 /* Legacy defines */
3299 #define ADC_SR_EOC (ADC_SR_EOS)
3300 #define ADC_SR_JEOC (ADC_SR_JEOS)
3301 
3302 /******************* Bit definition for ADC_CR1 register ********************/
3303 #define ADC_CR1_AWDCH_Pos (0U)
3304 #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */
3305 #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
3306 #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */
3307 #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */
3308 #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */
3309 #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */
3310 #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */
3311 
3312 #define ADC_CR1_EOSIE_Pos (5U)
3313 #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */
3314 #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
3315 #define ADC_CR1_AWDIE_Pos (6U)
3316 #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */
3317 #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */
3318 #define ADC_CR1_JEOSIE_Pos (7U)
3319 #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */
3320 #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
3321 #define ADC_CR1_SCAN_Pos (8U)
3322 #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */
3323 #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */
3324 #define ADC_CR1_AWDSGL_Pos (9U)
3325 #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */
3326 #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
3327 #define ADC_CR1_JAUTO_Pos (10U)
3328 #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */
3329 #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
3330 #define ADC_CR1_DISCEN_Pos (11U)
3331 #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */
3332 #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
3333 #define ADC_CR1_JDISCEN_Pos (12U)
3334 #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */
3335 #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
3336 
3337 #define ADC_CR1_DISCNUM_Pos (13U)
3338 #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */
3339 #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
3340 #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */
3341 #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */
3342 #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */
3343 
3344 #define ADC_CR1_DUALMOD_Pos (16U)
3345 #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */
3346 #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */
3347 #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */
3348 #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */
3349 #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */
3350 #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */
3351 
3352 #define ADC_CR1_JAWDEN_Pos (22U)
3353 #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */
3354 #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
3355 #define ADC_CR1_AWDEN_Pos (23U)
3356 #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */
3357 #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
3358 
3359 /* Legacy defines */
3360 #define ADC_CR1_EOCIE (ADC_CR1_EOSIE)
3361 #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)
3362 
3363 /******************* Bit definition for ADC_CR2 register ********************/
3364 #define ADC_CR2_ADON_Pos (0U)
3365 #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */
3366 #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */
3367 #define ADC_CR2_CONT_Pos (1U)
3368 #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */
3369 #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */
3370 #define ADC_CR2_CAL_Pos (2U)
3371 #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */
3372 #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */
3373 #define ADC_CR2_RSTCAL_Pos (3U)
3374 #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */
3375 #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */
3376 #define ADC_CR2_DMA_Pos (8U)
3377 #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */
3378 #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */
3379 #define ADC_CR2_ALIGN_Pos (11U)
3380 #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */
3381 #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */
3382 
3383 #define ADC_CR2_JEXTSEL_Pos (12U)
3384 #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */
3385 #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */
3386 #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */
3387 #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */
3388 #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */
3389 
3390 #define ADC_CR2_JEXTTRIG_Pos (15U)
3391 #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */
3392 #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */
3393 
3394 #define ADC_CR2_EXTSEL_Pos (17U)
3395 #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */
3396 #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */
3397 #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */
3398 #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */
3399 #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */
3400 
3401 #define ADC_CR2_EXTTRIG_Pos (20U)
3402 #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */
3403 #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */
3404 #define ADC_CR2_JSWSTART_Pos (21U)
3405 #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */
3406 #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */
3407 #define ADC_CR2_SWSTART_Pos (22U)
3408 #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */
3409 #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */
3410 #define ADC_CR2_TSVREFE_Pos (23U)
3411 #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */
3412 #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */
3413 
3414 /****************** Bit definition for ADC_SMPR1 register *******************/
3415 #define ADC_SMPR1_SMP10_Pos (0U)
3416 #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */
3417 #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */
3418 #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */
3419 #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */
3420 #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */
3421 
3422 #define ADC_SMPR1_SMP11_Pos (3U)
3423 #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */
3424 #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */
3425 #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */
3426 #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */
3427 #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */
3428 
3429 #define ADC_SMPR1_SMP12_Pos (6U)
3430 #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */
3431 #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */
3432 #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */
3433 #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */
3434 #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */
3435 
3436 #define ADC_SMPR1_SMP13_Pos (9U)
3437 #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */
3438 #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */
3439 #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */
3440 #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */
3441 #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */
3442 
3443 #define ADC_SMPR1_SMP14_Pos (12U)
3444 #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */
3445 #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */
3446 #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */
3447 #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */
3448 #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */
3449 
3450 #define ADC_SMPR1_SMP15_Pos (15U)
3451 #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */
3452 #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */
3453 #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */
3454 #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */
3455 #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */
3456 
3457 #define ADC_SMPR1_SMP16_Pos (18U)
3458 #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */
3459 #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */
3460 #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */
3461 #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */
3462 #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */
3463 
3464 #define ADC_SMPR1_SMP17_Pos (21U)
3465 #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */
3466 #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */
3467 #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */
3468 #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */
3469 #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */
3470 
3471 /****************** Bit definition for ADC_SMPR2 register *******************/
3472 #define ADC_SMPR2_SMP0_Pos (0U)
3473 #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */
3474 #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */
3475 #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */
3476 #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */
3477 #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */
3478 
3479 #define ADC_SMPR2_SMP1_Pos (3U)
3480 #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */
3481 #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */
3482 #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */
3483 #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */
3484 #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */
3485 
3486 #define ADC_SMPR2_SMP2_Pos (6U)
3487 #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */
3488 #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */
3489 #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */
3490 #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */
3491 #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */
3492 
3493 #define ADC_SMPR2_SMP3_Pos (9U)
3494 #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */
3495 #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */
3496 #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */
3497 #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */
3498 #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */
3499 
3500 #define ADC_SMPR2_SMP4_Pos (12U)
3501 #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */
3502 #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */
3503 #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */
3504 #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */
3505 #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */
3506 
3507 #define ADC_SMPR2_SMP5_Pos (15U)
3508 #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */
3509 #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */
3510 #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */
3511 #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */
3512 #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */
3513 
3514 #define ADC_SMPR2_SMP6_Pos (18U)
3515 #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */
3516 #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */
3517 #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */
3518 #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */
3519 #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */
3520 
3521 #define ADC_SMPR2_SMP7_Pos (21U)
3522 #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */
3523 #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */
3524 #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */
3525 #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */
3526 #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */
3527 
3528 #define ADC_SMPR2_SMP8_Pos (24U)
3529 #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */
3530 #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */
3531 #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */
3532 #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */
3533 #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */
3534 
3535 #define ADC_SMPR2_SMP9_Pos (27U)
3536 #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */
3537 #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */
3538 #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */
3539 #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */
3540 #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */
3541 
3542 /****************** Bit definition for ADC_JOFR1 register *******************/
3543 #define ADC_JOFR1_JOFFSET1_Pos (0U)
3544 #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
3545 #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */
3546 
3547 /****************** Bit definition for ADC_JOFR2 register *******************/
3548 #define ADC_JOFR2_JOFFSET2_Pos (0U)
3549 #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
3550 #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */
3551 
3552 /****************** Bit definition for ADC_JOFR3 register *******************/
3553 #define ADC_JOFR3_JOFFSET3_Pos (0U)
3554 #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
3555 #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */
3556 
3557 /****************** Bit definition for ADC_JOFR4 register *******************/
3558 #define ADC_JOFR4_JOFFSET4_Pos (0U)
3559 #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
3560 #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */
3561 
3562 /******************* Bit definition for ADC_HTR register ********************/
3563 #define ADC_HTR_HT_Pos (0U)
3564 #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */
3565 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */
3566 
3567 /******************* Bit definition for ADC_LTR register ********************/
3568 #define ADC_LTR_LT_Pos (0U)
3569 #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */
3570 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */
3571 
3572 /******************* Bit definition for ADC_SQR1 register *******************/
3573 #define ADC_SQR1_SQ13_Pos (0U)
3574 #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */
3575 #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
3576 #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */
3577 #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */
3578 #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */
3579 #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */
3580 #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */
3581 
3582 #define ADC_SQR1_SQ14_Pos (5U)
3583 #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */
3584 #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
3585 #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */
3586 #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */
3587 #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */
3588 #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */
3589 #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */
3590 
3591 #define ADC_SQR1_SQ15_Pos (10U)
3592 #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */
3593 #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
3594 #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */
3595 #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */
3596 #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */
3597 #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */
3598 #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */
3599 
3600 #define ADC_SQR1_SQ16_Pos (15U)
3601 #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */
3602 #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
3603 #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */
3604 #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */
3605 #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */
3606 #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */
3607 #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */
3608 
3609 #define ADC_SQR1_L_Pos (20U)
3610 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */
3611 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
3612 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */
3613 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */
3614 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */
3615 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */
3616 
3617 /******************* Bit definition for ADC_SQR2 register *******************/
3618 #define ADC_SQR2_SQ7_Pos (0U)
3619 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */
3620 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
3621 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */
3622 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */
3623 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */
3624 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */
3625 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */
3626 
3627 #define ADC_SQR2_SQ8_Pos (5U)
3628 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */
3629 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
3630 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */
3631 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */
3632 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */
3633 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */
3634 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */
3635 
3636 #define ADC_SQR2_SQ9_Pos (10U)
3637 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */
3638 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
3639 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */
3640 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */
3641 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */
3642 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */
3643 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */
3644 
3645 #define ADC_SQR2_SQ10_Pos (15U)
3646 #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */
3647 #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
3648 #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */
3649 #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */
3650 #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */
3651 #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */
3652 #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */
3653 
3654 #define ADC_SQR2_SQ11_Pos (20U)
3655 #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */
3656 #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */
3657 #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */
3658 #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */
3659 #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */
3660 #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */
3661 #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */
3662 
3663 #define ADC_SQR2_SQ12_Pos (25U)
3664 #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */
3665 #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
3666 #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */
3667 #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */
3668 #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */
3669 #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */
3670 #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */
3671 
3672 /******************* Bit definition for ADC_SQR3 register *******************/
3673 #define ADC_SQR3_SQ1_Pos (0U)
3674 #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */
3675 #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
3676 #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */
3677 #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */
3678 #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */
3679 #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */
3680 #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */
3681 
3682 #define ADC_SQR3_SQ2_Pos (5U)
3683 #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */
3684 #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
3685 #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */
3686 #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */
3687 #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */
3688 #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */
3689 #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */
3690 
3691 #define ADC_SQR3_SQ3_Pos (10U)
3692 #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */
3693 #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
3694 #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */
3695 #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */
3696 #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */
3697 #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */
3698 #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */
3699 
3700 #define ADC_SQR3_SQ4_Pos (15U)
3701 #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */
3702 #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
3703 #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */
3704 #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */
3705 #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */
3706 #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */
3707 #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */
3708 
3709 #define ADC_SQR3_SQ5_Pos (20U)
3710 #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */
3711 #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
3712 #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */
3713 #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */
3714 #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */
3715 #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */
3716 #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */
3717 
3718 #define ADC_SQR3_SQ6_Pos (25U)
3719 #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */
3720 #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
3721 #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */
3722 #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */
3723 #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */
3724 #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */
3725 #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */
3726 
3727 /******************* Bit definition for ADC_JSQR register *******************/
3728 #define ADC_JSQR_JSQ1_Pos (0U)
3729 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */
3730 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
3731 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */
3732 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */
3733 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */
3734 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */
3735 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */
3736 
3737 #define ADC_JSQR_JSQ2_Pos (5U)
3738 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */
3739 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
3740 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */
3741 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */
3742 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */
3743 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */
3744 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */
3745 
3746 #define ADC_JSQR_JSQ3_Pos (10U)
3747 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */
3748 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
3749 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */
3750 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */
3751 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */
3752 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */
3753 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */
3754 
3755 #define ADC_JSQR_JSQ4_Pos (15U)
3756 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */
3757 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
3758 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */
3759 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */
3760 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */
3761 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */
3762 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */
3763 
3764 #define ADC_JSQR_JL_Pos (20U)
3765 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */
3766 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
3767 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */
3768 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */
3769 
3770 /******************* Bit definition for ADC_JDR1 register *******************/
3771 #define ADC_JDR1_JDATA_Pos (0U)
3772 #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
3773 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
3774 
3775 /******************* Bit definition for ADC_JDR2 register *******************/
3776 #define ADC_JDR2_JDATA_Pos (0U)
3777 #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
3778 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
3779 
3780 /******************* Bit definition for ADC_JDR3 register *******************/
3781 #define ADC_JDR3_JDATA_Pos (0U)
3782 #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
3783 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
3784 
3785 /******************* Bit definition for ADC_JDR4 register *******************/
3786 #define ADC_JDR4_JDATA_Pos (0U)
3787 #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
3788 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
3789 
3790 /******************** Bit definition for ADC_DR register ********************/
3791 #define ADC_DR_DATA_Pos (0U)
3792 #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
3793 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
3794 #define ADC_DR_ADC2DATA_Pos (16U)
3795 #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */
3796 #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */
3797 
3798 
3799 /*****************************************************************************/
3800 /* */
3801 /* Timers (TIM) */
3802 /* */
3803 /*****************************************************************************/
3804 /******************* Bit definition for TIM_CR1 register *******************/
3805 #define TIM_CR1_CEN_Pos (0U)
3806 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
3807 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
3808 #define TIM_CR1_UDIS_Pos (1U)
3809 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
3810 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
3811 #define TIM_CR1_URS_Pos (2U)
3812 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
3813 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
3814 #define TIM_CR1_OPM_Pos (3U)
3815 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
3816 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
3817 #define TIM_CR1_DIR_Pos (4U)
3818 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
3819 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
3820 
3821 #define TIM_CR1_CMS_Pos (5U)
3822 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
3823 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
3824 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
3825 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
3826 
3827 #define TIM_CR1_ARPE_Pos (7U)
3828 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
3829 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
3830 
3831 #define TIM_CR1_CKD_Pos (8U)
3832 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
3833 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
3834 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
3835 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
3836 
3837 /******************* Bit definition for TIM_CR2 register *******************/
3838 #define TIM_CR2_CCPC_Pos (0U)
3839 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
3840 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
3841 #define TIM_CR2_CCUS_Pos (2U)
3842 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
3843 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
3844 #define TIM_CR2_CCDS_Pos (3U)
3845 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
3846 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
3847 
3848 #define TIM_CR2_MMS_Pos (4U)
3849 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
3850 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
3851 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
3852 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
3853 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
3854 
3855 #define TIM_CR2_TI1S_Pos (7U)
3856 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
3857 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
3858 #define TIM_CR2_OIS1_Pos (8U)
3859 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
3860 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
3861 #define TIM_CR2_OIS1N_Pos (9U)
3862 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
3863 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
3864 #define TIM_CR2_OIS2_Pos (10U)
3865 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
3866 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
3867 #define TIM_CR2_OIS2N_Pos (11U)
3868 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
3869 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
3870 #define TIM_CR2_OIS3_Pos (12U)
3871 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
3872 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
3873 #define TIM_CR2_OIS3N_Pos (13U)
3874 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
3875 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
3876 #define TIM_CR2_OIS4_Pos (14U)
3877 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
3878 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
3879 
3880 /******************* Bit definition for TIM_SMCR register ******************/
3881 #define TIM_SMCR_SMS_Pos (0U)
3882 #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
3883 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
3884 #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
3885 #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
3886 #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
3887 
3888 #define TIM_SMCR_TS_Pos (4U)
3889 #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
3890 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
3891 #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
3892 #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
3893 #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
3894 
3895 #define TIM_SMCR_MSM_Pos (7U)
3896 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
3897 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
3898 
3899 #define TIM_SMCR_ETF_Pos (8U)
3900 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
3901 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
3902 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
3903 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
3904 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
3905 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
3906 
3907 #define TIM_SMCR_ETPS_Pos (12U)
3908 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
3909 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
3910 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
3911 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
3912 
3913 #define TIM_SMCR_ECE_Pos (14U)
3914 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
3915 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
3916 #define TIM_SMCR_ETP_Pos (15U)
3917 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
3918 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
3919 
3920 /******************* Bit definition for TIM_DIER register ******************/
3921 #define TIM_DIER_UIE_Pos (0U)
3922 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
3923 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
3924 #define TIM_DIER_CC1IE_Pos (1U)
3925 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
3926 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
3927 #define TIM_DIER_CC2IE_Pos (2U)
3928 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
3929 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
3930 #define TIM_DIER_CC3IE_Pos (3U)
3931 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
3932 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
3933 #define TIM_DIER_CC4IE_Pos (4U)
3934 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
3935 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
3936 #define TIM_DIER_COMIE_Pos (5U)
3937 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
3938 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
3939 #define TIM_DIER_TIE_Pos (6U)
3940 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
3941 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
3942 #define TIM_DIER_BIE_Pos (7U)
3943 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
3944 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
3945 #define TIM_DIER_UDE_Pos (8U)
3946 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
3947 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
3948 #define TIM_DIER_CC1DE_Pos (9U)
3949 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
3950 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
3951 #define TIM_DIER_CC2DE_Pos (10U)
3952 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
3953 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
3954 #define TIM_DIER_CC3DE_Pos (11U)
3955 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
3956 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
3957 #define TIM_DIER_CC4DE_Pos (12U)
3958 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
3959 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
3960 #define TIM_DIER_COMDE_Pos (13U)
3961 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
3962 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
3963 #define TIM_DIER_TDE_Pos (14U)
3964 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
3965 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
3966 
3967 /******************** Bit definition for TIM_SR register *******************/
3968 #define TIM_SR_UIF_Pos (0U)
3969 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
3970 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
3971 #define TIM_SR_CC1IF_Pos (1U)
3972 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
3973 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
3974 #define TIM_SR_CC2IF_Pos (2U)
3975 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
3976 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
3977 #define TIM_SR_CC3IF_Pos (3U)
3978 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
3979 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
3980 #define TIM_SR_CC4IF_Pos (4U)
3981 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
3982 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
3983 #define TIM_SR_COMIF_Pos (5U)
3984 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
3985 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
3986 #define TIM_SR_TIF_Pos (6U)
3987 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
3988 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
3989 #define TIM_SR_BIF_Pos (7U)
3990 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
3991 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
3992 #define TIM_SR_CC1OF_Pos (9U)
3993 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
3994 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
3995 #define TIM_SR_CC2OF_Pos (10U)
3996 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
3997 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
3998 #define TIM_SR_CC3OF_Pos (11U)
3999 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
4000 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
4001 #define TIM_SR_CC4OF_Pos (12U)
4002 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
4003 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
4004 
4005 /******************* Bit definition for TIM_EGR register *******************/
4006 #define TIM_EGR_UG_Pos (0U)
4007 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
4008 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
4009 #define TIM_EGR_CC1G_Pos (1U)
4010 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
4011 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
4012 #define TIM_EGR_CC2G_Pos (2U)
4013 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
4014 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
4015 #define TIM_EGR_CC3G_Pos (3U)
4016 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
4017 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
4018 #define TIM_EGR_CC4G_Pos (4U)
4019 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
4020 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
4021 #define TIM_EGR_COMG_Pos (5U)
4022 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
4023 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
4024 #define TIM_EGR_TG_Pos (6U)
4025 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
4026 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
4027 #define TIM_EGR_BG_Pos (7U)
4028 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
4029 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
4030 
4031 /****************** Bit definition for TIM_CCMR1 register ******************/
4032 #define TIM_CCMR1_CC1S_Pos (0U)
4033 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
4034 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
4035 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
4036 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
4037 
4038 #define TIM_CCMR1_OC1FE_Pos (2U)
4039 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
4040 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
4041 #define TIM_CCMR1_OC1PE_Pos (3U)
4042 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
4043 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
4044 
4045 #define TIM_CCMR1_OC1M_Pos (4U)
4046 #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
4047 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
4048 #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
4049 #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
4050 #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
4051 
4052 #define TIM_CCMR1_OC1CE_Pos (7U)
4053 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
4054 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
4055 
4056 #define TIM_CCMR1_CC2S_Pos (8U)
4057 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
4058 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
4059 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
4060 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
4061 
4062 #define TIM_CCMR1_OC2FE_Pos (10U)
4063 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
4064 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
4065 #define TIM_CCMR1_OC2PE_Pos (11U)
4066 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
4067 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
4068 
4069 #define TIM_CCMR1_OC2M_Pos (12U)
4070 #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
4071 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
4072 #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
4073 #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
4074 #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
4075 
4076 #define TIM_CCMR1_OC2CE_Pos (15U)
4077 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
4078 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
4079 
4080 /*---------------------------------------------------------------------------*/
4081 
4082 #define TIM_CCMR1_IC1PSC_Pos (2U)
4083 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
4084 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
4085 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
4086 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
4087 
4088 #define TIM_CCMR1_IC1F_Pos (4U)
4089 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
4090 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
4091 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
4092 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
4093 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
4094 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
4095 
4096 #define TIM_CCMR1_IC2PSC_Pos (10U)
4097 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
4098 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
4099 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
4100 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
4101 
4102 #define TIM_CCMR1_IC2F_Pos (12U)
4103 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
4104 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
4105 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
4106 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
4107 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
4108 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
4109 
4110 /****************** Bit definition for TIM_CCMR2 register ******************/
4111 #define TIM_CCMR2_CC3S_Pos (0U)
4112 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
4113 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
4114 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
4115 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
4116 
4117 #define TIM_CCMR2_OC3FE_Pos (2U)
4118 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
4119 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
4120 #define TIM_CCMR2_OC3PE_Pos (3U)
4121 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
4122 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
4123 
4124 #define TIM_CCMR2_OC3M_Pos (4U)
4125 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
4126 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
4127 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
4128 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
4129 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
4130 
4131 #define TIM_CCMR2_OC3CE_Pos (7U)
4132 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
4133 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
4134 
4135 #define TIM_CCMR2_CC4S_Pos (8U)
4136 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
4137 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
4138 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
4139 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
4140 
4141 #define TIM_CCMR2_OC4FE_Pos (10U)
4142 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
4143 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
4144 #define TIM_CCMR2_OC4PE_Pos (11U)
4145 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
4146 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
4147 
4148 #define TIM_CCMR2_OC4M_Pos (12U)
4149 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
4150 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
4151 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
4152 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
4153 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
4154 
4155 #define TIM_CCMR2_OC4CE_Pos (15U)
4156 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
4157 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
4158 
4159 /*---------------------------------------------------------------------------*/
4160 
4161 #define TIM_CCMR2_IC3PSC_Pos (2U)
4162 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
4163 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
4164 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
4165 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
4166 
4167 #define TIM_CCMR2_IC3F_Pos (4U)
4168 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
4169 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
4170 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
4171 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
4172 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
4173 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
4174 
4175 #define TIM_CCMR2_IC4PSC_Pos (10U)
4176 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
4177 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
4178 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
4179 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
4180 
4181 #define TIM_CCMR2_IC4F_Pos (12U)
4182 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
4183 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
4184 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
4185 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
4186 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
4187 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
4188 
4189 /******************* Bit definition for TIM_CCER register ******************/
4190 #define TIM_CCER_CC1E_Pos (0U)
4191 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
4192 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
4193 #define TIM_CCER_CC1P_Pos (1U)
4194 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
4195 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
4196 #define TIM_CCER_CC1NE_Pos (2U)
4197 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
4198 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
4199 #define TIM_CCER_CC1NP_Pos (3U)
4200 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
4201 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
4202 #define TIM_CCER_CC2E_Pos (4U)
4203 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
4204 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
4205 #define TIM_CCER_CC2P_Pos (5U)
4206 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
4207 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
4208 #define TIM_CCER_CC2NE_Pos (6U)
4209 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
4210 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
4211 #define TIM_CCER_CC2NP_Pos (7U)
4212 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
4213 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
4214 #define TIM_CCER_CC3E_Pos (8U)
4215 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
4216 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
4217 #define TIM_CCER_CC3P_Pos (9U)
4218 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
4219 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
4220 #define TIM_CCER_CC3NE_Pos (10U)
4221 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
4222 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
4223 #define TIM_CCER_CC3NP_Pos (11U)
4224 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
4225 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
4226 #define TIM_CCER_CC4E_Pos (12U)
4227 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
4228 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
4229 #define TIM_CCER_CC4P_Pos (13U)
4230 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
4231 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
4232 
4233 /******************* Bit definition for TIM_CNT register *******************/
4234 #define TIM_CNT_CNT_Pos (0U)
4235 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
4236 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
4237 
4238 /******************* Bit definition for TIM_PSC register *******************/
4239 #define TIM_PSC_PSC_Pos (0U)
4240 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
4241 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
4242 
4243 /******************* Bit definition for TIM_ARR register *******************/
4244 #define TIM_ARR_ARR_Pos (0U)
4245 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
4246 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
4247 
4248 /******************* Bit definition for TIM_RCR register *******************/
4249 #define TIM_RCR_REP_Pos (0U)
4250 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
4251 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
4252 
4253 /******************* Bit definition for TIM_CCR1 register ******************/
4254 #define TIM_CCR1_CCR1_Pos (0U)
4255 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
4256 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
4257 
4258 /******************* Bit definition for TIM_CCR2 register ******************/
4259 #define TIM_CCR2_CCR2_Pos (0U)
4260 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
4261 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
4262 
4263 /******************* Bit definition for TIM_CCR3 register ******************/
4264 #define TIM_CCR3_CCR3_Pos (0U)
4265 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
4266 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
4267 
4268 /******************* Bit definition for TIM_CCR4 register ******************/
4269 #define TIM_CCR4_CCR4_Pos (0U)
4270 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
4271 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
4272 
4273 /******************* Bit definition for TIM_BDTR register ******************/
4274 #define TIM_BDTR_DTG_Pos (0U)
4275 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
4276 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
4277 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
4278 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
4279 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
4280 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
4281 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
4282 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
4283 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
4284 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
4285 
4286 #define TIM_BDTR_LOCK_Pos (8U)
4287 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
4288 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
4289 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
4290 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
4291 
4292 #define TIM_BDTR_OSSI_Pos (10U)
4293 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
4294 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
4295 #define TIM_BDTR_OSSR_Pos (11U)
4296 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
4297 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
4298 #define TIM_BDTR_BKE_Pos (12U)
4299 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
4300 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
4301 #define TIM_BDTR_BKP_Pos (13U)
4302 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
4303 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
4304 #define TIM_BDTR_AOE_Pos (14U)
4305 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
4306 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
4307 #define TIM_BDTR_MOE_Pos (15U)
4308 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
4309 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
4310 
4311 /******************* Bit definition for TIM_DCR register *******************/
4312 #define TIM_DCR_DBA_Pos (0U)
4313 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
4314 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
4315 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
4316 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
4317 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
4318 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
4319 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
4320 
4321 #define TIM_DCR_DBL_Pos (8U)
4322 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
4323 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
4324 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
4325 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
4326 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
4327 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
4328 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
4329 
4330 /******************* Bit definition for TIM_DMAR register ******************/
4331 #define TIM_DMAR_DMAB_Pos (0U)
4332 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
4333 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
4334 
4335 /******************************************************************************/
4336 /* */
4337 /* Real-Time Clock */
4338 /* */
4339 /******************************************************************************/
4340 
4341 /******************* Bit definition for RTC_CRH register ********************/
4342 #define RTC_CRH_SECIE_Pos (0U)
4343 #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */
4344 #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */
4345 #define RTC_CRH_ALRIE_Pos (1U)
4346 #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */
4347 #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */
4348 #define RTC_CRH_OWIE_Pos (2U)
4349 #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */
4350 #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */
4351 
4352 /******************* Bit definition for RTC_CRL register ********************/
4353 #define RTC_CRL_SECF_Pos (0U)
4354 #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */
4355 #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */
4356 #define RTC_CRL_ALRF_Pos (1U)
4357 #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */
4358 #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */
4359 #define RTC_CRL_OWF_Pos (2U)
4360 #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */
4361 #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */
4362 #define RTC_CRL_RSF_Pos (3U)
4363 #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */
4364 #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */
4365 #define RTC_CRL_CNF_Pos (4U)
4366 #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */
4367 #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */
4368 #define RTC_CRL_RTOFF_Pos (5U)
4369 #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */
4370 #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */
4371 
4372 /******************* Bit definition for RTC_PRLH register *******************/
4373 #define RTC_PRLH_PRL_Pos (0U)
4374 #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */
4375 #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */
4376 
4377 /******************* Bit definition for RTC_PRLL register *******************/
4378 #define RTC_PRLL_PRL_Pos (0U)
4379 #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */
4380 #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */
4381 
4382 /******************* Bit definition for RTC_DIVH register *******************/
4383 #define RTC_DIVH_RTC_DIV_Pos (0U)
4384 #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */
4385 #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */
4386 
4387 /******************* Bit definition for RTC_DIVL register *******************/
4388 #define RTC_DIVL_RTC_DIV_Pos (0U)
4389 #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */
4390 #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */
4391 
4392 /******************* Bit definition for RTC_CNTH register *******************/
4393 #define RTC_CNTH_RTC_CNT_Pos (0U)
4394 #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */
4395 #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */
4396 
4397 /******************* Bit definition for RTC_CNTL register *******************/
4398 #define RTC_CNTL_RTC_CNT_Pos (0U)
4399 #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */
4400 #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */
4401 
4402 /******************* Bit definition for RTC_ALRH register *******************/
4403 #define RTC_ALRH_RTC_ALR_Pos (0U)
4404 #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */
4405 #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */
4406 
4407 /******************* Bit definition for RTC_ALRL register *******************/
4408 #define RTC_ALRL_RTC_ALR_Pos (0U)
4409 #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */
4410 #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */
4411 
4412 /******************************************************************************/
4413 /* */
4414 /* Independent WATCHDOG (IWDG) */
4415 /* */
4416 /******************************************************************************/
4417 
4418 /******************* Bit definition for IWDG_KR register ********************/
4419 #define IWDG_KR_KEY_Pos (0U)
4420 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
4421 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
4422 
4423 /******************* Bit definition for IWDG_PR register ********************/
4424 #define IWDG_PR_PR_Pos (0U)
4425 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
4426 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
4427 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
4428 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
4429 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
4430 
4431 /******************* Bit definition for IWDG_RLR register *******************/
4432 #define IWDG_RLR_RL_Pos (0U)
4433 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
4434 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
4435 
4436 /******************* Bit definition for IWDG_SR register ********************/
4437 #define IWDG_SR_PVU_Pos (0U)
4438 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
4439 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
4440 #define IWDG_SR_RVU_Pos (1U)
4441 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
4442 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
4443 
4444 /******************************************************************************/
4445 /* */
4446 /* Window WATCHDOG (WWDG) */
4447 /* */
4448 /******************************************************************************/
4449 
4450 /******************* Bit definition for WWDG_CR register ********************/
4451 #define WWDG_CR_T_Pos (0U)
4452 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
4453 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
4454 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
4455 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
4456 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
4457 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
4458 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
4459 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
4460 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
4461 
4462 /* Legacy defines */
4463 #define WWDG_CR_T0 WWDG_CR_T_0
4464 #define WWDG_CR_T1 WWDG_CR_T_1
4465 #define WWDG_CR_T2 WWDG_CR_T_2
4466 #define WWDG_CR_T3 WWDG_CR_T_3
4467 #define WWDG_CR_T4 WWDG_CR_T_4
4468 #define WWDG_CR_T5 WWDG_CR_T_5
4469 #define WWDG_CR_T6 WWDG_CR_T_6
4470 
4471 #define WWDG_CR_WDGA_Pos (7U)
4472 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
4473 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
4474 
4475 /******************* Bit definition for WWDG_CFR register *******************/
4476 #define WWDG_CFR_W_Pos (0U)
4477 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
4478 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
4479 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
4480 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
4481 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
4482 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
4483 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
4484 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
4485 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
4486 
4487 /* Legacy defines */
4488 #define WWDG_CFR_W0 WWDG_CFR_W_0
4489 #define WWDG_CFR_W1 WWDG_CFR_W_1
4490 #define WWDG_CFR_W2 WWDG_CFR_W_2
4491 #define WWDG_CFR_W3 WWDG_CFR_W_3
4492 #define WWDG_CFR_W4 WWDG_CFR_W_4
4493 #define WWDG_CFR_W5 WWDG_CFR_W_5
4494 #define WWDG_CFR_W6 WWDG_CFR_W_6
4495 
4496 #define WWDG_CFR_WDGTB_Pos (7U)
4497 #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
4498 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
4499 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
4500 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
4501 
4502 /* Legacy defines */
4503 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
4504 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
4505 
4506 #define WWDG_CFR_EWI_Pos (9U)
4507 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
4508 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
4509 
4510 /******************* Bit definition for WWDG_SR register ********************/
4511 #define WWDG_SR_EWIF_Pos (0U)
4512 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
4513 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
4514 
4515 /******************************************************************************/
4516 /* */
4517 /* USB Device FS */
4518 /* */
4519 /******************************************************************************/
4520 
4521 /*!< Endpoint-specific registers */
4522 #define USB_EP0R USB_BASE /*!< Endpoint 0 register address */
4523 #define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */
4524 #define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */
4525 #define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */
4526 #define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */
4527 #define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */
4528 #define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */
4529 #define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */
4530 
4531 /* bit positions */
4532 #define USB_EP_CTR_RX_Pos (15U)
4533 #define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */
4534 #define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */
4535 #define USB_EP_DTOG_RX_Pos (14U)
4536 #define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */
4537 #define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */
4538 #define USB_EPRX_STAT_Pos (12U)
4539 #define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */
4540 #define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */
4541 #define USB_EP_SETUP_Pos (11U)
4542 #define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */
4543 #define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */
4544 #define USB_EP_T_FIELD_Pos (9U)
4545 #define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */
4546 #define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */
4547 #define USB_EP_KIND_Pos (8U)
4548 #define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */
4549 #define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */
4550 #define USB_EP_CTR_TX_Pos (7U)
4551 #define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */
4552 #define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */
4553 #define USB_EP_DTOG_TX_Pos (6U)
4554 #define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */
4555 #define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */
4556 #define USB_EPTX_STAT_Pos (4U)
4557 #define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */
4558 #define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */
4559 #define USB_EPADDR_FIELD_Pos (0U)
4560 #define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */
4561 #define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */
4562 
4563 /* EndPoint REGister MASK (no toggle fields) */
4564 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
4565  /*!< EP_TYPE[1:0] EndPoint TYPE */
4566 #define USB_EP_TYPE_MASK_Pos (9U)
4567 #define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */
4568 #define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */
4569 #define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */
4570 #define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */
4571 #define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */
4572 #define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */
4573 #define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK)
4574 
4575 #define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
4576  /*!< STAT_TX[1:0] STATus for TX transfer */
4577 #define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */
4578 #define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */
4579 #define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */
4580 #define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */
4581 #define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */
4582 #define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */
4583 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
4584  /*!< STAT_RX[1:0] STATus for RX transfer */
4585 #define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */
4586 #define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */
4587 #define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */
4588 #define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */
4589 #define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */
4590 #define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */
4591 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
4592 
4593 /******************* Bit definition for USB_EP0R register *******************/
4594 #define USB_EP0R_EA_Pos (0U)
4595 #define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */
4596 #define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */
4597 
4598 #define USB_EP0R_STAT_TX_Pos (4U)
4599 #define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */
4600 #define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4601 #define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */
4602 #define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */
4603 
4604 #define USB_EP0R_DTOG_TX_Pos (6U)
4605 #define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */
4606 #define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4607 #define USB_EP0R_CTR_TX_Pos (7U)
4608 #define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */
4609 #define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4610 #define USB_EP0R_EP_KIND_Pos (8U)
4611 #define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */
4612 #define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */
4613 
4614 #define USB_EP0R_EP_TYPE_Pos (9U)
4615 #define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */
4616 #define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4617 #define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */
4618 #define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */
4619 
4620 #define USB_EP0R_SETUP_Pos (11U)
4621 #define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */
4622 #define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */
4623 
4624 #define USB_EP0R_STAT_RX_Pos (12U)
4625 #define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */
4626 #define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4627 #define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */
4628 #define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */
4629 
4630 #define USB_EP0R_DTOG_RX_Pos (14U)
4631 #define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */
4632 #define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4633 #define USB_EP0R_CTR_RX_Pos (15U)
4634 #define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */
4635 #define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */
4636 
4637 /******************* Bit definition for USB_EP1R register *******************/
4638 #define USB_EP1R_EA_Pos (0U)
4639 #define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */
4640 #define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */
4641 
4642 #define USB_EP1R_STAT_TX_Pos (4U)
4643 #define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */
4644 #define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4645 #define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */
4646 #define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */
4647 
4648 #define USB_EP1R_DTOG_TX_Pos (6U)
4649 #define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */
4650 #define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4651 #define USB_EP1R_CTR_TX_Pos (7U)
4652 #define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */
4653 #define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4654 #define USB_EP1R_EP_KIND_Pos (8U)
4655 #define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */
4656 #define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */
4657 
4658 #define USB_EP1R_EP_TYPE_Pos (9U)
4659 #define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */
4660 #define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4661 #define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */
4662 #define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */
4663 
4664 #define USB_EP1R_SETUP_Pos (11U)
4665 #define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */
4666 #define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */
4667 
4668 #define USB_EP1R_STAT_RX_Pos (12U)
4669 #define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */
4670 #define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4671 #define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */
4672 #define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */
4673 
4674 #define USB_EP1R_DTOG_RX_Pos (14U)
4675 #define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */
4676 #define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4677 #define USB_EP1R_CTR_RX_Pos (15U)
4678 #define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */
4679 #define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */
4680 
4681 /******************* Bit definition for USB_EP2R register *******************/
4682 #define USB_EP2R_EA_Pos (0U)
4683 #define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */
4684 #define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */
4685 
4686 #define USB_EP2R_STAT_TX_Pos (4U)
4687 #define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */
4688 #define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4689 #define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */
4690 #define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */
4691 
4692 #define USB_EP2R_DTOG_TX_Pos (6U)
4693 #define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */
4694 #define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4695 #define USB_EP2R_CTR_TX_Pos (7U)
4696 #define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */
4697 #define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4698 #define USB_EP2R_EP_KIND_Pos (8U)
4699 #define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */
4700 #define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */
4701 
4702 #define USB_EP2R_EP_TYPE_Pos (9U)
4703 #define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */
4704 #define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4705 #define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */
4706 #define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */
4707 
4708 #define USB_EP2R_SETUP_Pos (11U)
4709 #define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */
4710 #define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */
4711 
4712 #define USB_EP2R_STAT_RX_Pos (12U)
4713 #define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */
4714 #define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4715 #define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */
4716 #define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */
4717 
4718 #define USB_EP2R_DTOG_RX_Pos (14U)
4719 #define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */
4720 #define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4721 #define USB_EP2R_CTR_RX_Pos (15U)
4722 #define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */
4723 #define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */
4724 
4725 /******************* Bit definition for USB_EP3R register *******************/
4726 #define USB_EP3R_EA_Pos (0U)
4727 #define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */
4728 #define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */
4729 
4730 #define USB_EP3R_STAT_TX_Pos (4U)
4731 #define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */
4732 #define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4733 #define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */
4734 #define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */
4735 
4736 #define USB_EP3R_DTOG_TX_Pos (6U)
4737 #define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */
4738 #define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4739 #define USB_EP3R_CTR_TX_Pos (7U)
4740 #define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */
4741 #define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4742 #define USB_EP3R_EP_KIND_Pos (8U)
4743 #define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */
4744 #define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */
4745 
4746 #define USB_EP3R_EP_TYPE_Pos (9U)
4747 #define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */
4748 #define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4749 #define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */
4750 #define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */
4751 
4752 #define USB_EP3R_SETUP_Pos (11U)
4753 #define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */
4754 #define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */
4755 
4756 #define USB_EP3R_STAT_RX_Pos (12U)
4757 #define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */
4758 #define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4759 #define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */
4760 #define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */
4761 
4762 #define USB_EP3R_DTOG_RX_Pos (14U)
4763 #define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */
4764 #define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4765 #define USB_EP3R_CTR_RX_Pos (15U)
4766 #define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */
4767 #define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */
4768 
4769 /******************* Bit definition for USB_EP4R register *******************/
4770 #define USB_EP4R_EA_Pos (0U)
4771 #define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */
4772 #define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */
4773 
4774 #define USB_EP4R_STAT_TX_Pos (4U)
4775 #define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */
4776 #define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4777 #define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */
4778 #define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */
4779 
4780 #define USB_EP4R_DTOG_TX_Pos (6U)
4781 #define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */
4782 #define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4783 #define USB_EP4R_CTR_TX_Pos (7U)
4784 #define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */
4785 #define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4786 #define USB_EP4R_EP_KIND_Pos (8U)
4787 #define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */
4788 #define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */
4789 
4790 #define USB_EP4R_EP_TYPE_Pos (9U)
4791 #define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */
4792 #define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4793 #define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */
4794 #define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */
4795 
4796 #define USB_EP4R_SETUP_Pos (11U)
4797 #define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */
4798 #define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */
4799 
4800 #define USB_EP4R_STAT_RX_Pos (12U)
4801 #define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */
4802 #define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4803 #define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */
4804 #define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */
4805 
4806 #define USB_EP4R_DTOG_RX_Pos (14U)
4807 #define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */
4808 #define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4809 #define USB_EP4R_CTR_RX_Pos (15U)
4810 #define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */
4811 #define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */
4812 
4813 /******************* Bit definition for USB_EP5R register *******************/
4814 #define USB_EP5R_EA_Pos (0U)
4815 #define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */
4816 #define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */
4817 
4818 #define USB_EP5R_STAT_TX_Pos (4U)
4819 #define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */
4820 #define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4821 #define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */
4822 #define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */
4823 
4824 #define USB_EP5R_DTOG_TX_Pos (6U)
4825 #define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */
4826 #define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4827 #define USB_EP5R_CTR_TX_Pos (7U)
4828 #define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */
4829 #define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4830 #define USB_EP5R_EP_KIND_Pos (8U)
4831 #define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */
4832 #define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */
4833 
4834 #define USB_EP5R_EP_TYPE_Pos (9U)
4835 #define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */
4836 #define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4837 #define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */
4838 #define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */
4839 
4840 #define USB_EP5R_SETUP_Pos (11U)
4841 #define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */
4842 #define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */
4843 
4844 #define USB_EP5R_STAT_RX_Pos (12U)
4845 #define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */
4846 #define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4847 #define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */
4848 #define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */
4849 
4850 #define USB_EP5R_DTOG_RX_Pos (14U)
4851 #define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */
4852 #define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4853 #define USB_EP5R_CTR_RX_Pos (15U)
4854 #define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */
4855 #define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */
4856 
4857 /******************* Bit definition for USB_EP6R register *******************/
4858 #define USB_EP6R_EA_Pos (0U)
4859 #define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */
4860 #define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */
4861 
4862 #define USB_EP6R_STAT_TX_Pos (4U)
4863 #define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */
4864 #define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4865 #define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */
4866 #define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */
4867 
4868 #define USB_EP6R_DTOG_TX_Pos (6U)
4869 #define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */
4870 #define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4871 #define USB_EP6R_CTR_TX_Pos (7U)
4872 #define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */
4873 #define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4874 #define USB_EP6R_EP_KIND_Pos (8U)
4875 #define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */
4876 #define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */
4877 
4878 #define USB_EP6R_EP_TYPE_Pos (9U)
4879 #define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */
4880 #define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4881 #define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */
4882 #define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */
4883 
4884 #define USB_EP6R_SETUP_Pos (11U)
4885 #define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */
4886 #define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */
4887 
4888 #define USB_EP6R_STAT_RX_Pos (12U)
4889 #define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */
4890 #define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4891 #define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */
4892 #define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */
4893 
4894 #define USB_EP6R_DTOG_RX_Pos (14U)
4895 #define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */
4896 #define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4897 #define USB_EP6R_CTR_RX_Pos (15U)
4898 #define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */
4899 #define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */
4900 
4901 /******************* Bit definition for USB_EP7R register *******************/
4902 #define USB_EP7R_EA_Pos (0U)
4903 #define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */
4904 #define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */
4905 
4906 #define USB_EP7R_STAT_TX_Pos (4U)
4907 #define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */
4908 #define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */
4909 #define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */
4910 #define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */
4911 
4912 #define USB_EP7R_DTOG_TX_Pos (6U)
4913 #define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */
4914 #define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */
4915 #define USB_EP7R_CTR_TX_Pos (7U)
4916 #define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */
4917 #define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */
4918 #define USB_EP7R_EP_KIND_Pos (8U)
4919 #define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */
4920 #define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */
4921 
4922 #define USB_EP7R_EP_TYPE_Pos (9U)
4923 #define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */
4924 #define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */
4925 #define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */
4926 #define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */
4927 
4928 #define USB_EP7R_SETUP_Pos (11U)
4929 #define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */
4930 #define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */
4931 
4932 #define USB_EP7R_STAT_RX_Pos (12U)
4933 #define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */
4934 #define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */
4935 #define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */
4936 #define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */
4937 
4938 #define USB_EP7R_DTOG_RX_Pos (14U)
4939 #define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */
4940 #define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */
4941 #define USB_EP7R_CTR_RX_Pos (15U)
4942 #define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */
4943 #define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */
4944 
4945 /*!< Common registers */
4946 /******************* Bit definition for USB_CNTR register *******************/
4947 #define USB_CNTR_FRES_Pos (0U)
4948 #define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */
4949 #define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */
4950 #define USB_CNTR_PDWN_Pos (1U)
4951 #define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */
4952 #define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */
4953 #define USB_CNTR_LP_MODE_Pos (2U)
4954 #define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */
4955 #define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */
4956 #define USB_CNTR_FSUSP_Pos (3U)
4957 #define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */
4958 #define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */
4959 #define USB_CNTR_RESUME_Pos (4U)
4960 #define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */
4961 #define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */
4962 #define USB_CNTR_ESOFM_Pos (8U)
4963 #define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */
4964 #define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */
4965 #define USB_CNTR_SOFM_Pos (9U)
4966 #define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */
4967 #define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */
4968 #define USB_CNTR_RESETM_Pos (10U)
4969 #define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */
4970 #define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */
4971 #define USB_CNTR_SUSPM_Pos (11U)
4972 #define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */
4973 #define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */
4974 #define USB_CNTR_WKUPM_Pos (12U)
4975 #define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */
4976 #define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */
4977 #define USB_CNTR_ERRM_Pos (13U)
4978 #define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */
4979 #define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */
4980 #define USB_CNTR_PMAOVRM_Pos (14U)
4981 #define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */
4982 #define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */
4983 #define USB_CNTR_CTRM_Pos (15U)
4984 #define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */
4985 #define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */
4986 
4987 /******************* Bit definition for USB_ISTR register *******************/
4988 #define USB_ISTR_EP_ID_Pos (0U)
4989 #define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */
4990 #define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */
4991 #define USB_ISTR_DIR_Pos (4U)
4992 #define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */
4993 #define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */
4994 #define USB_ISTR_ESOF_Pos (8U)
4995 #define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */
4996 #define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */
4997 #define USB_ISTR_SOF_Pos (9U)
4998 #define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */
4999 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */
5000 #define USB_ISTR_RESET_Pos (10U)
5001 #define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */
5002 #define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */
5003 #define USB_ISTR_SUSP_Pos (11U)
5004 #define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */
5005 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */
5006 #define USB_ISTR_WKUP_Pos (12U)
5007 #define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */
5008 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */
5009 #define USB_ISTR_ERR_Pos (13U)
5010 #define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */
5011 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */
5012 #define USB_ISTR_PMAOVR_Pos (14U)
5013 #define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */
5014 #define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */
5015 #define USB_ISTR_CTR_Pos (15U)
5016 #define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */
5017 #define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */
5018 
5019 /******************* Bit definition for USB_FNR register ********************/
5020 #define USB_FNR_FN_Pos (0U)
5021 #define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */
5022 #define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */
5023 #define USB_FNR_LSOF_Pos (11U)
5024 #define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */
5025 #define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */
5026 #define USB_FNR_LCK_Pos (13U)
5027 #define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */
5028 #define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */
5029 #define USB_FNR_RXDM_Pos (14U)
5030 #define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */
5031 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */
5032 #define USB_FNR_RXDP_Pos (15U)
5033 #define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */
5034 #define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */
5035 
5036 /****************** Bit definition for USB_DADDR register *******************/
5037 #define USB_DADDR_ADD_Pos (0U)
5038 #define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */
5039 #define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */
5040 #define USB_DADDR_ADD0_Pos (0U)
5041 #define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */
5042 #define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */
5043 #define USB_DADDR_ADD1_Pos (1U)
5044 #define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */
5045 #define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */
5046 #define USB_DADDR_ADD2_Pos (2U)
5047 #define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */
5048 #define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */
5049 #define USB_DADDR_ADD3_Pos (3U)
5050 #define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */
5051 #define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */
5052 #define USB_DADDR_ADD4_Pos (4U)
5053 #define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */
5054 #define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */
5055 #define USB_DADDR_ADD5_Pos (5U)
5056 #define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */
5057 #define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */
5058 #define USB_DADDR_ADD6_Pos (6U)
5059 #define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */
5060 #define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */
5061 
5062 #define USB_DADDR_EF_Pos (7U)
5063 #define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */
5064 #define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */
5065 
5066 /****************** Bit definition for USB_BTABLE register ******************/
5067 #define USB_BTABLE_BTABLE_Pos (3U)
5068 #define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
5069 #define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */
5070 
5071 /*!< Buffer descriptor table */
5072 /***************** Bit definition for USB_ADDR0_TX register *****************/
5073 #define USB_ADDR0_TX_ADDR0_TX_Pos (1U)
5074 #define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
5075 #define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */
5076 
5077 /***************** Bit definition for USB_ADDR1_TX register *****************/
5078 #define USB_ADDR1_TX_ADDR1_TX_Pos (1U)
5079 #define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
5080 #define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */
5081 
5082 /***************** Bit definition for USB_ADDR2_TX register *****************/
5083 #define USB_ADDR2_TX_ADDR2_TX_Pos (1U)
5084 #define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
5085 #define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */
5086 
5087 /***************** Bit definition for USB_ADDR3_TX register *****************/
5088 #define USB_ADDR3_TX_ADDR3_TX_Pos (1U)
5089 #define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
5090 #define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */
5091 
5092 /***************** Bit definition for USB_ADDR4_TX register *****************/
5093 #define USB_ADDR4_TX_ADDR4_TX_Pos (1U)
5094 #define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
5095 #define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */
5096 
5097 /***************** Bit definition for USB_ADDR5_TX register *****************/
5098 #define USB_ADDR5_TX_ADDR5_TX_Pos (1U)
5099 #define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
5100 #define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */
5101 
5102 /***************** Bit definition for USB_ADDR6_TX register *****************/
5103 #define USB_ADDR6_TX_ADDR6_TX_Pos (1U)
5104 #define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
5105 #define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */
5106 
5107 /***************** Bit definition for USB_ADDR7_TX register *****************/
5108 #define USB_ADDR7_TX_ADDR7_TX_Pos (1U)
5109 #define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
5110 #define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */
5111 
5112 /*----------------------------------------------------------------------------*/
5113 
5114 /***************** Bit definition for USB_COUNT0_TX register ****************/
5115 #define USB_COUNT0_TX_COUNT0_TX_Pos (0U)
5116 #define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
5117 #define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */
5118 
5119 /***************** Bit definition for USB_COUNT1_TX register ****************/
5120 #define USB_COUNT1_TX_COUNT1_TX_Pos (0U)
5121 #define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
5122 #define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */
5123 
5124 /***************** Bit definition for USB_COUNT2_TX register ****************/
5125 #define USB_COUNT2_TX_COUNT2_TX_Pos (0U)
5126 #define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
5127 #define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */
5128 
5129 /***************** Bit definition for USB_COUNT3_TX register ****************/
5130 #define USB_COUNT3_TX_COUNT3_TX_Pos (0U)
5131 #define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
5132 #define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */
5133 
5134 /***************** Bit definition for USB_COUNT4_TX register ****************/
5135 #define USB_COUNT4_TX_COUNT4_TX_Pos (0U)
5136 #define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
5137 #define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */
5138 
5139 /***************** Bit definition for USB_COUNT5_TX register ****************/
5140 #define USB_COUNT5_TX_COUNT5_TX_Pos (0U)
5141 #define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
5142 #define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */
5143 
5144 /***************** Bit definition for USB_COUNT6_TX register ****************/
5145 #define USB_COUNT6_TX_COUNT6_TX_Pos (0U)
5146 #define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
5147 #define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */
5148 
5149 /***************** Bit definition for USB_COUNT7_TX register ****************/
5150 #define USB_COUNT7_TX_COUNT7_TX_Pos (0U)
5151 #define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
5152 #define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */
5153 
5154 /*----------------------------------------------------------------------------*/
5155 
5156 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
5157 #define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */
5158 
5159 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
5160 #define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */
5161 
5162 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
5163 #define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */
5164 
5165 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
5166 #define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */
5167 
5168 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
5169 #define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */
5170 
5171 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
5172 #define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */
5173 
5174 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
5175 #define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */
5176 
5177 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
5178 #define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */
5179 
5180 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
5181 #define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */
5182 
5183 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
5184 #define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */
5185 
5186 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
5187 #define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */
5188 
5189 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
5190 #define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */
5191 
5192 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
5193 #define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */
5194 
5195 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
5196 #define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */
5197 
5198 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
5199 #define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */
5200 
5201 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
5202 #define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */
5203 
5204 /*----------------------------------------------------------------------------*/
5205 
5206 /***************** Bit definition for USB_ADDR0_RX register *****************/
5207 #define USB_ADDR0_RX_ADDR0_RX_Pos (1U)
5208 #define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
5209 #define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */
5210 
5211 /***************** Bit definition for USB_ADDR1_RX register *****************/
5212 #define USB_ADDR1_RX_ADDR1_RX_Pos (1U)
5213 #define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
5214 #define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */
5215 
5216 /***************** Bit definition for USB_ADDR2_RX register *****************/
5217 #define USB_ADDR2_RX_ADDR2_RX_Pos (1U)
5218 #define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
5219 #define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */
5220 
5221 /***************** Bit definition for USB_ADDR3_RX register *****************/
5222 #define USB_ADDR3_RX_ADDR3_RX_Pos (1U)
5223 #define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
5224 #define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */
5225 
5226 /***************** Bit definition for USB_ADDR4_RX register *****************/
5227 #define USB_ADDR4_RX_ADDR4_RX_Pos (1U)
5228 #define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
5229 #define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */
5230 
5231 /***************** Bit definition for USB_ADDR5_RX register *****************/
5232 #define USB_ADDR5_RX_ADDR5_RX_Pos (1U)
5233 #define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
5234 #define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */
5235 
5236 /***************** Bit definition for USB_ADDR6_RX register *****************/
5237 #define USB_ADDR6_RX_ADDR6_RX_Pos (1U)
5238 #define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
5239 #define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */
5240 
5241 /***************** Bit definition for USB_ADDR7_RX register *****************/
5242 #define USB_ADDR7_RX_ADDR7_RX_Pos (1U)
5243 #define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
5244 #define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */
5245 
5246 /*----------------------------------------------------------------------------*/
5247 
5248 /***************** Bit definition for USB_COUNT0_RX register ****************/
5249 #define USB_COUNT0_RX_COUNT0_RX_Pos (0U)
5250 #define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
5251 #define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */
5252 
5253 #define USB_COUNT0_RX_NUM_BLOCK_Pos (10U)
5254 #define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5255 #define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5256 #define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5257 #define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5258 #define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5259 #define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5260 #define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5261 
5262 #define USB_COUNT0_RX_BLSIZE_Pos (15U)
5263 #define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
5264 #define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */
5265 
5266 /***************** Bit definition for USB_COUNT1_RX register ****************/
5267 #define USB_COUNT1_RX_COUNT1_RX_Pos (0U)
5268 #define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
5269 #define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */
5270 
5271 #define USB_COUNT1_RX_NUM_BLOCK_Pos (10U)
5272 #define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5273 #define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5274 #define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5275 #define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5276 #define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5277 #define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5278 #define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5279 
5280 #define USB_COUNT1_RX_BLSIZE_Pos (15U)
5281 #define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
5282 #define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */
5283 
5284 /***************** Bit definition for USB_COUNT2_RX register ****************/
5285 #define USB_COUNT2_RX_COUNT2_RX_Pos (0U)
5286 #define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
5287 #define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */
5288 
5289 #define USB_COUNT2_RX_NUM_BLOCK_Pos (10U)
5290 #define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5291 #define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5292 #define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5293 #define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5294 #define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5295 #define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5296 #define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5297 
5298 #define USB_COUNT2_RX_BLSIZE_Pos (15U)
5299 #define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
5300 #define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */
5301 
5302 /***************** Bit definition for USB_COUNT3_RX register ****************/
5303 #define USB_COUNT3_RX_COUNT3_RX_Pos (0U)
5304 #define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
5305 #define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */
5306 
5307 #define USB_COUNT3_RX_NUM_BLOCK_Pos (10U)
5308 #define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5309 #define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5310 #define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5311 #define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5312 #define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5313 #define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5314 #define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5315 
5316 #define USB_COUNT3_RX_BLSIZE_Pos (15U)
5317 #define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
5318 #define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */
5319 
5320 /***************** Bit definition for USB_COUNT4_RX register ****************/
5321 #define USB_COUNT4_RX_COUNT4_RX_Pos (0U)
5322 #define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
5323 #define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */
5324 
5325 #define USB_COUNT4_RX_NUM_BLOCK_Pos (10U)
5326 #define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5327 #define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5328 #define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5329 #define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5330 #define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5331 #define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5332 #define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5333 
5334 #define USB_COUNT4_RX_BLSIZE_Pos (15U)
5335 #define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
5336 #define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */
5337 
5338 /***************** Bit definition for USB_COUNT5_RX register ****************/
5339 #define USB_COUNT5_RX_COUNT5_RX_Pos (0U)
5340 #define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
5341 #define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */
5342 
5343 #define USB_COUNT5_RX_NUM_BLOCK_Pos (10U)
5344 #define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5345 #define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5346 #define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5347 #define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5348 #define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5349 #define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5350 #define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5351 
5352 #define USB_COUNT5_RX_BLSIZE_Pos (15U)
5353 #define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
5354 #define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */
5355 
5356 /***************** Bit definition for USB_COUNT6_RX register ****************/
5357 #define USB_COUNT6_RX_COUNT6_RX_Pos (0U)
5358 #define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
5359 #define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */
5360 
5361 #define USB_COUNT6_RX_NUM_BLOCK_Pos (10U)
5362 #define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5363 #define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5364 #define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5365 #define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5366 #define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5367 #define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5368 #define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5369 
5370 #define USB_COUNT6_RX_BLSIZE_Pos (15U)
5371 #define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
5372 #define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */
5373 
5374 /***************** Bit definition for USB_COUNT7_RX register ****************/
5375 #define USB_COUNT7_RX_COUNT7_RX_Pos (0U)
5376 #define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
5377 #define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */
5378 
5379 #define USB_COUNT7_RX_NUM_BLOCK_Pos (10U)
5380 #define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
5381 #define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
5382 #define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
5383 #define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
5384 #define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
5385 #define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
5386 #define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
5387 
5388 #define USB_COUNT7_RX_BLSIZE_Pos (15U)
5389 #define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
5390 #define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */
5391 
5392 /*----------------------------------------------------------------------------*/
5393 
5394 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
5395 #define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5396 
5397 #define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5398 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5399 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5400 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5401 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5402 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5403 
5404 #define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5405 
5406 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
5407 #define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5408 
5409 #define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5410 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */
5411 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5412 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5413 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5414 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5415 
5416 #define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5417 
5418 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
5419 #define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5420 
5421 #define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5422 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5423 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5424 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5425 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5426 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5427 
5428 #define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5429 
5430 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
5431 #define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5432 
5433 #define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5434 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5435 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5436 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5437 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5438 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5439 
5440 #define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5441 
5442 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
5443 #define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5444 
5445 #define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5446 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5447 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5448 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5449 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5450 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5451 
5452 #define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5453 
5454 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
5455 #define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5456 
5457 #define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5458 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5459 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5460 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5461 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5462 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5463 
5464 #define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5465 
5466 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
5467 #define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5468 
5469 #define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5470 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5471 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5472 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5473 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5474 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5475 
5476 #define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5477 
5478 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
5479 #define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5480 
5481 #define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5482 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5483 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5484 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5485 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5486 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5487 
5488 #define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5489 
5490 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
5491 #define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5492 
5493 #define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5494 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5495 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5496 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5497 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5498 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5499 
5500 #define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5501 
5502 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
5503 #define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5504 
5505 #define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5506 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5507 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5508 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5509 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5510 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5511 
5512 #define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5513 
5514 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
5515 #define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5516 
5517 #define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5518 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5519 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5520 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5521 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5522 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5523 
5524 #define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5525 
5526 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
5527 #define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5528 
5529 #define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5530 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5531 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5532 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5533 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5534 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5535 
5536 #define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5537 
5538 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
5539 #define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5540 
5541 #define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5542 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5543 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5544 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5545 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5546 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5547 
5548 #define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5549 
5550 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
5551 #define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5552 
5553 #define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5554 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5555 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5556 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5557 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5558 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5559 
5560 #define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5561 
5562 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
5563 #define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */
5564 
5565 #define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
5566 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */
5567 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */
5568 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */
5569 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */
5570 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */
5571 
5572 #define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */
5573 
5574 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
5575 #define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */
5576 
5577 #define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
5578 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */
5579 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */
5580 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */
5581 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */
5582 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */
5583 
5584 #define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */
5585 
5586 /******************************************************************************/
5587 /* */
5588 /* Controller Area Network */
5589 /* */
5590 /******************************************************************************/
5591 
5592 /*!< CAN control and status registers */
5593 /******************* Bit definition for CAN_MCR register ********************/
5594 #define CAN_MCR_INRQ_Pos (0U)
5595 #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
5596 #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */
5597 #define CAN_MCR_SLEEP_Pos (1U)
5598 #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
5599 #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */
5600 #define CAN_MCR_TXFP_Pos (2U)
5601 #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
5602 #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */
5603 #define CAN_MCR_RFLM_Pos (3U)
5604 #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
5605 #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */
5606 #define CAN_MCR_NART_Pos (4U)
5607 #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
5608 #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */
5609 #define CAN_MCR_AWUM_Pos (5U)
5610 #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
5611 #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */
5612 #define CAN_MCR_ABOM_Pos (6U)
5613 #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
5614 #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */
5615 #define CAN_MCR_TTCM_Pos (7U)
5616 #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
5617 #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */
5618 #define CAN_MCR_RESET_Pos (15U)
5619 #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
5620 #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */
5621 #define CAN_MCR_DBF_Pos (16U)
5622 #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */
5623 #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */
5624 
5625 /******************* Bit definition for CAN_MSR register ********************/
5626 #define CAN_MSR_INAK_Pos (0U)
5627 #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
5628 #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */
5629 #define CAN_MSR_SLAK_Pos (1U)
5630 #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
5631 #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */
5632 #define CAN_MSR_ERRI_Pos (2U)
5633 #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
5634 #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */
5635 #define CAN_MSR_WKUI_Pos (3U)
5636 #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
5637 #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */
5638 #define CAN_MSR_SLAKI_Pos (4U)
5639 #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
5640 #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */
5641 #define CAN_MSR_TXM_Pos (8U)
5642 #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
5643 #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */
5644 #define CAN_MSR_RXM_Pos (9U)
5645 #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
5646 #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */
5647 #define CAN_MSR_SAMP_Pos (10U)
5648 #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
5649 #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */
5650 #define CAN_MSR_RX_Pos (11U)
5651 #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
5652 #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */
5653 
5654 /******************* Bit definition for CAN_TSR register ********************/
5655 #define CAN_TSR_RQCP0_Pos (0U)
5656 #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
5657 #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */
5658 #define CAN_TSR_TXOK0_Pos (1U)
5659 #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
5660 #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */
5661 #define CAN_TSR_ALST0_Pos (2U)
5662 #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
5663 #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */
5664 #define CAN_TSR_TERR0_Pos (3U)
5665 #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
5666 #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */
5667 #define CAN_TSR_ABRQ0_Pos (7U)
5668 #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
5669 #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */
5670 #define CAN_TSR_RQCP1_Pos (8U)
5671 #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
5672 #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */
5673 #define CAN_TSR_TXOK1_Pos (9U)
5674 #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
5675 #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */
5676 #define CAN_TSR_ALST1_Pos (10U)
5677 #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
5678 #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */
5679 #define CAN_TSR_TERR1_Pos (11U)
5680 #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
5681 #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */
5682 #define CAN_TSR_ABRQ1_Pos (15U)
5683 #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
5684 #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */
5685 #define CAN_TSR_RQCP2_Pos (16U)
5686 #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
5687 #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */
5688 #define CAN_TSR_TXOK2_Pos (17U)
5689 #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
5690 #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */
5691 #define CAN_TSR_ALST2_Pos (18U)
5692 #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
5693 #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */
5694 #define CAN_TSR_TERR2_Pos (19U)
5695 #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
5696 #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */
5697 #define CAN_TSR_ABRQ2_Pos (23U)
5698 #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
5699 #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */
5700 #define CAN_TSR_CODE_Pos (24U)
5701 #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
5702 #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */
5703 
5704 #define CAN_TSR_TME_Pos (26U)
5705 #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
5706 #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */
5707 #define CAN_TSR_TME0_Pos (26U)
5708 #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
5709 #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */
5710 #define CAN_TSR_TME1_Pos (27U)
5711 #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
5712 #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */
5713 #define CAN_TSR_TME2_Pos (28U)
5714 #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
5715 #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */
5716 
5717 #define CAN_TSR_LOW_Pos (29U)
5718 #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
5719 #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */
5720 #define CAN_TSR_LOW0_Pos (29U)
5721 #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
5722 #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */
5723 #define CAN_TSR_LOW1_Pos (30U)
5724 #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
5725 #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */
5726 #define CAN_TSR_LOW2_Pos (31U)
5727 #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
5728 #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */
5729 
5730 /******************* Bit definition for CAN_RF0R register *******************/
5731 #define CAN_RF0R_FMP0_Pos (0U)
5732 #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
5733 #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */
5734 #define CAN_RF0R_FULL0_Pos (3U)
5735 #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
5736 #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */
5737 #define CAN_RF0R_FOVR0_Pos (4U)
5738 #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
5739 #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */
5740 #define CAN_RF0R_RFOM0_Pos (5U)
5741 #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
5742 #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */
5743 
5744 /******************* Bit definition for CAN_RF1R register *******************/
5745 #define CAN_RF1R_FMP1_Pos (0U)
5746 #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
5747 #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */
5748 #define CAN_RF1R_FULL1_Pos (3U)
5749 #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
5750 #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */
5751 #define CAN_RF1R_FOVR1_Pos (4U)
5752 #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
5753 #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */
5754 #define CAN_RF1R_RFOM1_Pos (5U)
5755 #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
5756 #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */
5757 
5758 /******************** Bit definition for CAN_IER register *******************/
5759 #define CAN_IER_TMEIE_Pos (0U)
5760 #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
5761 #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */
5762 #define CAN_IER_FMPIE0_Pos (1U)
5763 #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
5764 #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */
5765 #define CAN_IER_FFIE0_Pos (2U)
5766 #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
5767 #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */
5768 #define CAN_IER_FOVIE0_Pos (3U)
5769 #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
5770 #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */
5771 #define CAN_IER_FMPIE1_Pos (4U)
5772 #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
5773 #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */
5774 #define CAN_IER_FFIE1_Pos (5U)
5775 #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
5776 #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */
5777 #define CAN_IER_FOVIE1_Pos (6U)
5778 #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
5779 #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */
5780 #define CAN_IER_EWGIE_Pos (8U)
5781 #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
5782 #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */
5783 #define CAN_IER_EPVIE_Pos (9U)
5784 #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
5785 #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */
5786 #define CAN_IER_BOFIE_Pos (10U)
5787 #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
5788 #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */
5789 #define CAN_IER_LECIE_Pos (11U)
5790 #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
5791 #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */
5792 #define CAN_IER_ERRIE_Pos (15U)
5793 #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
5794 #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */
5795 #define CAN_IER_WKUIE_Pos (16U)
5796 #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
5797 #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */
5798 #define CAN_IER_SLKIE_Pos (17U)
5799 #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
5800 #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */
5801 
5802 /******************** Bit definition for CAN_ESR register *******************/
5803 #define CAN_ESR_EWGF_Pos (0U)
5804 #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
5805 #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */
5806 #define CAN_ESR_EPVF_Pos (1U)
5807 #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
5808 #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */
5809 #define CAN_ESR_BOFF_Pos (2U)
5810 #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
5811 #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */
5812 
5813 #define CAN_ESR_LEC_Pos (4U)
5814 #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
5815 #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */
5816 #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
5817 #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
5818 #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
5819 
5820 #define CAN_ESR_TEC_Pos (16U)
5821 #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
5822 #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */
5823 #define CAN_ESR_REC_Pos (24U)
5824 #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
5825 #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */
5826 
5827 /******************* Bit definition for CAN_BTR register ********************/
5828 #define CAN_BTR_BRP_Pos (0U)
5829 #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
5830 #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
5831 #define CAN_BTR_TS1_Pos (16U)
5832 #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
5833 #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
5834 #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
5835 #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
5836 #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
5837 #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
5838 #define CAN_BTR_TS2_Pos (20U)
5839 #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
5840 #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
5841 #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
5842 #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
5843 #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
5844 #define CAN_BTR_SJW_Pos (24U)
5845 #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
5846 #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
5847 #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
5848 #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
5849 #define CAN_BTR_LBKM_Pos (30U)
5850 #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
5851 #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
5852 #define CAN_BTR_SILM_Pos (31U)
5853 #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
5854 #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
5855 
5856 /*!< Mailbox registers */
5857 /****************** Bit definition for CAN_TI0R register ********************/
5858 #define CAN_TI0R_TXRQ_Pos (0U)
5859 #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
5860 #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */
5861 #define CAN_TI0R_RTR_Pos (1U)
5862 #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
5863 #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */
5864 #define CAN_TI0R_IDE_Pos (2U)
5865 #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
5866 #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */
5867 #define CAN_TI0R_EXID_Pos (3U)
5868 #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
5869 #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */
5870 #define CAN_TI0R_STID_Pos (21U)
5871 #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
5872 #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
5873 
5874 /****************** Bit definition for CAN_TDT0R register *******************/
5875 #define CAN_TDT0R_DLC_Pos (0U)
5876 #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
5877 #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */
5878 #define CAN_TDT0R_TGT_Pos (8U)
5879 #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
5880 #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */
5881 #define CAN_TDT0R_TIME_Pos (16U)
5882 #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
5883 #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */
5884 
5885 /****************** Bit definition for CAN_TDL0R register *******************/
5886 #define CAN_TDL0R_DATA0_Pos (0U)
5887 #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
5888 #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */
5889 #define CAN_TDL0R_DATA1_Pos (8U)
5890 #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
5891 #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */
5892 #define CAN_TDL0R_DATA2_Pos (16U)
5893 #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
5894 #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */
5895 #define CAN_TDL0R_DATA3_Pos (24U)
5896 #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
5897 #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */
5898 
5899 /****************** Bit definition for CAN_TDH0R register *******************/
5900 #define CAN_TDH0R_DATA4_Pos (0U)
5901 #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
5902 #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */
5903 #define CAN_TDH0R_DATA5_Pos (8U)
5904 #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
5905 #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */
5906 #define CAN_TDH0R_DATA6_Pos (16U)
5907 #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
5908 #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */
5909 #define CAN_TDH0R_DATA7_Pos (24U)
5910 #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
5911 #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */
5912 
5913 /******************* Bit definition for CAN_TI1R register *******************/
5914 #define CAN_TI1R_TXRQ_Pos (0U)
5915 #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
5916 #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */
5917 #define CAN_TI1R_RTR_Pos (1U)
5918 #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
5919 #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */
5920 #define CAN_TI1R_IDE_Pos (2U)
5921 #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
5922 #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */
5923 #define CAN_TI1R_EXID_Pos (3U)
5924 #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
5925 #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */
5926 #define CAN_TI1R_STID_Pos (21U)
5927 #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
5928 #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
5929 
5930 /******************* Bit definition for CAN_TDT1R register ******************/
5931 #define CAN_TDT1R_DLC_Pos (0U)
5932 #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
5933 #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */
5934 #define CAN_TDT1R_TGT_Pos (8U)
5935 #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
5936 #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */
5937 #define CAN_TDT1R_TIME_Pos (16U)
5938 #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
5939 #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */
5940 
5941 /******************* Bit definition for CAN_TDL1R register ******************/
5942 #define CAN_TDL1R_DATA0_Pos (0U)
5943 #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
5944 #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */
5945 #define CAN_TDL1R_DATA1_Pos (8U)
5946 #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
5947 #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */
5948 #define CAN_TDL1R_DATA2_Pos (16U)
5949 #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
5950 #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */
5951 #define CAN_TDL1R_DATA3_Pos (24U)
5952 #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
5953 #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */
5954 
5955 /******************* Bit definition for CAN_TDH1R register ******************/
5956 #define CAN_TDH1R_DATA4_Pos (0U)
5957 #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
5958 #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */
5959 #define CAN_TDH1R_DATA5_Pos (8U)
5960 #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
5961 #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */
5962 #define CAN_TDH1R_DATA6_Pos (16U)
5963 #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
5964 #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */
5965 #define CAN_TDH1R_DATA7_Pos (24U)
5966 #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
5967 #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */
5968 
5969 /******************* Bit definition for CAN_TI2R register *******************/
5970 #define CAN_TI2R_TXRQ_Pos (0U)
5971 #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
5972 #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */
5973 #define CAN_TI2R_RTR_Pos (1U)
5974 #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
5975 #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */
5976 #define CAN_TI2R_IDE_Pos (2U)
5977 #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
5978 #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */
5979 #define CAN_TI2R_EXID_Pos (3U)
5980 #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
5981 #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */
5982 #define CAN_TI2R_STID_Pos (21U)
5983 #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
5984 #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */
5985 
5986 /******************* Bit definition for CAN_TDT2R register ******************/
5987 #define CAN_TDT2R_DLC_Pos (0U)
5988 #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
5989 #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */
5990 #define CAN_TDT2R_TGT_Pos (8U)
5991 #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
5992 #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */
5993 #define CAN_TDT2R_TIME_Pos (16U)
5994 #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
5995 #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */
5996 
5997 /******************* Bit definition for CAN_TDL2R register ******************/
5998 #define CAN_TDL2R_DATA0_Pos (0U)
5999 #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
6000 #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */
6001 #define CAN_TDL2R_DATA1_Pos (8U)
6002 #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
6003 #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */
6004 #define CAN_TDL2R_DATA2_Pos (16U)
6005 #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
6006 #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */
6007 #define CAN_TDL2R_DATA3_Pos (24U)
6008 #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
6009 #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */
6010 
6011 /******************* Bit definition for CAN_TDH2R register ******************/
6012 #define CAN_TDH2R_DATA4_Pos (0U)
6013 #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
6014 #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */
6015 #define CAN_TDH2R_DATA5_Pos (8U)
6016 #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
6017 #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */
6018 #define CAN_TDH2R_DATA6_Pos (16U)
6019 #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
6020 #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */
6021 #define CAN_TDH2R_DATA7_Pos (24U)
6022 #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
6023 #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */
6024 
6025 /******************* Bit definition for CAN_RI0R register *******************/
6026 #define CAN_RI0R_RTR_Pos (1U)
6027 #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
6028 #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */
6029 #define CAN_RI0R_IDE_Pos (2U)
6030 #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
6031 #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */
6032 #define CAN_RI0R_EXID_Pos (3U)
6033 #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
6034 #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */
6035 #define CAN_RI0R_STID_Pos (21U)
6036 #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
6037 #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6038 
6039 /******************* Bit definition for CAN_RDT0R register ******************/
6040 #define CAN_RDT0R_DLC_Pos (0U)
6041 #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
6042 #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */
6043 #define CAN_RDT0R_FMI_Pos (8U)
6044 #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
6045 #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */
6046 #define CAN_RDT0R_TIME_Pos (16U)
6047 #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
6048 #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */
6049 
6050 /******************* Bit definition for CAN_RDL0R register ******************/
6051 #define CAN_RDL0R_DATA0_Pos (0U)
6052 #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
6053 #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */
6054 #define CAN_RDL0R_DATA1_Pos (8U)
6055 #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
6056 #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */
6057 #define CAN_RDL0R_DATA2_Pos (16U)
6058 #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
6059 #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */
6060 #define CAN_RDL0R_DATA3_Pos (24U)
6061 #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
6062 #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */
6063 
6064 /******************* Bit definition for CAN_RDH0R register ******************/
6065 #define CAN_RDH0R_DATA4_Pos (0U)
6066 #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
6067 #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */
6068 #define CAN_RDH0R_DATA5_Pos (8U)
6069 #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
6070 #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */
6071 #define CAN_RDH0R_DATA6_Pos (16U)
6072 #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
6073 #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */
6074 #define CAN_RDH0R_DATA7_Pos (24U)
6075 #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
6076 #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */
6077 
6078 /******************* Bit definition for CAN_RI1R register *******************/
6079 #define CAN_RI1R_RTR_Pos (1U)
6080 #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
6081 #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */
6082 #define CAN_RI1R_IDE_Pos (2U)
6083 #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
6084 #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */
6085 #define CAN_RI1R_EXID_Pos (3U)
6086 #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
6087 #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */
6088 #define CAN_RI1R_STID_Pos (21U)
6089 #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
6090 #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */
6091 
6092 /******************* Bit definition for CAN_RDT1R register ******************/
6093 #define CAN_RDT1R_DLC_Pos (0U)
6094 #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
6095 #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */
6096 #define CAN_RDT1R_FMI_Pos (8U)
6097 #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
6098 #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */
6099 #define CAN_RDT1R_TIME_Pos (16U)
6100 #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
6101 #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */
6102 
6103 /******************* Bit definition for CAN_RDL1R register ******************/
6104 #define CAN_RDL1R_DATA0_Pos (0U)
6105 #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
6106 #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */
6107 #define CAN_RDL1R_DATA1_Pos (8U)
6108 #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
6109 #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */
6110 #define CAN_RDL1R_DATA2_Pos (16U)
6111 #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
6112 #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */
6113 #define CAN_RDL1R_DATA3_Pos (24U)
6114 #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
6115 #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */
6116 
6117 /******************* Bit definition for CAN_RDH1R register ******************/
6118 #define CAN_RDH1R_DATA4_Pos (0U)
6119 #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
6120 #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */
6121 #define CAN_RDH1R_DATA5_Pos (8U)
6122 #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
6123 #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */
6124 #define CAN_RDH1R_DATA6_Pos (16U)
6125 #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
6126 #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */
6127 #define CAN_RDH1R_DATA7_Pos (24U)
6128 #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
6129 #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */
6130 
6131 /*!< CAN filter registers */
6132 /******************* Bit definition for CAN_FMR register ********************/
6133 #define CAN_FMR_FINIT_Pos (0U)
6134 #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
6135 #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */
6136 #define CAN_FMR_CAN2SB_Pos (8U)
6137 #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */
6138 #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */
6139 
6140 /******************* Bit definition for CAN_FM1R register *******************/
6141 #define CAN_FM1R_FBM_Pos (0U)
6142 #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
6143 #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */
6144 #define CAN_FM1R_FBM0_Pos (0U)
6145 #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
6146 #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */
6147 #define CAN_FM1R_FBM1_Pos (1U)
6148 #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
6149 #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */
6150 #define CAN_FM1R_FBM2_Pos (2U)
6151 #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
6152 #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */
6153 #define CAN_FM1R_FBM3_Pos (3U)
6154 #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
6155 #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */
6156 #define CAN_FM1R_FBM4_Pos (4U)
6157 #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
6158 #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */
6159 #define CAN_FM1R_FBM5_Pos (5U)
6160 #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
6161 #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */
6162 #define CAN_FM1R_FBM6_Pos (6U)
6163 #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
6164 #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */
6165 #define CAN_FM1R_FBM7_Pos (7U)
6166 #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
6167 #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */
6168 #define CAN_FM1R_FBM8_Pos (8U)
6169 #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
6170 #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */
6171 #define CAN_FM1R_FBM9_Pos (9U)
6172 #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
6173 #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */
6174 #define CAN_FM1R_FBM10_Pos (10U)
6175 #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
6176 #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */
6177 #define CAN_FM1R_FBM11_Pos (11U)
6178 #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
6179 #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */
6180 #define CAN_FM1R_FBM12_Pos (12U)
6181 #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
6182 #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */
6183 #define CAN_FM1R_FBM13_Pos (13U)
6184 #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
6185 #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */
6186 
6187 /******************* Bit definition for CAN_FS1R register *******************/
6188 #define CAN_FS1R_FSC_Pos (0U)
6189 #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
6190 #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */
6191 #define CAN_FS1R_FSC0_Pos (0U)
6192 #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
6193 #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */
6194 #define CAN_FS1R_FSC1_Pos (1U)
6195 #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
6196 #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */
6197 #define CAN_FS1R_FSC2_Pos (2U)
6198 #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
6199 #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */
6200 #define CAN_FS1R_FSC3_Pos (3U)
6201 #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
6202 #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */
6203 #define CAN_FS1R_FSC4_Pos (4U)
6204 #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
6205 #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */
6206 #define CAN_FS1R_FSC5_Pos (5U)
6207 #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
6208 #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */
6209 #define CAN_FS1R_FSC6_Pos (6U)
6210 #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
6211 #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */
6212 #define CAN_FS1R_FSC7_Pos (7U)
6213 #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
6214 #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */
6215 #define CAN_FS1R_FSC8_Pos (8U)
6216 #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
6217 #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */
6218 #define CAN_FS1R_FSC9_Pos (9U)
6219 #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
6220 #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */
6221 #define CAN_FS1R_FSC10_Pos (10U)
6222 #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
6223 #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */
6224 #define CAN_FS1R_FSC11_Pos (11U)
6225 #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
6226 #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */
6227 #define CAN_FS1R_FSC12_Pos (12U)
6228 #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
6229 #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */
6230 #define CAN_FS1R_FSC13_Pos (13U)
6231 #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
6232 #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */
6233 
6234 /****************** Bit definition for CAN_FFA1R register *******************/
6235 #define CAN_FFA1R_FFA_Pos (0U)
6236 #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
6237 #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */
6238 #define CAN_FFA1R_FFA0_Pos (0U)
6239 #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
6240 #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */
6241 #define CAN_FFA1R_FFA1_Pos (1U)
6242 #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
6243 #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */
6244 #define CAN_FFA1R_FFA2_Pos (2U)
6245 #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
6246 #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */
6247 #define CAN_FFA1R_FFA3_Pos (3U)
6248 #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
6249 #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */
6250 #define CAN_FFA1R_FFA4_Pos (4U)
6251 #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
6252 #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */
6253 #define CAN_FFA1R_FFA5_Pos (5U)
6254 #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
6255 #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */
6256 #define CAN_FFA1R_FFA6_Pos (6U)
6257 #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
6258 #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */
6259 #define CAN_FFA1R_FFA7_Pos (7U)
6260 #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
6261 #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */
6262 #define CAN_FFA1R_FFA8_Pos (8U)
6263 #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
6264 #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */
6265 #define CAN_FFA1R_FFA9_Pos (9U)
6266 #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
6267 #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */
6268 #define CAN_FFA1R_FFA10_Pos (10U)
6269 #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
6270 #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */
6271 #define CAN_FFA1R_FFA11_Pos (11U)
6272 #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
6273 #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */
6274 #define CAN_FFA1R_FFA12_Pos (12U)
6275 #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
6276 #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */
6277 #define CAN_FFA1R_FFA13_Pos (13U)
6278 #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
6279 #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */
6280 
6281 /******************* Bit definition for CAN_FA1R register *******************/
6282 #define CAN_FA1R_FACT_Pos (0U)
6283 #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
6284 #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */
6285 #define CAN_FA1R_FACT0_Pos (0U)
6286 #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
6287 #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */
6288 #define CAN_FA1R_FACT1_Pos (1U)
6289 #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
6290 #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */
6291 #define CAN_FA1R_FACT2_Pos (2U)
6292 #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
6293 #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */
6294 #define CAN_FA1R_FACT3_Pos (3U)
6295 #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
6296 #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */
6297 #define CAN_FA1R_FACT4_Pos (4U)
6298 #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
6299 #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */
6300 #define CAN_FA1R_FACT5_Pos (5U)
6301 #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
6302 #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */
6303 #define CAN_FA1R_FACT6_Pos (6U)
6304 #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
6305 #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */
6306 #define CAN_FA1R_FACT7_Pos (7U)
6307 #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
6308 #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */
6309 #define CAN_FA1R_FACT8_Pos (8U)
6310 #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
6311 #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */
6312 #define CAN_FA1R_FACT9_Pos (9U)
6313 #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
6314 #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */
6315 #define CAN_FA1R_FACT10_Pos (10U)
6316 #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
6317 #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */
6318 #define CAN_FA1R_FACT11_Pos (11U)
6319 #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
6320 #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */
6321 #define CAN_FA1R_FACT12_Pos (12U)
6322 #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
6323 #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */
6324 #define CAN_FA1R_FACT13_Pos (13U)
6325 #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
6326 #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */
6327 
6328 /******************* Bit definition for CAN_F0R1 register *******************/
6329 #define CAN_F0R1_FB0_Pos (0U)
6330 #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
6331 #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */
6332 #define CAN_F0R1_FB1_Pos (1U)
6333 #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
6334 #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */
6335 #define CAN_F0R1_FB2_Pos (2U)
6336 #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
6337 #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */
6338 #define CAN_F0R1_FB3_Pos (3U)
6339 #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
6340 #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */
6341 #define CAN_F0R1_FB4_Pos (4U)
6342 #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
6343 #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */
6344 #define CAN_F0R1_FB5_Pos (5U)
6345 #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
6346 #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */
6347 #define CAN_F0R1_FB6_Pos (6U)
6348 #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
6349 #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */
6350 #define CAN_F0R1_FB7_Pos (7U)
6351 #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
6352 #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */
6353 #define CAN_F0R1_FB8_Pos (8U)
6354 #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
6355 #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */
6356 #define CAN_F0R1_FB9_Pos (9U)
6357 #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
6358 #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */
6359 #define CAN_F0R1_FB10_Pos (10U)
6360 #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
6361 #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */
6362 #define CAN_F0R1_FB11_Pos (11U)
6363 #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
6364 #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */
6365 #define CAN_F0R1_FB12_Pos (12U)
6366 #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
6367 #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */
6368 #define CAN_F0R1_FB13_Pos (13U)
6369 #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
6370 #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */
6371 #define CAN_F0R1_FB14_Pos (14U)
6372 #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
6373 #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */
6374 #define CAN_F0R1_FB15_Pos (15U)
6375 #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
6376 #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */
6377 #define CAN_F0R1_FB16_Pos (16U)
6378 #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
6379 #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */
6380 #define CAN_F0R1_FB17_Pos (17U)
6381 #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
6382 #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */
6383 #define CAN_F0R1_FB18_Pos (18U)
6384 #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
6385 #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */
6386 #define CAN_F0R1_FB19_Pos (19U)
6387 #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
6388 #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */
6389 #define CAN_F0R1_FB20_Pos (20U)
6390 #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
6391 #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */
6392 #define CAN_F0R1_FB21_Pos (21U)
6393 #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
6394 #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */
6395 #define CAN_F0R1_FB22_Pos (22U)
6396 #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
6397 #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */
6398 #define CAN_F0R1_FB23_Pos (23U)
6399 #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
6400 #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */
6401 #define CAN_F0R1_FB24_Pos (24U)
6402 #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
6403 #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */
6404 #define CAN_F0R1_FB25_Pos (25U)
6405 #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
6406 #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */
6407 #define CAN_F0R1_FB26_Pos (26U)
6408 #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
6409 #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */
6410 #define CAN_F0R1_FB27_Pos (27U)
6411 #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
6412 #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */
6413 #define CAN_F0R1_FB28_Pos (28U)
6414 #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
6415 #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */
6416 #define CAN_F0R1_FB29_Pos (29U)
6417 #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
6418 #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */
6419 #define CAN_F0R1_FB30_Pos (30U)
6420 #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
6421 #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */
6422 #define CAN_F0R1_FB31_Pos (31U)
6423 #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
6424 #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */
6425 
6426 /******************* Bit definition for CAN_F1R1 register *******************/
6427 #define CAN_F1R1_FB0_Pos (0U)
6428 #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
6429 #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */
6430 #define CAN_F1R1_FB1_Pos (1U)
6431 #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
6432 #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */
6433 #define CAN_F1R1_FB2_Pos (2U)
6434 #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
6435 #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */
6436 #define CAN_F1R1_FB3_Pos (3U)
6437 #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
6438 #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */
6439 #define CAN_F1R1_FB4_Pos (4U)
6440 #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
6441 #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */
6442 #define CAN_F1R1_FB5_Pos (5U)
6443 #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
6444 #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */
6445 #define CAN_F1R1_FB6_Pos (6U)
6446 #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
6447 #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */
6448 #define CAN_F1R1_FB7_Pos (7U)
6449 #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
6450 #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */
6451 #define CAN_F1R1_FB8_Pos (8U)
6452 #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
6453 #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */
6454 #define CAN_F1R1_FB9_Pos (9U)
6455 #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
6456 #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */
6457 #define CAN_F1R1_FB10_Pos (10U)
6458 #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
6459 #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */
6460 #define CAN_F1R1_FB11_Pos (11U)
6461 #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
6462 #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */
6463 #define CAN_F1R1_FB12_Pos (12U)
6464 #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
6465 #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */
6466 #define CAN_F1R1_FB13_Pos (13U)
6467 #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
6468 #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */
6469 #define CAN_F1R1_FB14_Pos (14U)
6470 #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
6471 #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */
6472 #define CAN_F1R1_FB15_Pos (15U)
6473 #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
6474 #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */
6475 #define CAN_F1R1_FB16_Pos (16U)
6476 #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
6477 #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */
6478 #define CAN_F1R1_FB17_Pos (17U)
6479 #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
6480 #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */
6481 #define CAN_F1R1_FB18_Pos (18U)
6482 #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
6483 #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */
6484 #define CAN_F1R1_FB19_Pos (19U)
6485 #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
6486 #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */
6487 #define CAN_F1R1_FB20_Pos (20U)
6488 #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
6489 #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */
6490 #define CAN_F1R1_FB21_Pos (21U)
6491 #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
6492 #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */
6493 #define CAN_F1R1_FB22_Pos (22U)
6494 #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
6495 #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */
6496 #define CAN_F1R1_FB23_Pos (23U)
6497 #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
6498 #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */
6499 #define CAN_F1R1_FB24_Pos (24U)
6500 #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
6501 #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */
6502 #define CAN_F1R1_FB25_Pos (25U)
6503 #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
6504 #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */
6505 #define CAN_F1R1_FB26_Pos (26U)
6506 #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
6507 #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */
6508 #define CAN_F1R1_FB27_Pos (27U)
6509 #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
6510 #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */
6511 #define CAN_F1R1_FB28_Pos (28U)
6512 #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
6513 #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */
6514 #define CAN_F1R1_FB29_Pos (29U)
6515 #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
6516 #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */
6517 #define CAN_F1R1_FB30_Pos (30U)
6518 #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
6519 #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */
6520 #define CAN_F1R1_FB31_Pos (31U)
6521 #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
6522 #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */
6523 
6524 /******************* Bit definition for CAN_F2R1 register *******************/
6525 #define CAN_F2R1_FB0_Pos (0U)
6526 #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
6527 #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */
6528 #define CAN_F2R1_FB1_Pos (1U)
6529 #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
6530 #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */
6531 #define CAN_F2R1_FB2_Pos (2U)
6532 #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
6533 #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */
6534 #define CAN_F2R1_FB3_Pos (3U)
6535 #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
6536 #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */
6537 #define CAN_F2R1_FB4_Pos (4U)
6538 #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
6539 #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */
6540 #define CAN_F2R1_FB5_Pos (5U)
6541 #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
6542 #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */
6543 #define CAN_F2R1_FB6_Pos (6U)
6544 #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
6545 #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */
6546 #define CAN_F2R1_FB7_Pos (7U)
6547 #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
6548 #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */
6549 #define CAN_F2R1_FB8_Pos (8U)
6550 #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
6551 #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */
6552 #define CAN_F2R1_FB9_Pos (9U)
6553 #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
6554 #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */
6555 #define CAN_F2R1_FB10_Pos (10U)
6556 #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
6557 #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */
6558 #define CAN_F2R1_FB11_Pos (11U)
6559 #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
6560 #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */
6561 #define CAN_F2R1_FB12_Pos (12U)
6562 #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
6563 #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */
6564 #define CAN_F2R1_FB13_Pos (13U)
6565 #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
6566 #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */
6567 #define CAN_F2R1_FB14_Pos (14U)
6568 #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
6569 #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */
6570 #define CAN_F2R1_FB15_Pos (15U)
6571 #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
6572 #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */
6573 #define CAN_F2R1_FB16_Pos (16U)
6574 #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
6575 #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */
6576 #define CAN_F2R1_FB17_Pos (17U)
6577 #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
6578 #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */
6579 #define CAN_F2R1_FB18_Pos (18U)
6580 #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
6581 #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */
6582 #define CAN_F2R1_FB19_Pos (19U)
6583 #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
6584 #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */
6585 #define CAN_F2R1_FB20_Pos (20U)
6586 #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
6587 #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */
6588 #define CAN_F2R1_FB21_Pos (21U)
6589 #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
6590 #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */
6591 #define CAN_F2R1_FB22_Pos (22U)
6592 #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
6593 #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */
6594 #define CAN_F2R1_FB23_Pos (23U)
6595 #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
6596 #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */
6597 #define CAN_F2R1_FB24_Pos (24U)
6598 #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
6599 #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */
6600 #define CAN_F2R1_FB25_Pos (25U)
6601 #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
6602 #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */
6603 #define CAN_F2R1_FB26_Pos (26U)
6604 #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
6605 #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */
6606 #define CAN_F2R1_FB27_Pos (27U)
6607 #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
6608 #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */
6609 #define CAN_F2R1_FB28_Pos (28U)
6610 #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
6611 #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */
6612 #define CAN_F2R1_FB29_Pos (29U)
6613 #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
6614 #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */
6615 #define CAN_F2R1_FB30_Pos (30U)
6616 #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
6617 #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */
6618 #define CAN_F2R1_FB31_Pos (31U)
6619 #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
6620 #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */
6621 
6622 /******************* Bit definition for CAN_F3R1 register *******************/
6623 #define CAN_F3R1_FB0_Pos (0U)
6624 #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
6625 #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */
6626 #define CAN_F3R1_FB1_Pos (1U)
6627 #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
6628 #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */
6629 #define CAN_F3R1_FB2_Pos (2U)
6630 #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
6631 #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */
6632 #define CAN_F3R1_FB3_Pos (3U)
6633 #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
6634 #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */
6635 #define CAN_F3R1_FB4_Pos (4U)
6636 #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
6637 #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */
6638 #define CAN_F3R1_FB5_Pos (5U)
6639 #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
6640 #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */
6641 #define CAN_F3R1_FB6_Pos (6U)
6642 #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
6643 #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */
6644 #define CAN_F3R1_FB7_Pos (7U)
6645 #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
6646 #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */
6647 #define CAN_F3R1_FB8_Pos (8U)
6648 #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
6649 #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */
6650 #define CAN_F3R1_FB9_Pos (9U)
6651 #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
6652 #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */
6653 #define CAN_F3R1_FB10_Pos (10U)
6654 #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
6655 #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */
6656 #define CAN_F3R1_FB11_Pos (11U)
6657 #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
6658 #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */
6659 #define CAN_F3R1_FB12_Pos (12U)
6660 #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
6661 #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */
6662 #define CAN_F3R1_FB13_Pos (13U)
6663 #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
6664 #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */
6665 #define CAN_F3R1_FB14_Pos (14U)
6666 #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
6667 #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */
6668 #define CAN_F3R1_FB15_Pos (15U)
6669 #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
6670 #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */
6671 #define CAN_F3R1_FB16_Pos (16U)
6672 #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
6673 #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */
6674 #define CAN_F3R1_FB17_Pos (17U)
6675 #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
6676 #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */
6677 #define CAN_F3R1_FB18_Pos (18U)
6678 #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
6679 #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */
6680 #define CAN_F3R1_FB19_Pos (19U)
6681 #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
6682 #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */
6683 #define CAN_F3R1_FB20_Pos (20U)
6684 #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
6685 #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */
6686 #define CAN_F3R1_FB21_Pos (21U)
6687 #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
6688 #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */
6689 #define CAN_F3R1_FB22_Pos (22U)
6690 #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
6691 #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */
6692 #define CAN_F3R1_FB23_Pos (23U)
6693 #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
6694 #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */
6695 #define CAN_F3R1_FB24_Pos (24U)
6696 #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
6697 #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */
6698 #define CAN_F3R1_FB25_Pos (25U)
6699 #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
6700 #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */
6701 #define CAN_F3R1_FB26_Pos (26U)
6702 #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
6703 #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */
6704 #define CAN_F3R1_FB27_Pos (27U)
6705 #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
6706 #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */
6707 #define CAN_F3R1_FB28_Pos (28U)
6708 #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
6709 #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */
6710 #define CAN_F3R1_FB29_Pos (29U)
6711 #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
6712 #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */
6713 #define CAN_F3R1_FB30_Pos (30U)
6714 #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
6715 #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */
6716 #define CAN_F3R1_FB31_Pos (31U)
6717 #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
6718 #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */
6719 
6720 /******************* Bit definition for CAN_F4R1 register *******************/
6721 #define CAN_F4R1_FB0_Pos (0U)
6722 #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
6723 #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */
6724 #define CAN_F4R1_FB1_Pos (1U)
6725 #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
6726 #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */
6727 #define CAN_F4R1_FB2_Pos (2U)
6728 #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
6729 #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */
6730 #define CAN_F4R1_FB3_Pos (3U)
6731 #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
6732 #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */
6733 #define CAN_F4R1_FB4_Pos (4U)
6734 #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
6735 #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */
6736 #define CAN_F4R1_FB5_Pos (5U)
6737 #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
6738 #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */
6739 #define CAN_F4R1_FB6_Pos (6U)
6740 #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
6741 #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */
6742 #define CAN_F4R1_FB7_Pos (7U)
6743 #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
6744 #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */
6745 #define CAN_F4R1_FB8_Pos (8U)
6746 #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
6747 #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */
6748 #define CAN_F4R1_FB9_Pos (9U)
6749 #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
6750 #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */
6751 #define CAN_F4R1_FB10_Pos (10U)
6752 #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
6753 #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */
6754 #define CAN_F4R1_FB11_Pos (11U)
6755 #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
6756 #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */
6757 #define CAN_F4R1_FB12_Pos (12U)
6758 #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
6759 #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */
6760 #define CAN_F4R1_FB13_Pos (13U)
6761 #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
6762 #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */
6763 #define CAN_F4R1_FB14_Pos (14U)
6764 #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
6765 #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */
6766 #define CAN_F4R1_FB15_Pos (15U)
6767 #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
6768 #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */
6769 #define CAN_F4R1_FB16_Pos (16U)
6770 #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
6771 #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */
6772 #define CAN_F4R1_FB17_Pos (17U)
6773 #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
6774 #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */
6775 #define CAN_F4R1_FB18_Pos (18U)
6776 #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
6777 #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */
6778 #define CAN_F4R1_FB19_Pos (19U)
6779 #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
6780 #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */
6781 #define CAN_F4R1_FB20_Pos (20U)
6782 #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
6783 #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */
6784 #define CAN_F4R1_FB21_Pos (21U)
6785 #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
6786 #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */
6787 #define CAN_F4R1_FB22_Pos (22U)
6788 #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
6789 #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */
6790 #define CAN_F4R1_FB23_Pos (23U)
6791 #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
6792 #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */
6793 #define CAN_F4R1_FB24_Pos (24U)
6794 #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
6795 #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */
6796 #define CAN_F4R1_FB25_Pos (25U)
6797 #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
6798 #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */
6799 #define CAN_F4R1_FB26_Pos (26U)
6800 #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
6801 #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */
6802 #define CAN_F4R1_FB27_Pos (27U)
6803 #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
6804 #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */
6805 #define CAN_F4R1_FB28_Pos (28U)
6806 #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
6807 #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */
6808 #define CAN_F4R1_FB29_Pos (29U)
6809 #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
6810 #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */
6811 #define CAN_F4R1_FB30_Pos (30U)
6812 #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
6813 #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */
6814 #define CAN_F4R1_FB31_Pos (31U)
6815 #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
6816 #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */
6817 
6818 /******************* Bit definition for CAN_F5R1 register *******************/
6819 #define CAN_F5R1_FB0_Pos (0U)
6820 #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
6821 #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */
6822 #define CAN_F5R1_FB1_Pos (1U)
6823 #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
6824 #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */
6825 #define CAN_F5R1_FB2_Pos (2U)
6826 #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
6827 #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */
6828 #define CAN_F5R1_FB3_Pos (3U)
6829 #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
6830 #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */
6831 #define CAN_F5R1_FB4_Pos (4U)
6832 #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
6833 #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */
6834 #define CAN_F5R1_FB5_Pos (5U)
6835 #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
6836 #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */
6837 #define CAN_F5R1_FB6_Pos (6U)
6838 #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
6839 #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */
6840 #define CAN_F5R1_FB7_Pos (7U)
6841 #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
6842 #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */
6843 #define CAN_F5R1_FB8_Pos (8U)
6844 #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
6845 #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */
6846 #define CAN_F5R1_FB9_Pos (9U)
6847 #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
6848 #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */
6849 #define CAN_F5R1_FB10_Pos (10U)
6850 #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
6851 #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */
6852 #define CAN_F5R1_FB11_Pos (11U)
6853 #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
6854 #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */
6855 #define CAN_F5R1_FB12_Pos (12U)
6856 #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
6857 #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */
6858 #define CAN_F5R1_FB13_Pos (13U)
6859 #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
6860 #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */
6861 #define CAN_F5R1_FB14_Pos (14U)
6862 #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
6863 #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */
6864 #define CAN_F5R1_FB15_Pos (15U)
6865 #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
6866 #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */
6867 #define CAN_F5R1_FB16_Pos (16U)
6868 #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
6869 #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */
6870 #define CAN_F5R1_FB17_Pos (17U)
6871 #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
6872 #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */
6873 #define CAN_F5R1_FB18_Pos (18U)
6874 #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
6875 #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */
6876 #define CAN_F5R1_FB19_Pos (19U)
6877 #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
6878 #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */
6879 #define CAN_F5R1_FB20_Pos (20U)
6880 #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
6881 #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */
6882 #define CAN_F5R1_FB21_Pos (21U)
6883 #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
6884 #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */
6885 #define CAN_F5R1_FB22_Pos (22U)
6886 #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
6887 #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */
6888 #define CAN_F5R1_FB23_Pos (23U)
6889 #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
6890 #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */
6891 #define CAN_F5R1_FB24_Pos (24U)
6892 #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
6893 #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */
6894 #define CAN_F5R1_FB25_Pos (25U)
6895 #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
6896 #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */
6897 #define CAN_F5R1_FB26_Pos (26U)
6898 #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
6899 #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */
6900 #define CAN_F5R1_FB27_Pos (27U)
6901 #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
6902 #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */
6903 #define CAN_F5R1_FB28_Pos (28U)
6904 #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
6905 #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */
6906 #define CAN_F5R1_FB29_Pos (29U)
6907 #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
6908 #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */
6909 #define CAN_F5R1_FB30_Pos (30U)
6910 #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
6911 #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */
6912 #define CAN_F5R1_FB31_Pos (31U)
6913 #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
6914 #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */
6915 
6916 /******************* Bit definition for CAN_F6R1 register *******************/
6917 #define CAN_F6R1_FB0_Pos (0U)
6918 #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
6919 #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */
6920 #define CAN_F6R1_FB1_Pos (1U)
6921 #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
6922 #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */
6923 #define CAN_F6R1_FB2_Pos (2U)
6924 #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
6925 #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */
6926 #define CAN_F6R1_FB3_Pos (3U)
6927 #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
6928 #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */
6929 #define CAN_F6R1_FB4_Pos (4U)
6930 #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
6931 #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */
6932 #define CAN_F6R1_FB5_Pos (5U)
6933 #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
6934 #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */
6935 #define CAN_F6R1_FB6_Pos (6U)
6936 #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
6937 #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */
6938 #define CAN_F6R1_FB7_Pos (7U)
6939 #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
6940 #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */
6941 #define CAN_F6R1_FB8_Pos (8U)
6942 #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
6943 #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */
6944 #define CAN_F6R1_FB9_Pos (9U)
6945 #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
6946 #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */
6947 #define CAN_F6R1_FB10_Pos (10U)
6948 #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
6949 #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */
6950 #define CAN_F6R1_FB11_Pos (11U)
6951 #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
6952 #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */
6953 #define CAN_F6R1_FB12_Pos (12U)
6954 #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
6955 #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */
6956 #define CAN_F6R1_FB13_Pos (13U)
6957 #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
6958 #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */
6959 #define CAN_F6R1_FB14_Pos (14U)
6960 #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
6961 #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */
6962 #define CAN_F6R1_FB15_Pos (15U)
6963 #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
6964 #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */
6965 #define CAN_F6R1_FB16_Pos (16U)
6966 #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
6967 #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */
6968 #define CAN_F6R1_FB17_Pos (17U)
6969 #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
6970 #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */
6971 #define CAN_F6R1_FB18_Pos (18U)
6972 #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
6973 #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */
6974 #define CAN_F6R1_FB19_Pos (19U)
6975 #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
6976 #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */
6977 #define CAN_F6R1_FB20_Pos (20U)
6978 #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
6979 #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */
6980 #define CAN_F6R1_FB21_Pos (21U)
6981 #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
6982 #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */
6983 #define CAN_F6R1_FB22_Pos (22U)
6984 #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
6985 #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */
6986 #define CAN_F6R1_FB23_Pos (23U)
6987 #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
6988 #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */
6989 #define CAN_F6R1_FB24_Pos (24U)
6990 #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
6991 #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */
6992 #define CAN_F6R1_FB25_Pos (25U)
6993 #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
6994 #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */
6995 #define CAN_F6R1_FB26_Pos (26U)
6996 #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
6997 #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */
6998 #define CAN_F6R1_FB27_Pos (27U)
6999 #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
7000 #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */
7001 #define CAN_F6R1_FB28_Pos (28U)
7002 #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
7003 #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */
7004 #define CAN_F6R1_FB29_Pos (29U)
7005 #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
7006 #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */
7007 #define CAN_F6R1_FB30_Pos (30U)
7008 #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
7009 #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */
7010 #define CAN_F6R1_FB31_Pos (31U)
7011 #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
7012 #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */
7013 
7014 /******************* Bit definition for CAN_F7R1 register *******************/
7015 #define CAN_F7R1_FB0_Pos (0U)
7016 #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
7017 #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */
7018 #define CAN_F7R1_FB1_Pos (1U)
7019 #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
7020 #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */
7021 #define CAN_F7R1_FB2_Pos (2U)
7022 #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
7023 #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */
7024 #define CAN_F7R1_FB3_Pos (3U)
7025 #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
7026 #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */
7027 #define CAN_F7R1_FB4_Pos (4U)
7028 #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
7029 #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */
7030 #define CAN_F7R1_FB5_Pos (5U)
7031 #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
7032 #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */
7033 #define CAN_F7R1_FB6_Pos (6U)
7034 #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
7035 #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */
7036 #define CAN_F7R1_FB7_Pos (7U)
7037 #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
7038 #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */
7039 #define CAN_F7R1_FB8_Pos (8U)
7040 #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
7041 #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */
7042 #define CAN_F7R1_FB9_Pos (9U)
7043 #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
7044 #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */
7045 #define CAN_F7R1_FB10_Pos (10U)
7046 #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
7047 #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */
7048 #define CAN_F7R1_FB11_Pos (11U)
7049 #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
7050 #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */
7051 #define CAN_F7R1_FB12_Pos (12U)
7052 #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
7053 #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */
7054 #define CAN_F7R1_FB13_Pos (13U)
7055 #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
7056 #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */
7057 #define CAN_F7R1_FB14_Pos (14U)
7058 #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
7059 #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */
7060 #define CAN_F7R1_FB15_Pos (15U)
7061 #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
7062 #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */
7063 #define CAN_F7R1_FB16_Pos (16U)
7064 #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
7065 #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */
7066 #define CAN_F7R1_FB17_Pos (17U)
7067 #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
7068 #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */
7069 #define CAN_F7R1_FB18_Pos (18U)
7070 #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
7071 #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */
7072 #define CAN_F7R1_FB19_Pos (19U)
7073 #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
7074 #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */
7075 #define CAN_F7R1_FB20_Pos (20U)
7076 #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
7077 #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */
7078 #define CAN_F7R1_FB21_Pos (21U)
7079 #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
7080 #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */
7081 #define CAN_F7R1_FB22_Pos (22U)
7082 #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
7083 #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */
7084 #define CAN_F7R1_FB23_Pos (23U)
7085 #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
7086 #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */
7087 #define CAN_F7R1_FB24_Pos (24U)
7088 #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
7089 #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */
7090 #define CAN_F7R1_FB25_Pos (25U)
7091 #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
7092 #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */
7093 #define CAN_F7R1_FB26_Pos (26U)
7094 #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
7095 #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */
7096 #define CAN_F7R1_FB27_Pos (27U)
7097 #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
7098 #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */
7099 #define CAN_F7R1_FB28_Pos (28U)
7100 #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
7101 #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */
7102 #define CAN_F7R1_FB29_Pos (29U)
7103 #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
7104 #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */
7105 #define CAN_F7R1_FB30_Pos (30U)
7106 #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
7107 #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */
7108 #define CAN_F7R1_FB31_Pos (31U)
7109 #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
7110 #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */
7111 
7112 /******************* Bit definition for CAN_F8R1 register *******************/
7113 #define CAN_F8R1_FB0_Pos (0U)
7114 #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
7115 #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */
7116 #define CAN_F8R1_FB1_Pos (1U)
7117 #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
7118 #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */
7119 #define CAN_F8R1_FB2_Pos (2U)
7120 #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
7121 #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */
7122 #define CAN_F8R1_FB3_Pos (3U)
7123 #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
7124 #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */
7125 #define CAN_F8R1_FB4_Pos (4U)
7126 #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
7127 #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */
7128 #define CAN_F8R1_FB5_Pos (5U)
7129 #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
7130 #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */
7131 #define CAN_F8R1_FB6_Pos (6U)
7132 #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
7133 #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */
7134 #define CAN_F8R1_FB7_Pos (7U)
7135 #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
7136 #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */
7137 #define CAN_F8R1_FB8_Pos (8U)
7138 #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
7139 #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */
7140 #define CAN_F8R1_FB9_Pos (9U)
7141 #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
7142 #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */
7143 #define CAN_F8R1_FB10_Pos (10U)
7144 #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
7145 #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */
7146 #define CAN_F8R1_FB11_Pos (11U)
7147 #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
7148 #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */
7149 #define CAN_F8R1_FB12_Pos (12U)
7150 #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
7151 #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */
7152 #define CAN_F8R1_FB13_Pos (13U)
7153 #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
7154 #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */
7155 #define CAN_F8R1_FB14_Pos (14U)
7156 #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
7157 #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */
7158 #define CAN_F8R1_FB15_Pos (15U)
7159 #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
7160 #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */
7161 #define CAN_F8R1_FB16_Pos (16U)
7162 #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
7163 #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */
7164 #define CAN_F8R1_FB17_Pos (17U)
7165 #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
7166 #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */
7167 #define CAN_F8R1_FB18_Pos (18U)
7168 #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
7169 #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */
7170 #define CAN_F8R1_FB19_Pos (19U)
7171 #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
7172 #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */
7173 #define CAN_F8R1_FB20_Pos (20U)
7174 #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
7175 #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */
7176 #define CAN_F8R1_FB21_Pos (21U)
7177 #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
7178 #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */
7179 #define CAN_F8R1_FB22_Pos (22U)
7180 #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
7181 #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */
7182 #define CAN_F8R1_FB23_Pos (23U)
7183 #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
7184 #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */
7185 #define CAN_F8R1_FB24_Pos (24U)
7186 #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
7187 #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */
7188 #define CAN_F8R1_FB25_Pos (25U)
7189 #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
7190 #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */
7191 #define CAN_F8R1_FB26_Pos (26U)
7192 #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
7193 #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */
7194 #define CAN_F8R1_FB27_Pos (27U)
7195 #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
7196 #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */
7197 #define CAN_F8R1_FB28_Pos (28U)
7198 #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
7199 #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */
7200 #define CAN_F8R1_FB29_Pos (29U)
7201 #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
7202 #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */
7203 #define CAN_F8R1_FB30_Pos (30U)
7204 #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
7205 #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */
7206 #define CAN_F8R1_FB31_Pos (31U)
7207 #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
7208 #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */
7209 
7210 /******************* Bit definition for CAN_F9R1 register *******************/
7211 #define CAN_F9R1_FB0_Pos (0U)
7212 #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
7213 #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */
7214 #define CAN_F9R1_FB1_Pos (1U)
7215 #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
7216 #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */
7217 #define CAN_F9R1_FB2_Pos (2U)
7218 #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
7219 #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */
7220 #define CAN_F9R1_FB3_Pos (3U)
7221 #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
7222 #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */
7223 #define CAN_F9R1_FB4_Pos (4U)
7224 #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
7225 #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */
7226 #define CAN_F9R1_FB5_Pos (5U)
7227 #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
7228 #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */
7229 #define CAN_F9R1_FB6_Pos (6U)
7230 #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
7231 #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */
7232 #define CAN_F9R1_FB7_Pos (7U)
7233 #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
7234 #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */
7235 #define CAN_F9R1_FB8_Pos (8U)
7236 #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
7237 #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */
7238 #define CAN_F9R1_FB9_Pos (9U)
7239 #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
7240 #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */
7241 #define CAN_F9R1_FB10_Pos (10U)
7242 #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
7243 #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */
7244 #define CAN_F9R1_FB11_Pos (11U)
7245 #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
7246 #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */
7247 #define CAN_F9R1_FB12_Pos (12U)
7248 #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
7249 #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */
7250 #define CAN_F9R1_FB13_Pos (13U)
7251 #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
7252 #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */
7253 #define CAN_F9R1_FB14_Pos (14U)
7254 #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
7255 #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */
7256 #define CAN_F9R1_FB15_Pos (15U)
7257 #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
7258 #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */
7259 #define CAN_F9R1_FB16_Pos (16U)
7260 #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
7261 #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */
7262 #define CAN_F9R1_FB17_Pos (17U)
7263 #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
7264 #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */
7265 #define CAN_F9R1_FB18_Pos (18U)
7266 #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
7267 #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */
7268 #define CAN_F9R1_FB19_Pos (19U)
7269 #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
7270 #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */
7271 #define CAN_F9R1_FB20_Pos (20U)
7272 #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
7273 #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */
7274 #define CAN_F9R1_FB21_Pos (21U)
7275 #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
7276 #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */
7277 #define CAN_F9R1_FB22_Pos (22U)
7278 #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
7279 #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */
7280 #define CAN_F9R1_FB23_Pos (23U)
7281 #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
7282 #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */
7283 #define CAN_F9R1_FB24_Pos (24U)
7284 #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
7285 #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */
7286 #define CAN_F9R1_FB25_Pos (25U)
7287 #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
7288 #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */
7289 #define CAN_F9R1_FB26_Pos (26U)
7290 #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
7291 #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */
7292 #define CAN_F9R1_FB27_Pos (27U)
7293 #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
7294 #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */
7295 #define CAN_F9R1_FB28_Pos (28U)
7296 #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
7297 #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */
7298 #define CAN_F9R1_FB29_Pos (29U)
7299 #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
7300 #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */
7301 #define CAN_F9R1_FB30_Pos (30U)
7302 #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
7303 #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */
7304 #define CAN_F9R1_FB31_Pos (31U)
7305 #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
7306 #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */
7307 
7308 /******************* Bit definition for CAN_F10R1 register ******************/
7309 #define CAN_F10R1_FB0_Pos (0U)
7310 #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
7311 #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */
7312 #define CAN_F10R1_FB1_Pos (1U)
7313 #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
7314 #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */
7315 #define CAN_F10R1_FB2_Pos (2U)
7316 #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
7317 #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */
7318 #define CAN_F10R1_FB3_Pos (3U)
7319 #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
7320 #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */
7321 #define CAN_F10R1_FB4_Pos (4U)
7322 #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
7323 #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */
7324 #define CAN_F10R1_FB5_Pos (5U)
7325 #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
7326 #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */
7327 #define CAN_F10R1_FB6_Pos (6U)
7328 #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
7329 #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */
7330 #define CAN_F10R1_FB7_Pos (7U)
7331 #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
7332 #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */
7333 #define CAN_F10R1_FB8_Pos (8U)
7334 #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
7335 #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */
7336 #define CAN_F10R1_FB9_Pos (9U)
7337 #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
7338 #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */
7339 #define CAN_F10R1_FB10_Pos (10U)
7340 #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
7341 #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */
7342 #define CAN_F10R1_FB11_Pos (11U)
7343 #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
7344 #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */
7345 #define CAN_F10R1_FB12_Pos (12U)
7346 #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
7347 #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */
7348 #define CAN_F10R1_FB13_Pos (13U)
7349 #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
7350 #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */
7351 #define CAN_F10R1_FB14_Pos (14U)
7352 #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
7353 #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */
7354 #define CAN_F10R1_FB15_Pos (15U)
7355 #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
7356 #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */
7357 #define CAN_F10R1_FB16_Pos (16U)
7358 #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
7359 #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */
7360 #define CAN_F10R1_FB17_Pos (17U)
7361 #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
7362 #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */
7363 #define CAN_F10R1_FB18_Pos (18U)
7364 #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
7365 #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */
7366 #define CAN_F10R1_FB19_Pos (19U)
7367 #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
7368 #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */
7369 #define CAN_F10R1_FB20_Pos (20U)
7370 #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
7371 #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */
7372 #define CAN_F10R1_FB21_Pos (21U)
7373 #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
7374 #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */
7375 #define CAN_F10R1_FB22_Pos (22U)
7376 #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
7377 #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */
7378 #define CAN_F10R1_FB23_Pos (23U)
7379 #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
7380 #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */
7381 #define CAN_F10R1_FB24_Pos (24U)
7382 #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
7383 #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */
7384 #define CAN_F10R1_FB25_Pos (25U)
7385 #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
7386 #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */
7387 #define CAN_F10R1_FB26_Pos (26U)
7388 #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
7389 #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */
7390 #define CAN_F10R1_FB27_Pos (27U)
7391 #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
7392 #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */
7393 #define CAN_F10R1_FB28_Pos (28U)
7394 #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
7395 #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */
7396 #define CAN_F10R1_FB29_Pos (29U)
7397 #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
7398 #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */
7399 #define CAN_F10R1_FB30_Pos (30U)
7400 #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
7401 #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */
7402 #define CAN_F10R1_FB31_Pos (31U)
7403 #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
7404 #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */
7405 
7406 /******************* Bit definition for CAN_F11R1 register ******************/
7407 #define CAN_F11R1_FB0_Pos (0U)
7408 #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
7409 #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */
7410 #define CAN_F11R1_FB1_Pos (1U)
7411 #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
7412 #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */
7413 #define CAN_F11R1_FB2_Pos (2U)
7414 #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
7415 #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */
7416 #define CAN_F11R1_FB3_Pos (3U)
7417 #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
7418 #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */
7419 #define CAN_F11R1_FB4_Pos (4U)
7420 #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
7421 #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */
7422 #define CAN_F11R1_FB5_Pos (5U)
7423 #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
7424 #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */
7425 #define CAN_F11R1_FB6_Pos (6U)
7426 #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
7427 #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */
7428 #define CAN_F11R1_FB7_Pos (7U)
7429 #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
7430 #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */
7431 #define CAN_F11R1_FB8_Pos (8U)
7432 #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
7433 #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */
7434 #define CAN_F11R1_FB9_Pos (9U)
7435 #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
7436 #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */
7437 #define CAN_F11R1_FB10_Pos (10U)
7438 #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
7439 #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */
7440 #define CAN_F11R1_FB11_Pos (11U)
7441 #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
7442 #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */
7443 #define CAN_F11R1_FB12_Pos (12U)
7444 #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
7445 #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */
7446 #define CAN_F11R1_FB13_Pos (13U)
7447 #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
7448 #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */
7449 #define CAN_F11R1_FB14_Pos (14U)
7450 #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
7451 #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */
7452 #define CAN_F11R1_FB15_Pos (15U)
7453 #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
7454 #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */
7455 #define CAN_F11R1_FB16_Pos (16U)
7456 #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
7457 #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */
7458 #define CAN_F11R1_FB17_Pos (17U)
7459 #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
7460 #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */
7461 #define CAN_F11R1_FB18_Pos (18U)
7462 #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
7463 #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */
7464 #define CAN_F11R1_FB19_Pos (19U)
7465 #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
7466 #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */
7467 #define CAN_F11R1_FB20_Pos (20U)
7468 #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
7469 #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */
7470 #define CAN_F11R1_FB21_Pos (21U)
7471 #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
7472 #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */
7473 #define CAN_F11R1_FB22_Pos (22U)
7474 #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
7475 #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */
7476 #define CAN_F11R1_FB23_Pos (23U)
7477 #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
7478 #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */
7479 #define CAN_F11R1_FB24_Pos (24U)
7480 #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
7481 #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */
7482 #define CAN_F11R1_FB25_Pos (25U)
7483 #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
7484 #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */
7485 #define CAN_F11R1_FB26_Pos (26U)
7486 #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
7487 #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */
7488 #define CAN_F11R1_FB27_Pos (27U)
7489 #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
7490 #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */
7491 #define CAN_F11R1_FB28_Pos (28U)
7492 #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
7493 #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */
7494 #define CAN_F11R1_FB29_Pos (29U)
7495 #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
7496 #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */
7497 #define CAN_F11R1_FB30_Pos (30U)
7498 #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
7499 #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */
7500 #define CAN_F11R1_FB31_Pos (31U)
7501 #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
7502 #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */
7503 
7504 /******************* Bit definition for CAN_F12R1 register ******************/
7505 #define CAN_F12R1_FB0_Pos (0U)
7506 #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
7507 #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */
7508 #define CAN_F12R1_FB1_Pos (1U)
7509 #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
7510 #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */
7511 #define CAN_F12R1_FB2_Pos (2U)
7512 #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
7513 #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */
7514 #define CAN_F12R1_FB3_Pos (3U)
7515 #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
7516 #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */
7517 #define CAN_F12R1_FB4_Pos (4U)
7518 #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
7519 #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */
7520 #define CAN_F12R1_FB5_Pos (5U)
7521 #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
7522 #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */
7523 #define CAN_F12R1_FB6_Pos (6U)
7524 #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
7525 #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */
7526 #define CAN_F12R1_FB7_Pos (7U)
7527 #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
7528 #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */
7529 #define CAN_F12R1_FB8_Pos (8U)
7530 #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
7531 #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */
7532 #define CAN_F12R1_FB9_Pos (9U)
7533 #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
7534 #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */
7535 #define CAN_F12R1_FB10_Pos (10U)
7536 #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
7537 #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */
7538 #define CAN_F12R1_FB11_Pos (11U)
7539 #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
7540 #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */
7541 #define CAN_F12R1_FB12_Pos (12U)
7542 #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
7543 #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */
7544 #define CAN_F12R1_FB13_Pos (13U)
7545 #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
7546 #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */
7547 #define CAN_F12R1_FB14_Pos (14U)
7548 #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
7549 #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */
7550 #define CAN_F12R1_FB15_Pos (15U)
7551 #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
7552 #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */
7553 #define CAN_F12R1_FB16_Pos (16U)
7554 #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
7555 #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */
7556 #define CAN_F12R1_FB17_Pos (17U)
7557 #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
7558 #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */
7559 #define CAN_F12R1_FB18_Pos (18U)
7560 #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
7561 #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */
7562 #define CAN_F12R1_FB19_Pos (19U)
7563 #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
7564 #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */
7565 #define CAN_F12R1_FB20_Pos (20U)
7566 #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
7567 #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */
7568 #define CAN_F12R1_FB21_Pos (21U)
7569 #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
7570 #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */
7571 #define CAN_F12R1_FB22_Pos (22U)
7572 #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
7573 #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */
7574 #define CAN_F12R1_FB23_Pos (23U)
7575 #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
7576 #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */
7577 #define CAN_F12R1_FB24_Pos (24U)
7578 #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
7579 #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */
7580 #define CAN_F12R1_FB25_Pos (25U)
7581 #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
7582 #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */
7583 #define CAN_F12R1_FB26_Pos (26U)
7584 #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
7585 #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */
7586 #define CAN_F12R1_FB27_Pos (27U)
7587 #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
7588 #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */
7589 #define CAN_F12R1_FB28_Pos (28U)
7590 #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
7591 #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */
7592 #define CAN_F12R1_FB29_Pos (29U)
7593 #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
7594 #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */
7595 #define CAN_F12R1_FB30_Pos (30U)
7596 #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
7597 #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */
7598 #define CAN_F12R1_FB31_Pos (31U)
7599 #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
7600 #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */
7601 
7602 /******************* Bit definition for CAN_F13R1 register ******************/
7603 #define CAN_F13R1_FB0_Pos (0U)
7604 #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
7605 #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */
7606 #define CAN_F13R1_FB1_Pos (1U)
7607 #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
7608 #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */
7609 #define CAN_F13R1_FB2_Pos (2U)
7610 #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
7611 #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */
7612 #define CAN_F13R1_FB3_Pos (3U)
7613 #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
7614 #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */
7615 #define CAN_F13R1_FB4_Pos (4U)
7616 #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
7617 #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */
7618 #define CAN_F13R1_FB5_Pos (5U)
7619 #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
7620 #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */
7621 #define CAN_F13R1_FB6_Pos (6U)
7622 #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
7623 #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */
7624 #define CAN_F13R1_FB7_Pos (7U)
7625 #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
7626 #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */
7627 #define CAN_F13R1_FB8_Pos (8U)
7628 #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
7629 #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */
7630 #define CAN_F13R1_FB9_Pos (9U)
7631 #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
7632 #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */
7633 #define CAN_F13R1_FB10_Pos (10U)
7634 #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
7635 #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */
7636 #define CAN_F13R1_FB11_Pos (11U)
7637 #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
7638 #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */
7639 #define CAN_F13R1_FB12_Pos (12U)
7640 #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
7641 #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */
7642 #define CAN_F13R1_FB13_Pos (13U)
7643 #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
7644 #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */
7645 #define CAN_F13R1_FB14_Pos (14U)
7646 #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
7647 #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */
7648 #define CAN_F13R1_FB15_Pos (15U)
7649 #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
7650 #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */
7651 #define CAN_F13R1_FB16_Pos (16U)
7652 #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
7653 #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */
7654 #define CAN_F13R1_FB17_Pos (17U)
7655 #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
7656 #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */
7657 #define CAN_F13R1_FB18_Pos (18U)
7658 #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
7659 #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */
7660 #define CAN_F13R1_FB19_Pos (19U)
7661 #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
7662 #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */
7663 #define CAN_F13R1_FB20_Pos (20U)
7664 #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
7665 #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */
7666 #define CAN_F13R1_FB21_Pos (21U)
7667 #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
7668 #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */
7669 #define CAN_F13R1_FB22_Pos (22U)
7670 #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
7671 #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */
7672 #define CAN_F13R1_FB23_Pos (23U)
7673 #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
7674 #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */
7675 #define CAN_F13R1_FB24_Pos (24U)
7676 #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
7677 #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */
7678 #define CAN_F13R1_FB25_Pos (25U)
7679 #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
7680 #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */
7681 #define CAN_F13R1_FB26_Pos (26U)
7682 #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
7683 #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */
7684 #define CAN_F13R1_FB27_Pos (27U)
7685 #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
7686 #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */
7687 #define CAN_F13R1_FB28_Pos (28U)
7688 #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
7689 #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */
7690 #define CAN_F13R1_FB29_Pos (29U)
7691 #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
7692 #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */
7693 #define CAN_F13R1_FB30_Pos (30U)
7694 #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */
7695 #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */
7696 #define CAN_F13R1_FB31_Pos (31U)
7697 #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */
7698 #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */
7699 
7700 /******************* Bit definition for CAN_F0R2 register *******************/
7701 #define CAN_F0R2_FB0_Pos (0U)
7702 #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */
7703 #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */
7704 #define CAN_F0R2_FB1_Pos (1U)
7705 #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */
7706 #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */
7707 #define CAN_F0R2_FB2_Pos (2U)
7708 #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */
7709 #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */
7710 #define CAN_F0R2_FB3_Pos (3U)
7711 #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */
7712 #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */
7713 #define CAN_F0R2_FB4_Pos (4U)
7714 #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */
7715 #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */
7716 #define CAN_F0R2_FB5_Pos (5U)
7717 #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */
7718 #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */
7719 #define CAN_F0R2_FB6_Pos (6U)
7720 #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */
7721 #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */
7722 #define CAN_F0R2_FB7_Pos (7U)
7723 #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */
7724 #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */
7725 #define CAN_F0R2_FB8_Pos (8U)
7726 #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */
7727 #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */
7728 #define CAN_F0R2_FB9_Pos (9U)
7729 #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */
7730 #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */
7731 #define CAN_F0R2_FB10_Pos (10U)
7732 #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */
7733 #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */
7734 #define CAN_F0R2_FB11_Pos (11U)
7735 #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */
7736 #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */
7737 #define CAN_F0R2_FB12_Pos (12U)
7738 #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */
7739 #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */
7740 #define CAN_F0R2_FB13_Pos (13U)
7741 #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */
7742 #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */
7743 #define CAN_F0R2_FB14_Pos (14U)
7744 #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */
7745 #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */
7746 #define CAN_F0R2_FB15_Pos (15U)
7747 #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */
7748 #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */
7749 #define CAN_F0R2_FB16_Pos (16U)
7750 #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */
7751 #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */
7752 #define CAN_F0R2_FB17_Pos (17U)
7753 #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */
7754 #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */
7755 #define CAN_F0R2_FB18_Pos (18U)
7756 #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */
7757 #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */
7758 #define CAN_F0R2_FB19_Pos (19U)
7759 #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */
7760 #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */
7761 #define CAN_F0R2_FB20_Pos (20U)
7762 #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */
7763 #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */
7764 #define CAN_F0R2_FB21_Pos (21U)
7765 #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */
7766 #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */
7767 #define CAN_F0R2_FB22_Pos (22U)
7768 #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */
7769 #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */
7770 #define CAN_F0R2_FB23_Pos (23U)
7771 #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */
7772 #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */
7773 #define CAN_F0R2_FB24_Pos (24U)
7774 #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */
7775 #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */
7776 #define CAN_F0R2_FB25_Pos (25U)
7777 #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */
7778 #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */
7779 #define CAN_F0R2_FB26_Pos (26U)
7780 #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */
7781 #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */
7782 #define CAN_F0R2_FB27_Pos (27U)
7783 #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */
7784 #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */
7785 #define CAN_F0R2_FB28_Pos (28U)
7786 #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */
7787 #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */
7788 #define CAN_F0R2_FB29_Pos (29U)
7789 #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */
7790 #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */
7791 #define CAN_F0R2_FB30_Pos (30U)
7792 #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */
7793 #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */
7794 #define CAN_F0R2_FB31_Pos (31U)
7795 #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */
7796 #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */
7797 
7798 /******************* Bit definition for CAN_F1R2 register *******************/
7799 #define CAN_F1R2_FB0_Pos (0U)
7800 #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */
7801 #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */
7802 #define CAN_F1R2_FB1_Pos (1U)
7803 #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */
7804 #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */
7805 #define CAN_F1R2_FB2_Pos (2U)
7806 #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */
7807 #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */
7808 #define CAN_F1R2_FB3_Pos (3U)
7809 #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */
7810 #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */
7811 #define CAN_F1R2_FB4_Pos (4U)
7812 #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */
7813 #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */
7814 #define CAN_F1R2_FB5_Pos (5U)
7815 #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */
7816 #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */
7817 #define CAN_F1R2_FB6_Pos (6U)
7818 #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */
7819 #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */
7820 #define CAN_F1R2_FB7_Pos (7U)
7821 #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */
7822 #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */
7823 #define CAN_F1R2_FB8_Pos (8U)
7824 #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */
7825 #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */
7826 #define CAN_F1R2_FB9_Pos (9U)
7827 #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */
7828 #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */
7829 #define CAN_F1R2_FB10_Pos (10U)
7830 #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */
7831 #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */
7832 #define CAN_F1R2_FB11_Pos (11U)
7833 #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */
7834 #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */
7835 #define CAN_F1R2_FB12_Pos (12U)
7836 #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */
7837 #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */
7838 #define CAN_F1R2_FB13_Pos (13U)
7839 #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */
7840 #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */
7841 #define CAN_F1R2_FB14_Pos (14U)
7842 #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */
7843 #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */
7844 #define CAN_F1R2_FB15_Pos (15U)
7845 #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */
7846 #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */
7847 #define CAN_F1R2_FB16_Pos (16U)
7848 #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */
7849 #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */
7850 #define CAN_F1R2_FB17_Pos (17U)
7851 #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */
7852 #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */
7853 #define CAN_F1R2_FB18_Pos (18U)
7854 #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */
7855 #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */
7856 #define CAN_F1R2_FB19_Pos (19U)
7857 #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */
7858 #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */
7859 #define CAN_F1R2_FB20_Pos (20U)
7860 #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */
7861 #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */
7862 #define CAN_F1R2_FB21_Pos (21U)
7863 #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */
7864 #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */
7865 #define CAN_F1R2_FB22_Pos (22U)
7866 #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */
7867 #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */
7868 #define CAN_F1R2_FB23_Pos (23U)
7869 #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */
7870 #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */
7871 #define CAN_F1R2_FB24_Pos (24U)
7872 #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */
7873 #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */
7874 #define CAN_F1R2_FB25_Pos (25U)
7875 #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */
7876 #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */
7877 #define CAN_F1R2_FB26_Pos (26U)
7878 #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */
7879 #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */
7880 #define CAN_F1R2_FB27_Pos (27U)
7881 #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */
7882 #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */
7883 #define CAN_F1R2_FB28_Pos (28U)
7884 #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */
7885 #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */
7886 #define CAN_F1R2_FB29_Pos (29U)
7887 #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */
7888 #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */
7889 #define CAN_F1R2_FB30_Pos (30U)
7890 #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */
7891 #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */
7892 #define CAN_F1R2_FB31_Pos (31U)
7893 #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */
7894 #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */
7895 
7896 /******************* Bit definition for CAN_F2R2 register *******************/
7897 #define CAN_F2R2_FB0_Pos (0U)
7898 #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */
7899 #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */
7900 #define CAN_F2R2_FB1_Pos (1U)
7901 #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */
7902 #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */
7903 #define CAN_F2R2_FB2_Pos (2U)
7904 #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */
7905 #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */
7906 #define CAN_F2R2_FB3_Pos (3U)
7907 #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */
7908 #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */
7909 #define CAN_F2R2_FB4_Pos (4U)
7910 #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */
7911 #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */
7912 #define CAN_F2R2_FB5_Pos (5U)
7913 #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */
7914 #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */
7915 #define CAN_F2R2_FB6_Pos (6U)
7916 #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */
7917 #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */
7918 #define CAN_F2R2_FB7_Pos (7U)
7919 #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */
7920 #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */
7921 #define CAN_F2R2_FB8_Pos (8U)
7922 #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */
7923 #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */
7924 #define CAN_F2R2_FB9_Pos (9U)
7925 #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */
7926 #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */
7927 #define CAN_F2R2_FB10_Pos (10U)
7928 #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */
7929 #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */
7930 #define CAN_F2R2_FB11_Pos (11U)
7931 #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */
7932 #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */
7933 #define CAN_F2R2_FB12_Pos (12U)
7934 #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */
7935 #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */
7936 #define CAN_F2R2_FB13_Pos (13U)
7937 #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */
7938 #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */
7939 #define CAN_F2R2_FB14_Pos (14U)
7940 #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */
7941 #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */
7942 #define CAN_F2R2_FB15_Pos (15U)
7943 #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */
7944 #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */
7945 #define CAN_F2R2_FB16_Pos (16U)
7946 #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */
7947 #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */
7948 #define CAN_F2R2_FB17_Pos (17U)
7949 #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */
7950 #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */
7951 #define CAN_F2R2_FB18_Pos (18U)
7952 #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */
7953 #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */
7954 #define CAN_F2R2_FB19_Pos (19U)
7955 #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */
7956 #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */
7957 #define CAN_F2R2_FB20_Pos (20U)
7958 #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */
7959 #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */
7960 #define CAN_F2R2_FB21_Pos (21U)
7961 #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */
7962 #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */
7963 #define CAN_F2R2_FB22_Pos (22U)
7964 #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */
7965 #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */
7966 #define CAN_F2R2_FB23_Pos (23U)
7967 #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */
7968 #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */
7969 #define CAN_F2R2_FB24_Pos (24U)
7970 #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */
7971 #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */
7972 #define CAN_F2R2_FB25_Pos (25U)
7973 #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */
7974 #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */
7975 #define CAN_F2R2_FB26_Pos (26U)
7976 #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */
7977 #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */
7978 #define CAN_F2R2_FB27_Pos (27U)
7979 #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */
7980 #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */
7981 #define CAN_F2R2_FB28_Pos (28U)
7982 #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */
7983 #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */
7984 #define CAN_F2R2_FB29_Pos (29U)
7985 #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */
7986 #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */
7987 #define CAN_F2R2_FB30_Pos (30U)
7988 #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */
7989 #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */
7990 #define CAN_F2R2_FB31_Pos (31U)
7991 #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */
7992 #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */
7993 
7994 /******************* Bit definition for CAN_F3R2 register *******************/
7995 #define CAN_F3R2_FB0_Pos (0U)
7996 #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */
7997 #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */
7998 #define CAN_F3R2_FB1_Pos (1U)
7999 #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */
8000 #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */
8001 #define CAN_F3R2_FB2_Pos (2U)
8002 #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */
8003 #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */
8004 #define CAN_F3R2_FB3_Pos (3U)
8005 #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */
8006 #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */
8007 #define CAN_F3R2_FB4_Pos (4U)
8008 #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */
8009 #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */
8010 #define CAN_F3R2_FB5_Pos (5U)
8011 #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */
8012 #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */
8013 #define CAN_F3R2_FB6_Pos (6U)
8014 #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */
8015 #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */
8016 #define CAN_F3R2_FB7_Pos (7U)
8017 #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */
8018 #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */
8019 #define CAN_F3R2_FB8_Pos (8U)
8020 #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */
8021 #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */
8022 #define CAN_F3R2_FB9_Pos (9U)
8023 #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */
8024 #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */
8025 #define CAN_F3R2_FB10_Pos (10U)
8026 #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */
8027 #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */
8028 #define CAN_F3R2_FB11_Pos (11U)
8029 #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */
8030 #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */
8031 #define CAN_F3R2_FB12_Pos (12U)
8032 #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */
8033 #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */
8034 #define CAN_F3R2_FB13_Pos (13U)
8035 #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */
8036 #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */
8037 #define CAN_F3R2_FB14_Pos (14U)
8038 #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */
8039 #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */
8040 #define CAN_F3R2_FB15_Pos (15U)
8041 #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */
8042 #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */
8043 #define CAN_F3R2_FB16_Pos (16U)
8044 #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */
8045 #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */
8046 #define CAN_F3R2_FB17_Pos (17U)
8047 #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */
8048 #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */
8049 #define CAN_F3R2_FB18_Pos (18U)
8050 #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */
8051 #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */
8052 #define CAN_F3R2_FB19_Pos (19U)
8053 #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */
8054 #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */
8055 #define CAN_F3R2_FB20_Pos (20U)
8056 #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */
8057 #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */
8058 #define CAN_F3R2_FB21_Pos (21U)
8059 #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */
8060 #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */
8061 #define CAN_F3R2_FB22_Pos (22U)
8062 #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */
8063 #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */
8064 #define CAN_F3R2_FB23_Pos (23U)
8065 #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */
8066 #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */
8067 #define CAN_F3R2_FB24_Pos (24U)
8068 #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */
8069 #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */
8070 #define CAN_F3R2_FB25_Pos (25U)
8071 #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */
8072 #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */
8073 #define CAN_F3R2_FB26_Pos (26U)
8074 #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */
8075 #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */
8076 #define CAN_F3R2_FB27_Pos (27U)
8077 #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */
8078 #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */
8079 #define CAN_F3R2_FB28_Pos (28U)
8080 #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */
8081 #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */
8082 #define CAN_F3R2_FB29_Pos (29U)
8083 #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */
8084 #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */
8085 #define CAN_F3R2_FB30_Pos (30U)
8086 #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */
8087 #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */
8088 #define CAN_F3R2_FB31_Pos (31U)
8089 #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */
8090 #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */
8091 
8092 /******************* Bit definition for CAN_F4R2 register *******************/
8093 #define CAN_F4R2_FB0_Pos (0U)
8094 #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */
8095 #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */
8096 #define CAN_F4R2_FB1_Pos (1U)
8097 #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */
8098 #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */
8099 #define CAN_F4R2_FB2_Pos (2U)
8100 #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */
8101 #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */
8102 #define CAN_F4R2_FB3_Pos (3U)
8103 #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */
8104 #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */
8105 #define CAN_F4R2_FB4_Pos (4U)
8106 #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */
8107 #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */
8108 #define CAN_F4R2_FB5_Pos (5U)
8109 #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */
8110 #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */
8111 #define CAN_F4R2_FB6_Pos (6U)
8112 #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */
8113 #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */
8114 #define CAN_F4R2_FB7_Pos (7U)
8115 #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */
8116 #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */
8117 #define CAN_F4R2_FB8_Pos (8U)
8118 #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */
8119 #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */
8120 #define CAN_F4R2_FB9_Pos (9U)
8121 #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */
8122 #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */
8123 #define CAN_F4R2_FB10_Pos (10U)
8124 #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */
8125 #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */
8126 #define CAN_F4R2_FB11_Pos (11U)
8127 #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */
8128 #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */
8129 #define CAN_F4R2_FB12_Pos (12U)
8130 #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */
8131 #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */
8132 #define CAN_F4R2_FB13_Pos (13U)
8133 #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */
8134 #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */
8135 #define CAN_F4R2_FB14_Pos (14U)
8136 #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */
8137 #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */
8138 #define CAN_F4R2_FB15_Pos (15U)
8139 #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */
8140 #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */
8141 #define CAN_F4R2_FB16_Pos (16U)
8142 #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */
8143 #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */
8144 #define CAN_F4R2_FB17_Pos (17U)
8145 #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */
8146 #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */
8147 #define CAN_F4R2_FB18_Pos (18U)
8148 #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */
8149 #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */
8150 #define CAN_F4R2_FB19_Pos (19U)
8151 #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */
8152 #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */
8153 #define CAN_F4R2_FB20_Pos (20U)
8154 #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */
8155 #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */
8156 #define CAN_F4R2_FB21_Pos (21U)
8157 #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */
8158 #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */
8159 #define CAN_F4R2_FB22_Pos (22U)
8160 #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */
8161 #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */
8162 #define CAN_F4R2_FB23_Pos (23U)
8163 #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */
8164 #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */
8165 #define CAN_F4R2_FB24_Pos (24U)
8166 #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */
8167 #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */
8168 #define CAN_F4R2_FB25_Pos (25U)
8169 #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */
8170 #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */
8171 #define CAN_F4R2_FB26_Pos (26U)
8172 #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */
8173 #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */
8174 #define CAN_F4R2_FB27_Pos (27U)
8175 #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */
8176 #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */
8177 #define CAN_F4R2_FB28_Pos (28U)
8178 #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */
8179 #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */
8180 #define CAN_F4R2_FB29_Pos (29U)
8181 #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */
8182 #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */
8183 #define CAN_F4R2_FB30_Pos (30U)
8184 #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */
8185 #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */
8186 #define CAN_F4R2_FB31_Pos (31U)
8187 #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */
8188 #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */
8189 
8190 /******************* Bit definition for CAN_F5R2 register *******************/
8191 #define CAN_F5R2_FB0_Pos (0U)
8192 #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */
8193 #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */
8194 #define CAN_F5R2_FB1_Pos (1U)
8195 #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */
8196 #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */
8197 #define CAN_F5R2_FB2_Pos (2U)
8198 #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */
8199 #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */
8200 #define CAN_F5R2_FB3_Pos (3U)
8201 #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */
8202 #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */
8203 #define CAN_F5R2_FB4_Pos (4U)
8204 #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */
8205 #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */
8206 #define CAN_F5R2_FB5_Pos (5U)
8207 #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */
8208 #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */
8209 #define CAN_F5R2_FB6_Pos (6U)
8210 #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */
8211 #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */
8212 #define CAN_F5R2_FB7_Pos (7U)
8213 #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */
8214 #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */
8215 #define CAN_F5R2_FB8_Pos (8U)
8216 #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */
8217 #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */
8218 #define CAN_F5R2_FB9_Pos (9U)
8219 #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */
8220 #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */
8221 #define CAN_F5R2_FB10_Pos (10U)
8222 #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */
8223 #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */
8224 #define CAN_F5R2_FB11_Pos (11U)
8225 #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */
8226 #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */
8227 #define CAN_F5R2_FB12_Pos (12U)
8228 #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */
8229 #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */
8230 #define CAN_F5R2_FB13_Pos (13U)
8231 #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */
8232 #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */
8233 #define CAN_F5R2_FB14_Pos (14U)
8234 #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */
8235 #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */
8236 #define CAN_F5R2_FB15_Pos (15U)
8237 #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */
8238 #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */
8239 #define CAN_F5R2_FB16_Pos (16U)
8240 #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */
8241 #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */
8242 #define CAN_F5R2_FB17_Pos (17U)
8243 #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */
8244 #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */
8245 #define CAN_F5R2_FB18_Pos (18U)
8246 #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */
8247 #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */
8248 #define CAN_F5R2_FB19_Pos (19U)
8249 #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */
8250 #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */
8251 #define CAN_F5R2_FB20_Pos (20U)
8252 #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */
8253 #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */
8254 #define CAN_F5R2_FB21_Pos (21U)
8255 #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */
8256 #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */
8257 #define CAN_F5R2_FB22_Pos (22U)
8258 #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */
8259 #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */
8260 #define CAN_F5R2_FB23_Pos (23U)
8261 #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */
8262 #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */
8263 #define CAN_F5R2_FB24_Pos (24U)
8264 #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */
8265 #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */
8266 #define CAN_F5R2_FB25_Pos (25U)
8267 #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */
8268 #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */
8269 #define CAN_F5R2_FB26_Pos (26U)
8270 #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */
8271 #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */
8272 #define CAN_F5R2_FB27_Pos (27U)
8273 #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */
8274 #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */
8275 #define CAN_F5R2_FB28_Pos (28U)
8276 #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */
8277 #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */
8278 #define CAN_F5R2_FB29_Pos (29U)
8279 #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */
8280 #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */
8281 #define CAN_F5R2_FB30_Pos (30U)
8282 #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */
8283 #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */
8284 #define CAN_F5R2_FB31_Pos (31U)
8285 #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */
8286 #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */
8287 
8288 /******************* Bit definition for CAN_F6R2 register *******************/
8289 #define CAN_F6R2_FB0_Pos (0U)
8290 #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */
8291 #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */
8292 #define CAN_F6R2_FB1_Pos (1U)
8293 #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */
8294 #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */
8295 #define CAN_F6R2_FB2_Pos (2U)
8296 #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */
8297 #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */
8298 #define CAN_F6R2_FB3_Pos (3U)
8299 #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */
8300 #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */
8301 #define CAN_F6R2_FB4_Pos (4U)
8302 #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */
8303 #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */
8304 #define CAN_F6R2_FB5_Pos (5U)
8305 #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */
8306 #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */
8307 #define CAN_F6R2_FB6_Pos (6U)
8308 #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */
8309 #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */
8310 #define CAN_F6R2_FB7_Pos (7U)
8311 #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */
8312 #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */
8313 #define CAN_F6R2_FB8_Pos (8U)
8314 #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */
8315 #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */
8316 #define CAN_F6R2_FB9_Pos (9U)
8317 #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */
8318 #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */
8319 #define CAN_F6R2_FB10_Pos (10U)
8320 #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */
8321 #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */
8322 #define CAN_F6R2_FB11_Pos (11U)
8323 #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */
8324 #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */
8325 #define CAN_F6R2_FB12_Pos (12U)
8326 #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */
8327 #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */
8328 #define CAN_F6R2_FB13_Pos (13U)
8329 #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */
8330 #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */
8331 #define CAN_F6R2_FB14_Pos (14U)
8332 #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */
8333 #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */
8334 #define CAN_F6R2_FB15_Pos (15U)
8335 #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */
8336 #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */
8337 #define CAN_F6R2_FB16_Pos (16U)
8338 #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */
8339 #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */
8340 #define CAN_F6R2_FB17_Pos (17U)
8341 #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */
8342 #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */
8343 #define CAN_F6R2_FB18_Pos (18U)
8344 #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */
8345 #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */
8346 #define CAN_F6R2_FB19_Pos (19U)
8347 #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */
8348 #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */
8349 #define CAN_F6R2_FB20_Pos (20U)
8350 #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */
8351 #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */
8352 #define CAN_F6R2_FB21_Pos (21U)
8353 #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */
8354 #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */
8355 #define CAN_F6R2_FB22_Pos (22U)
8356 #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */
8357 #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */
8358 #define CAN_F6R2_FB23_Pos (23U)
8359 #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */
8360 #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */
8361 #define CAN_F6R2_FB24_Pos (24U)
8362 #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */
8363 #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */
8364 #define CAN_F6R2_FB25_Pos (25U)
8365 #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */
8366 #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */
8367 #define CAN_F6R2_FB26_Pos (26U)
8368 #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */
8369 #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */
8370 #define CAN_F6R2_FB27_Pos (27U)
8371 #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */
8372 #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */
8373 #define CAN_F6R2_FB28_Pos (28U)
8374 #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */
8375 #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */
8376 #define CAN_F6R2_FB29_Pos (29U)
8377 #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */
8378 #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */
8379 #define CAN_F6R2_FB30_Pos (30U)
8380 #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */
8381 #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */
8382 #define CAN_F6R2_FB31_Pos (31U)
8383 #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */
8384 #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */
8385 
8386 /******************* Bit definition for CAN_F7R2 register *******************/
8387 #define CAN_F7R2_FB0_Pos (0U)
8388 #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */
8389 #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */
8390 #define CAN_F7R2_FB1_Pos (1U)
8391 #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */
8392 #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */
8393 #define CAN_F7R2_FB2_Pos (2U)
8394 #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */
8395 #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */
8396 #define CAN_F7R2_FB3_Pos (3U)
8397 #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */
8398 #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */
8399 #define CAN_F7R2_FB4_Pos (4U)
8400 #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */
8401 #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */
8402 #define CAN_F7R2_FB5_Pos (5U)
8403 #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */
8404 #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */
8405 #define CAN_F7R2_FB6_Pos (6U)
8406 #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */
8407 #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */
8408 #define CAN_F7R2_FB7_Pos (7U)
8409 #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */
8410 #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */
8411 #define CAN_F7R2_FB8_Pos (8U)
8412 #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */
8413 #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */
8414 #define CAN_F7R2_FB9_Pos (9U)
8415 #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */
8416 #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */
8417 #define CAN_F7R2_FB10_Pos (10U)
8418 #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */
8419 #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */
8420 #define CAN_F7R2_FB11_Pos (11U)
8421 #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */
8422 #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */
8423 #define CAN_F7R2_FB12_Pos (12U)
8424 #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */
8425 #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */
8426 #define CAN_F7R2_FB13_Pos (13U)
8427 #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */
8428 #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */
8429 #define CAN_F7R2_FB14_Pos (14U)
8430 #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */
8431 #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */
8432 #define CAN_F7R2_FB15_Pos (15U)
8433 #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */
8434 #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */
8435 #define CAN_F7R2_FB16_Pos (16U)
8436 #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */
8437 #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */
8438 #define CAN_F7R2_FB17_Pos (17U)
8439 #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */
8440 #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */
8441 #define CAN_F7R2_FB18_Pos (18U)
8442 #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */
8443 #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */
8444 #define CAN_F7R2_FB19_Pos (19U)
8445 #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */
8446 #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */
8447 #define CAN_F7R2_FB20_Pos (20U)
8448 #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */
8449 #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */
8450 #define CAN_F7R2_FB21_Pos (21U)
8451 #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */
8452 #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */
8453 #define CAN_F7R2_FB22_Pos (22U)
8454 #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */
8455 #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */
8456 #define CAN_F7R2_FB23_Pos (23U)
8457 #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */
8458 #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */
8459 #define CAN_F7R2_FB24_Pos (24U)
8460 #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */
8461 #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */
8462 #define CAN_F7R2_FB25_Pos (25U)
8463 #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */
8464 #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */
8465 #define CAN_F7R2_FB26_Pos (26U)
8466 #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */
8467 #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */
8468 #define CAN_F7R2_FB27_Pos (27U)
8469 #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */
8470 #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */
8471 #define CAN_F7R2_FB28_Pos (28U)
8472 #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */
8473 #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */
8474 #define CAN_F7R2_FB29_Pos (29U)
8475 #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */
8476 #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */
8477 #define CAN_F7R2_FB30_Pos (30U)
8478 #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */
8479 #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */
8480 #define CAN_F7R2_FB31_Pos (31U)
8481 #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */
8482 #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */
8483 
8484 /******************* Bit definition for CAN_F8R2 register *******************/
8485 #define CAN_F8R2_FB0_Pos (0U)
8486 #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */
8487 #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */
8488 #define CAN_F8R2_FB1_Pos (1U)
8489 #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */
8490 #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */
8491 #define CAN_F8R2_FB2_Pos (2U)
8492 #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */
8493 #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */
8494 #define CAN_F8R2_FB3_Pos (3U)
8495 #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */
8496 #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */
8497 #define CAN_F8R2_FB4_Pos (4U)
8498 #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */
8499 #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */
8500 #define CAN_F8R2_FB5_Pos (5U)
8501 #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */
8502 #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */
8503 #define CAN_F8R2_FB6_Pos (6U)
8504 #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */
8505 #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */
8506 #define CAN_F8R2_FB7_Pos (7U)
8507 #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */
8508 #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */
8509 #define CAN_F8R2_FB8_Pos (8U)
8510 #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */
8511 #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */
8512 #define CAN_F8R2_FB9_Pos (9U)
8513 #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */
8514 #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */
8515 #define CAN_F8R2_FB10_Pos (10U)
8516 #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */
8517 #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */
8518 #define CAN_F8R2_FB11_Pos (11U)
8519 #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */
8520 #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */
8521 #define CAN_F8R2_FB12_Pos (12U)
8522 #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */
8523 #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */
8524 #define CAN_F8R2_FB13_Pos (13U)
8525 #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */
8526 #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */
8527 #define CAN_F8R2_FB14_Pos (14U)
8528 #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */
8529 #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */
8530 #define CAN_F8R2_FB15_Pos (15U)
8531 #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */
8532 #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */
8533 #define CAN_F8R2_FB16_Pos (16U)
8534 #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */
8535 #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */
8536 #define CAN_F8R2_FB17_Pos (17U)
8537 #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */
8538 #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */
8539 #define CAN_F8R2_FB18_Pos (18U)
8540 #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */
8541 #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */
8542 #define CAN_F8R2_FB19_Pos (19U)
8543 #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */
8544 #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */
8545 #define CAN_F8R2_FB20_Pos (20U)
8546 #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */
8547 #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */
8548 #define CAN_F8R2_FB21_Pos (21U)
8549 #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */
8550 #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */
8551 #define CAN_F8R2_FB22_Pos (22U)
8552 #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */
8553 #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */
8554 #define CAN_F8R2_FB23_Pos (23U)
8555 #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */
8556 #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */
8557 #define CAN_F8R2_FB24_Pos (24U)
8558 #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */
8559 #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */
8560 #define CAN_F8R2_FB25_Pos (25U)
8561 #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */
8562 #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */
8563 #define CAN_F8R2_FB26_Pos (26U)
8564 #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */
8565 #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */
8566 #define CAN_F8R2_FB27_Pos (27U)
8567 #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */
8568 #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */
8569 #define CAN_F8R2_FB28_Pos (28U)
8570 #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */
8571 #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */
8572 #define CAN_F8R2_FB29_Pos (29U)
8573 #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */
8574 #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */
8575 #define CAN_F8R2_FB30_Pos (30U)
8576 #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */
8577 #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */
8578 #define CAN_F8R2_FB31_Pos (31U)
8579 #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */
8580 #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */
8581 
8582 /******************* Bit definition for CAN_F9R2 register *******************/
8583 #define CAN_F9R2_FB0_Pos (0U)
8584 #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */
8585 #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */
8586 #define CAN_F9R2_FB1_Pos (1U)
8587 #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */
8588 #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */
8589 #define CAN_F9R2_FB2_Pos (2U)
8590 #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */
8591 #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */
8592 #define CAN_F9R2_FB3_Pos (3U)
8593 #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */
8594 #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */
8595 #define CAN_F9R2_FB4_Pos (4U)
8596 #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */
8597 #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */
8598 #define CAN_F9R2_FB5_Pos (5U)
8599 #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */
8600 #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */
8601 #define CAN_F9R2_FB6_Pos (6U)
8602 #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */
8603 #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */
8604 #define CAN_F9R2_FB7_Pos (7U)
8605 #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */
8606 #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */
8607 #define CAN_F9R2_FB8_Pos (8U)
8608 #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */
8609 #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */
8610 #define CAN_F9R2_FB9_Pos (9U)
8611 #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */
8612 #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */
8613 #define CAN_F9R2_FB10_Pos (10U)
8614 #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */
8615 #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */
8616 #define CAN_F9R2_FB11_Pos (11U)
8617 #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */
8618 #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */
8619 #define CAN_F9R2_FB12_Pos (12U)
8620 #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */
8621 #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */
8622 #define CAN_F9R2_FB13_Pos (13U)
8623 #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */
8624 #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */
8625 #define CAN_F9R2_FB14_Pos (14U)
8626 #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */
8627 #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */
8628 #define CAN_F9R2_FB15_Pos (15U)
8629 #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */
8630 #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */
8631 #define CAN_F9R2_FB16_Pos (16U)
8632 #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */
8633 #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */
8634 #define CAN_F9R2_FB17_Pos (17U)
8635 #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */
8636 #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */
8637 #define CAN_F9R2_FB18_Pos (18U)
8638 #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */
8639 #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */
8640 #define CAN_F9R2_FB19_Pos (19U)
8641 #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */
8642 #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */
8643 #define CAN_F9R2_FB20_Pos (20U)
8644 #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */
8645 #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */
8646 #define CAN_F9R2_FB21_Pos (21U)
8647 #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */
8648 #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */
8649 #define CAN_F9R2_FB22_Pos (22U)
8650 #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */
8651 #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */
8652 #define CAN_F9R2_FB23_Pos (23U)
8653 #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */
8654 #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */
8655 #define CAN_F9R2_FB24_Pos (24U)
8656 #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */
8657 #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */
8658 #define CAN_F9R2_FB25_Pos (25U)
8659 #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */
8660 #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */
8661 #define CAN_F9R2_FB26_Pos (26U)
8662 #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */
8663 #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */
8664 #define CAN_F9R2_FB27_Pos (27U)
8665 #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */
8666 #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */
8667 #define CAN_F9R2_FB28_Pos (28U)
8668 #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */
8669 #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */
8670 #define CAN_F9R2_FB29_Pos (29U)
8671 #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */
8672 #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */
8673 #define CAN_F9R2_FB30_Pos (30U)
8674 #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */
8675 #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */
8676 #define CAN_F9R2_FB31_Pos (31U)
8677 #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */
8678 #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */
8679 
8680 /******************* Bit definition for CAN_F10R2 register ******************/
8681 #define CAN_F10R2_FB0_Pos (0U)
8682 #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */
8683 #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */
8684 #define CAN_F10R2_FB1_Pos (1U)
8685 #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */
8686 #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */
8687 #define CAN_F10R2_FB2_Pos (2U)
8688 #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */
8689 #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */
8690 #define CAN_F10R2_FB3_Pos (3U)
8691 #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */
8692 #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */
8693 #define CAN_F10R2_FB4_Pos (4U)
8694 #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */
8695 #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */
8696 #define CAN_F10R2_FB5_Pos (5U)
8697 #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */
8698 #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */
8699 #define CAN_F10R2_FB6_Pos (6U)
8700 #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */
8701 #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */
8702 #define CAN_F10R2_FB7_Pos (7U)
8703 #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */
8704 #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */
8705 #define CAN_F10R2_FB8_Pos (8U)
8706 #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */
8707 #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */
8708 #define CAN_F10R2_FB9_Pos (9U)
8709 #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */
8710 #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */
8711 #define CAN_F10R2_FB10_Pos (10U)
8712 #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */
8713 #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */
8714 #define CAN_F10R2_FB11_Pos (11U)
8715 #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */
8716 #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */
8717 #define CAN_F10R2_FB12_Pos (12U)
8718 #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */
8719 #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */
8720 #define CAN_F10R2_FB13_Pos (13U)
8721 #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */
8722 #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */
8723 #define CAN_F10R2_FB14_Pos (14U)
8724 #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */
8725 #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */
8726 #define CAN_F10R2_FB15_Pos (15U)
8727 #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */
8728 #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */
8729 #define CAN_F10R2_FB16_Pos (16U)
8730 #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */
8731 #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */
8732 #define CAN_F10R2_FB17_Pos (17U)
8733 #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */
8734 #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */
8735 #define CAN_F10R2_FB18_Pos (18U)
8736 #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */
8737 #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */
8738 #define CAN_F10R2_FB19_Pos (19U)
8739 #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */
8740 #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */
8741 #define CAN_F10R2_FB20_Pos (20U)
8742 #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */
8743 #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */
8744 #define CAN_F10R2_FB21_Pos (21U)
8745 #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */
8746 #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */
8747 #define CAN_F10R2_FB22_Pos (22U)
8748 #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */
8749 #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */
8750 #define CAN_F10R2_FB23_Pos (23U)
8751 #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */
8752 #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */
8753 #define CAN_F10R2_FB24_Pos (24U)
8754 #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */
8755 #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */
8756 #define CAN_F10R2_FB25_Pos (25U)
8757 #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */
8758 #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */
8759 #define CAN_F10R2_FB26_Pos (26U)
8760 #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */
8761 #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */
8762 #define CAN_F10R2_FB27_Pos (27U)
8763 #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */
8764 #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */
8765 #define CAN_F10R2_FB28_Pos (28U)
8766 #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */
8767 #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */
8768 #define CAN_F10R2_FB29_Pos (29U)
8769 #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */
8770 #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */
8771 #define CAN_F10R2_FB30_Pos (30U)
8772 #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */
8773 #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */
8774 #define CAN_F10R2_FB31_Pos (31U)
8775 #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */
8776 #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */
8777 
8778 /******************* Bit definition for CAN_F11R2 register ******************/
8779 #define CAN_F11R2_FB0_Pos (0U)
8780 #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */
8781 #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */
8782 #define CAN_F11R2_FB1_Pos (1U)
8783 #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */
8784 #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */
8785 #define CAN_F11R2_FB2_Pos (2U)
8786 #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */
8787 #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */
8788 #define CAN_F11R2_FB3_Pos (3U)
8789 #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */
8790 #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */
8791 #define CAN_F11R2_FB4_Pos (4U)
8792 #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */
8793 #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */
8794 #define CAN_F11R2_FB5_Pos (5U)
8795 #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */
8796 #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */
8797 #define CAN_F11R2_FB6_Pos (6U)
8798 #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */
8799 #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */
8800 #define CAN_F11R2_FB7_Pos (7U)
8801 #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */
8802 #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */
8803 #define CAN_F11R2_FB8_Pos (8U)
8804 #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */
8805 #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */
8806 #define CAN_F11R2_FB9_Pos (9U)
8807 #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */
8808 #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */
8809 #define CAN_F11R2_FB10_Pos (10U)
8810 #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */
8811 #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */
8812 #define CAN_F11R2_FB11_Pos (11U)
8813 #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */
8814 #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */
8815 #define CAN_F11R2_FB12_Pos (12U)
8816 #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */
8817 #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */
8818 #define CAN_F11R2_FB13_Pos (13U)
8819 #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */
8820 #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */
8821 #define CAN_F11R2_FB14_Pos (14U)
8822 #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */
8823 #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */
8824 #define CAN_F11R2_FB15_Pos (15U)
8825 #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */
8826 #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */
8827 #define CAN_F11R2_FB16_Pos (16U)
8828 #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */
8829 #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */
8830 #define CAN_F11R2_FB17_Pos (17U)
8831 #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */
8832 #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */
8833 #define CAN_F11R2_FB18_Pos (18U)
8834 #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */
8835 #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */
8836 #define CAN_F11R2_FB19_Pos (19U)
8837 #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */
8838 #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */
8839 #define CAN_F11R2_FB20_Pos (20U)
8840 #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */
8841 #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */
8842 #define CAN_F11R2_FB21_Pos (21U)
8843 #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */
8844 #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */
8845 #define CAN_F11R2_FB22_Pos (22U)
8846 #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */
8847 #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */
8848 #define CAN_F11R2_FB23_Pos (23U)
8849 #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */
8850 #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */
8851 #define CAN_F11R2_FB24_Pos (24U)
8852 #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */
8853 #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */
8854 #define CAN_F11R2_FB25_Pos (25U)
8855 #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */
8856 #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */
8857 #define CAN_F11R2_FB26_Pos (26U)
8858 #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */
8859 #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */
8860 #define CAN_F11R2_FB27_Pos (27U)
8861 #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */
8862 #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */
8863 #define CAN_F11R2_FB28_Pos (28U)
8864 #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */
8865 #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */
8866 #define CAN_F11R2_FB29_Pos (29U)
8867 #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */
8868 #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */
8869 #define CAN_F11R2_FB30_Pos (30U)
8870 #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */
8871 #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */
8872 #define CAN_F11R2_FB31_Pos (31U)
8873 #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */
8874 #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */
8875 
8876 /******************* Bit definition for CAN_F12R2 register ******************/
8877 #define CAN_F12R2_FB0_Pos (0U)
8878 #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */
8879 #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */
8880 #define CAN_F12R2_FB1_Pos (1U)
8881 #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */
8882 #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */
8883 #define CAN_F12R2_FB2_Pos (2U)
8884 #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */
8885 #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */
8886 #define CAN_F12R2_FB3_Pos (3U)
8887 #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */
8888 #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */
8889 #define CAN_F12R2_FB4_Pos (4U)
8890 #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */
8891 #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */
8892 #define CAN_F12R2_FB5_Pos (5U)
8893 #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */
8894 #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */
8895 #define CAN_F12R2_FB6_Pos (6U)
8896 #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */
8897 #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */
8898 #define CAN_F12R2_FB7_Pos (7U)
8899 #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */
8900 #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */
8901 #define CAN_F12R2_FB8_Pos (8U)
8902 #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */
8903 #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */
8904 #define CAN_F12R2_FB9_Pos (9U)
8905 #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */
8906 #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */
8907 #define CAN_F12R2_FB10_Pos (10U)
8908 #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */
8909 #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */
8910 #define CAN_F12R2_FB11_Pos (11U)
8911 #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */
8912 #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */
8913 #define CAN_F12R2_FB12_Pos (12U)
8914 #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */
8915 #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */
8916 #define CAN_F12R2_FB13_Pos (13U)
8917 #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */
8918 #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */
8919 #define CAN_F12R2_FB14_Pos (14U)
8920 #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */
8921 #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */
8922 #define CAN_F12R2_FB15_Pos (15U)
8923 #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */
8924 #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */
8925 #define CAN_F12R2_FB16_Pos (16U)
8926 #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */
8927 #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */
8928 #define CAN_F12R2_FB17_Pos (17U)
8929 #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */
8930 #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */
8931 #define CAN_F12R2_FB18_Pos (18U)
8932 #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */
8933 #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */
8934 #define CAN_F12R2_FB19_Pos (19U)
8935 #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */
8936 #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */
8937 #define CAN_F12R2_FB20_Pos (20U)
8938 #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */
8939 #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */
8940 #define CAN_F12R2_FB21_Pos (21U)
8941 #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */
8942 #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */
8943 #define CAN_F12R2_FB22_Pos (22U)
8944 #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */
8945 #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */
8946 #define CAN_F12R2_FB23_Pos (23U)
8947 #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */
8948 #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */
8949 #define CAN_F12R2_FB24_Pos (24U)
8950 #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */
8951 #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */
8952 #define CAN_F12R2_FB25_Pos (25U)
8953 #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */
8954 #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */
8955 #define CAN_F12R2_FB26_Pos (26U)
8956 #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */
8957 #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */
8958 #define CAN_F12R2_FB27_Pos (27U)
8959 #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */
8960 #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */
8961 #define CAN_F12R2_FB28_Pos (28U)
8962 #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */
8963 #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */
8964 #define CAN_F12R2_FB29_Pos (29U)
8965 #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */
8966 #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */
8967 #define CAN_F12R2_FB30_Pos (30U)
8968 #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */
8969 #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */
8970 #define CAN_F12R2_FB31_Pos (31U)
8971 #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */
8972 #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */
8973 
8974 /******************* Bit definition for CAN_F13R2 register ******************/
8975 #define CAN_F13R2_FB0_Pos (0U)
8976 #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */
8977 #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */
8978 #define CAN_F13R2_FB1_Pos (1U)
8979 #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */
8980 #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */
8981 #define CAN_F13R2_FB2_Pos (2U)
8982 #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */
8983 #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */
8984 #define CAN_F13R2_FB3_Pos (3U)
8985 #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */
8986 #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */
8987 #define CAN_F13R2_FB4_Pos (4U)
8988 #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */
8989 #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */
8990 #define CAN_F13R2_FB5_Pos (5U)
8991 #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */
8992 #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */
8993 #define CAN_F13R2_FB6_Pos (6U)
8994 #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */
8995 #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */
8996 #define CAN_F13R2_FB7_Pos (7U)
8997 #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */
8998 #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */
8999 #define CAN_F13R2_FB8_Pos (8U)
9000 #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */
9001 #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */
9002 #define CAN_F13R2_FB9_Pos (9U)
9003 #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */
9004 #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */
9005 #define CAN_F13R2_FB10_Pos (10U)
9006 #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */
9007 #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */
9008 #define CAN_F13R2_FB11_Pos (11U)
9009 #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */
9010 #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */
9011 #define CAN_F13R2_FB12_Pos (12U)
9012 #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */
9013 #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */
9014 #define CAN_F13R2_FB13_Pos (13U)
9015 #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */
9016 #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */
9017 #define CAN_F13R2_FB14_Pos (14U)
9018 #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */
9019 #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */
9020 #define CAN_F13R2_FB15_Pos (15U)
9021 #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */
9022 #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */
9023 #define CAN_F13R2_FB16_Pos (16U)
9024 #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */
9025 #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */
9026 #define CAN_F13R2_FB17_Pos (17U)
9027 #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */
9028 #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */
9029 #define CAN_F13R2_FB18_Pos (18U)
9030 #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */
9031 #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */
9032 #define CAN_F13R2_FB19_Pos (19U)
9033 #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */
9034 #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */
9035 #define CAN_F13R2_FB20_Pos (20U)
9036 #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */
9037 #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */
9038 #define CAN_F13R2_FB21_Pos (21U)
9039 #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */
9040 #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */
9041 #define CAN_F13R2_FB22_Pos (22U)
9042 #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */
9043 #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */
9044 #define CAN_F13R2_FB23_Pos (23U)
9045 #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */
9046 #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */
9047 #define CAN_F13R2_FB24_Pos (24U)
9048 #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */
9049 #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */
9050 #define CAN_F13R2_FB25_Pos (25U)
9051 #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */
9052 #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */
9053 #define CAN_F13R2_FB26_Pos (26U)
9054 #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */
9055 #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */
9056 #define CAN_F13R2_FB27_Pos (27U)
9057 #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */
9058 #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */
9059 #define CAN_F13R2_FB28_Pos (28U)
9060 #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */
9061 #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */
9062 #define CAN_F13R2_FB29_Pos (29U)
9063 #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */
9064 #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */
9065 #define CAN_F13R2_FB30_Pos (30U)
9066 #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */
9067 #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */
9068 #define CAN_F13R2_FB31_Pos (31U)
9069 #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */
9070 #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */
9071 
9072 /******************************************************************************/
9073 /* */
9074 /* Serial Peripheral Interface */
9075 /* */
9076 /******************************************************************************/
9077 
9078 /******************* Bit definition for SPI_CR1 register ********************/
9079 #define SPI_CR1_CPHA_Pos (0U)
9080 #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
9081 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
9082 #define SPI_CR1_CPOL_Pos (1U)
9083 #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
9084 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
9085 #define SPI_CR1_MSTR_Pos (2U)
9086 #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
9087 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
9088 
9089 #define SPI_CR1_BR_Pos (3U)
9090 #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
9091 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
9092 #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
9093 #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
9094 #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
9095 
9096 #define SPI_CR1_SPE_Pos (6U)
9097 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
9098 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
9099 #define SPI_CR1_LSBFIRST_Pos (7U)
9100 #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
9101 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
9102 #define SPI_CR1_SSI_Pos (8U)
9103 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
9104 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
9105 #define SPI_CR1_SSM_Pos (9U)
9106 #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
9107 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
9108 #define SPI_CR1_RXONLY_Pos (10U)
9109 #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
9110 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
9111 #define SPI_CR1_DFF_Pos (11U)
9112 #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */
9113 #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */
9114 #define SPI_CR1_CRCNEXT_Pos (12U)
9115 #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
9116 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
9117 #define SPI_CR1_CRCEN_Pos (13U)
9118 #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
9119 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
9120 #define SPI_CR1_BIDIOE_Pos (14U)
9121 #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
9122 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
9123 #define SPI_CR1_BIDIMODE_Pos (15U)
9124 #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
9125 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
9126 
9127 /******************* Bit definition for SPI_CR2 register ********************/
9128 #define SPI_CR2_RXDMAEN_Pos (0U)
9129 #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
9130 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
9131 #define SPI_CR2_TXDMAEN_Pos (1U)
9132 #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
9133 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
9134 #define SPI_CR2_SSOE_Pos (2U)
9135 #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
9136 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
9137 #define SPI_CR2_ERRIE_Pos (5U)
9138 #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
9139 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
9140 #define SPI_CR2_RXNEIE_Pos (6U)
9141 #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
9142 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
9143 #define SPI_CR2_TXEIE_Pos (7U)
9144 #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
9145 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
9146 
9147 /******************** Bit definition for SPI_SR register ********************/
9148 #define SPI_SR_RXNE_Pos (0U)
9149 #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
9150 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
9151 #define SPI_SR_TXE_Pos (1U)
9152 #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */
9153 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
9154 #define SPI_SR_CHSIDE_Pos (2U)
9155 #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
9156 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
9157 #define SPI_SR_UDR_Pos (3U)
9158 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */
9159 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
9160 #define SPI_SR_CRCERR_Pos (4U)
9161 #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
9162 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
9163 #define SPI_SR_MODF_Pos (5U)
9164 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */
9165 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
9166 #define SPI_SR_OVR_Pos (6U)
9167 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
9168 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
9169 #define SPI_SR_BSY_Pos (7U)
9170 #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */
9171 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
9172 
9173 /******************** Bit definition for SPI_DR register ********************/
9174 #define SPI_DR_DR_Pos (0U)
9175 #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */
9176 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
9177 
9178 /******************* Bit definition for SPI_CRCPR register ******************/
9179 #define SPI_CRCPR_CRCPOLY_Pos (0U)
9180 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
9181 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
9182 
9183 /****************** Bit definition for SPI_RXCRCR register ******************/
9184 #define SPI_RXCRCR_RXCRC_Pos (0U)
9185 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */
9186 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
9187 
9188 /****************** Bit definition for SPI_TXCRCR register ******************/
9189 #define SPI_TXCRCR_TXCRC_Pos (0U)
9190 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */
9191 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
9192 
9193 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
9194 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
9195 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */
9196 
9197 /******************************************************************************/
9198 /* */
9199 /* Inter-integrated Circuit Interface */
9200 /* */
9201 /******************************************************************************/
9202 
9203 /******************* Bit definition for I2C_CR1 register ********************/
9204 #define I2C_CR1_PE_Pos (0U)
9205 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
9206 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */
9207 #define I2C_CR1_SMBUS_Pos (1U)
9208 #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */
9209 #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */
9210 #define I2C_CR1_SMBTYPE_Pos (3U)
9211 #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */
9212 #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */
9213 #define I2C_CR1_ENARP_Pos (4U)
9214 #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */
9215 #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */
9216 #define I2C_CR1_ENPEC_Pos (5U)
9217 #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */
9218 #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */
9219 #define I2C_CR1_ENGC_Pos (6U)
9220 #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */
9221 #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */
9222 #define I2C_CR1_NOSTRETCH_Pos (7U)
9223 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */
9224 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */
9225 #define I2C_CR1_START_Pos (8U)
9226 #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */
9227 #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */
9228 #define I2C_CR1_STOP_Pos (9U)
9229 #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */
9230 #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */
9231 #define I2C_CR1_ACK_Pos (10U)
9232 #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */
9233 #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */
9234 #define I2C_CR1_POS_Pos (11U)
9235 #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */
9236 #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */
9237 #define I2C_CR1_PEC_Pos (12U)
9238 #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */
9239 #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */
9240 #define I2C_CR1_ALERT_Pos (13U)
9241 #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */
9242 #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */
9243 #define I2C_CR1_SWRST_Pos (15U)
9244 #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */
9245 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */
9246 
9247 /******************* Bit definition for I2C_CR2 register ********************/
9248 #define I2C_CR2_FREQ_Pos (0U)
9249 #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */
9250 #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
9251 #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */
9252 #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */
9253 #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */
9254 #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */
9255 #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */
9256 #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */
9257 
9258 #define I2C_CR2_ITERREN_Pos (8U)
9259 #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */
9260 #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */
9261 #define I2C_CR2_ITEVTEN_Pos (9U)
9262 #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */
9263 #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */
9264 #define I2C_CR2_ITBUFEN_Pos (10U)
9265 #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */
9266 #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */
9267 #define I2C_CR2_DMAEN_Pos (11U)
9268 #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */
9269 #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */
9270 #define I2C_CR2_LAST_Pos (12U)
9271 #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */
9272 #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */
9273 
9274 /******************* Bit definition for I2C_OAR1 register *******************/
9275 #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */
9276 #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */
9277 
9278 #define I2C_OAR1_ADD0_Pos (0U)
9279 #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */
9280 #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */
9281 #define I2C_OAR1_ADD1_Pos (1U)
9282 #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */
9283 #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */
9284 #define I2C_OAR1_ADD2_Pos (2U)
9285 #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */
9286 #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */
9287 #define I2C_OAR1_ADD3_Pos (3U)
9288 #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */
9289 #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */
9290 #define I2C_OAR1_ADD4_Pos (4U)
9291 #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */
9292 #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */
9293 #define I2C_OAR1_ADD5_Pos (5U)
9294 #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */
9295 #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */
9296 #define I2C_OAR1_ADD6_Pos (6U)
9297 #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */
9298 #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */
9299 #define I2C_OAR1_ADD7_Pos (7U)
9300 #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */
9301 #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */
9302 #define I2C_OAR1_ADD8_Pos (8U)
9303 #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */
9304 #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */
9305 #define I2C_OAR1_ADD9_Pos (9U)
9306 #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */
9307 #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */
9308 
9309 #define I2C_OAR1_ADDMODE_Pos (15U)
9310 #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */
9311 #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */
9312 
9313 /******************* Bit definition for I2C_OAR2 register *******************/
9314 #define I2C_OAR2_ENDUAL_Pos (0U)
9315 #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */
9316 #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */
9317 #define I2C_OAR2_ADD2_Pos (1U)
9318 #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */
9319 #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */
9320 
9321 /******************** Bit definition for I2C_DR register ********************/
9322 #define I2C_DR_DR_Pos (0U)
9323 #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */
9324 #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */
9325 
9326 /******************* Bit definition for I2C_SR1 register ********************/
9327 #define I2C_SR1_SB_Pos (0U)
9328 #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */
9329 #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */
9330 #define I2C_SR1_ADDR_Pos (1U)
9331 #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */
9332 #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */
9333 #define I2C_SR1_BTF_Pos (2U)
9334 #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */
9335 #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */
9336 #define I2C_SR1_ADD10_Pos (3U)
9337 #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */
9338 #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */
9339 #define I2C_SR1_STOPF_Pos (4U)
9340 #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */
9341 #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */
9342 #define I2C_SR1_RXNE_Pos (6U)
9343 #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */
9344 #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */
9345 #define I2C_SR1_TXE_Pos (7U)
9346 #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */
9347 #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */
9348 #define I2C_SR1_BERR_Pos (8U)
9349 #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */
9350 #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */
9351 #define I2C_SR1_ARLO_Pos (9U)
9352 #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */
9353 #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */
9354 #define I2C_SR1_AF_Pos (10U)
9355 #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */
9356 #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */
9357 #define I2C_SR1_OVR_Pos (11U)
9358 #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */
9359 #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */
9360 #define I2C_SR1_PECERR_Pos (12U)
9361 #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */
9362 #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */
9363 #define I2C_SR1_TIMEOUT_Pos (14U)
9364 #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */
9365 #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */
9366 #define I2C_SR1_SMBALERT_Pos (15U)
9367 #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */
9368 #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */
9369 
9370 /******************* Bit definition for I2C_SR2 register ********************/
9371 #define I2C_SR2_MSL_Pos (0U)
9372 #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */
9373 #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */
9374 #define I2C_SR2_BUSY_Pos (1U)
9375 #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */
9376 #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */
9377 #define I2C_SR2_TRA_Pos (2U)
9378 #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */
9379 #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */
9380 #define I2C_SR2_GENCALL_Pos (4U)
9381 #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */
9382 #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */
9383 #define I2C_SR2_SMBDEFAULT_Pos (5U)
9384 #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */
9385 #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */
9386 #define I2C_SR2_SMBHOST_Pos (6U)
9387 #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */
9388 #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */
9389 #define I2C_SR2_DUALF_Pos (7U)
9390 #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */
9391 #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */
9392 #define I2C_SR2_PEC_Pos (8U)
9393 #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */
9394 #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */
9395 
9396 /******************* Bit definition for I2C_CCR register ********************/
9397 #define I2C_CCR_CCR_Pos (0U)
9398 #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */
9399 #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */
9400 #define I2C_CCR_DUTY_Pos (14U)
9401 #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */
9402 #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */
9403 #define I2C_CCR_FS_Pos (15U)
9404 #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */
9405 #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */
9406 
9407 /****************** Bit definition for I2C_TRISE register *******************/
9408 #define I2C_TRISE_TRISE_Pos (0U)
9409 #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */
9410 #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
9411 
9412 /******************************************************************************/
9413 /* */
9414 /* Universal Synchronous Asynchronous Receiver Transmitter */
9415 /* */
9416 /******************************************************************************/
9417 
9418 /******************* Bit definition for USART_SR register *******************/
9419 #define USART_SR_PE_Pos (0U)
9420 #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */
9421 #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */
9422 #define USART_SR_FE_Pos (1U)
9423 #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */
9424 #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */
9425 #define USART_SR_NE_Pos (2U)
9426 #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */
9427 #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */
9428 #define USART_SR_ORE_Pos (3U)
9429 #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */
9430 #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */
9431 #define USART_SR_IDLE_Pos (4U)
9432 #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */
9433 #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */
9434 #define USART_SR_RXNE_Pos (5U)
9435 #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */
9436 #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */
9437 #define USART_SR_TC_Pos (6U)
9438 #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */
9439 #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */
9440 #define USART_SR_TXE_Pos (7U)
9441 #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */
9442 #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */
9443 #define USART_SR_LBD_Pos (8U)
9444 #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */
9445 #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */
9446 #define USART_SR_CTS_Pos (9U)
9447 #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */
9448 #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */
9449 
9450 /******************* Bit definition for USART_DR register *******************/
9451 #define USART_DR_DR_Pos (0U)
9452 #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */
9453 #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */
9454 
9455 /****************** Bit definition for USART_BRR register *******************/
9456 #define USART_BRR_DIV_Fraction_Pos (0U)
9457 #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */
9458 #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */
9459 #define USART_BRR_DIV_Mantissa_Pos (4U)
9460 #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */
9461 #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */
9462 
9463 /****************** Bit definition for USART_CR1 register *******************/
9464 #define USART_CR1_SBK_Pos (0U)
9465 #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */
9466 #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */
9467 #define USART_CR1_RWU_Pos (1U)
9468 #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */
9469 #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */
9470 #define USART_CR1_RE_Pos (2U)
9471 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
9472 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
9473 #define USART_CR1_TE_Pos (3U)
9474 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
9475 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
9476 #define USART_CR1_IDLEIE_Pos (4U)
9477 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
9478 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
9479 #define USART_CR1_RXNEIE_Pos (5U)
9480 #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
9481 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
9482 #define USART_CR1_TCIE_Pos (6U)
9483 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
9484 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
9485 #define USART_CR1_TXEIE_Pos (7U)
9486 #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
9487 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */
9488 #define USART_CR1_PEIE_Pos (8U)
9489 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
9490 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
9491 #define USART_CR1_PS_Pos (9U)
9492 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
9493 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
9494 #define USART_CR1_PCE_Pos (10U)
9495 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
9496 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
9497 #define USART_CR1_WAKE_Pos (11U)
9498 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
9499 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */
9500 #define USART_CR1_M_Pos (12U)
9501 #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */
9502 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
9503 #define USART_CR1_UE_Pos (13U)
9504 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */
9505 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
9506 
9507 /****************** Bit definition for USART_CR2 register *******************/
9508 #define USART_CR2_ADD_Pos (0U)
9509 #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */
9510 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
9511 #define USART_CR2_LBDL_Pos (5U)
9512 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
9513 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
9514 #define USART_CR2_LBDIE_Pos (6U)
9515 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
9516 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
9517 #define USART_CR2_LBCL_Pos (8U)
9518 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
9519 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
9520 #define USART_CR2_CPHA_Pos (9U)
9521 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
9522 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
9523 #define USART_CR2_CPOL_Pos (10U)
9524 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
9525 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
9526 #define USART_CR2_CLKEN_Pos (11U)
9527 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
9528 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
9529 
9530 #define USART_CR2_STOP_Pos (12U)
9531 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
9532 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
9533 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
9534 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
9535 
9536 #define USART_CR2_LINEN_Pos (14U)
9537 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
9538 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
9539 
9540 /****************** Bit definition for USART_CR3 register *******************/
9541 #define USART_CR3_EIE_Pos (0U)
9542 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
9543 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
9544 #define USART_CR3_IREN_Pos (1U)
9545 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
9546 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
9547 #define USART_CR3_IRLP_Pos (2U)
9548 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
9549 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
9550 #define USART_CR3_HDSEL_Pos (3U)
9551 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
9552 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
9553 #define USART_CR3_NACK_Pos (4U)
9554 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
9555 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */
9556 #define USART_CR3_SCEN_Pos (5U)
9557 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
9558 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */
9559 #define USART_CR3_DMAR_Pos (6U)
9560 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
9561 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
9562 #define USART_CR3_DMAT_Pos (7U)
9563 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
9564 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
9565 #define USART_CR3_RTSE_Pos (8U)
9566 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
9567 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
9568 #define USART_CR3_CTSE_Pos (9U)
9569 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
9570 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
9571 #define USART_CR3_CTSIE_Pos (10U)
9572 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
9573 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
9574 
9575 /****************** Bit definition for USART_GTPR register ******************/
9576 #define USART_GTPR_PSC_Pos (0U)
9577 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
9578 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
9579 #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */
9580 #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */
9581 #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */
9582 #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */
9583 #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */
9584 #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */
9585 #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */
9586 #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */
9587 
9588 #define USART_GTPR_GT_Pos (8U)
9589 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
9590 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */
9591 
9592 /******************************************************************************/
9593 /* */
9594 /* Debug MCU */
9595 /* */
9596 /******************************************************************************/
9597 
9598 /**************** Bit definition for DBGMCU_IDCODE register *****************/
9599 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
9600 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
9601 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
9602 
9603 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
9604 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
9605 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
9606 #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
9607 #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
9608 #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
9609 #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
9610 #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
9611 #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
9612 #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
9613 #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
9614 #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
9615 #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
9616 #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
9617 #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
9618 #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
9619 #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
9620 #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
9621 #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
9622 
9623 /****************** Bit definition for DBGMCU_CR register *******************/
9624 #define DBGMCU_CR_DBG_SLEEP_Pos (0U)
9625 #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
9626 #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */
9627 #define DBGMCU_CR_DBG_STOP_Pos (1U)
9628 #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
9629 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
9630 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
9631 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
9632 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
9633 #define DBGMCU_CR_TRACE_IOEN_Pos (5U)
9634 #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
9635 #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */
9636 
9637 #define DBGMCU_CR_TRACE_MODE_Pos (6U)
9638 #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
9639 #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
9640 #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
9641 #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
9642 
9643 #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)
9644 #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */
9645 #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
9646 #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)
9647 #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */
9648 #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
9649 #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)
9650 #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */
9651 #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
9652 #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)
9653 #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */
9654 #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
9655 #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)
9656 #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */
9657 #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
9658 #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)
9659 #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */
9660 #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
9661 #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)
9662 #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */
9663 #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */
9664 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)
9665 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */
9666 #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
9667 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)
9668 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */
9669 #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
9670 
9671 /******************************************************************************/
9672 /* */
9673 /* FLASH and Option Bytes Registers */
9674 /* */
9675 /******************************************************************************/
9676 /******************* Bit definition for FLASH_ACR register ******************/
9677 #define FLASH_ACR_LATENCY_Pos (0U)
9678 #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
9679 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */
9680 #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
9681 #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
9682 #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
9683 
9684 #define FLASH_ACR_HLFCYA_Pos (3U)
9685 #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */
9686 #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */
9687 #define FLASH_ACR_PRFTBE_Pos (4U)
9688 #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
9689 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
9690 #define FLASH_ACR_PRFTBS_Pos (5U)
9691 #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
9692 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
9693 
9694 /****************** Bit definition for FLASH_KEYR register ******************/
9695 #define FLASH_KEYR_FKEYR_Pos (0U)
9696 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
9697 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
9698 
9699 #define RDP_KEY_Pos (0U)
9700 #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */
9701 #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */
9702 #define FLASH_KEY1_Pos (0U)
9703 #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */
9704 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */
9705 #define FLASH_KEY2_Pos (0U)
9706 #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
9707 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */
9708 
9709 /***************** Bit definition for FLASH_OPTKEYR register ****************/
9710 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
9711 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
9712 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
9713 
9714 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
9715 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
9716 
9717 /****************** Bit definition for FLASH_SR register ********************/
9718 #define FLASH_SR_BSY_Pos (0U)
9719 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
9720 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
9721 #define FLASH_SR_PGERR_Pos (2U)
9722 #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
9723 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
9724 #define FLASH_SR_WRPRTERR_Pos (4U)
9725 #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
9726 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
9727 #define FLASH_SR_EOP_Pos (5U)
9728 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
9729 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
9730 
9731 /******************* Bit definition for FLASH_CR register *******************/
9732 #define FLASH_CR_PG_Pos (0U)
9733 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
9734 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
9735 #define FLASH_CR_PER_Pos (1U)
9736 #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
9737 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
9738 #define FLASH_CR_MER_Pos (2U)
9739 #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
9740 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
9741 #define FLASH_CR_OPTPG_Pos (4U)
9742 #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
9743 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
9744 #define FLASH_CR_OPTER_Pos (5U)
9745 #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
9746 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
9747 #define FLASH_CR_STRT_Pos (6U)
9748 #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
9749 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
9750 #define FLASH_CR_LOCK_Pos (7U)
9751 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
9752 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
9753 #define FLASH_CR_OPTWRE_Pos (9U)
9754 #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
9755 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
9756 #define FLASH_CR_ERRIE_Pos (10U)
9757 #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
9758 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
9759 #define FLASH_CR_EOPIE_Pos (12U)
9760 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
9761 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
9762 
9763 /******************* Bit definition for FLASH_AR register *******************/
9764 #define FLASH_AR_FAR_Pos (0U)
9765 #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
9766 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
9767 
9768 /****************** Bit definition for FLASH_OBR register *******************/
9769 #define FLASH_OBR_OPTERR_Pos (0U)
9770 #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
9771 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
9772 #define FLASH_OBR_RDPRT_Pos (1U)
9773 #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */
9774 #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */
9775 
9776 #define FLASH_OBR_IWDG_SW_Pos (2U)
9777 #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */
9778 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
9779 #define FLASH_OBR_nRST_STOP_Pos (3U)
9780 #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */
9781 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
9782 #define FLASH_OBR_nRST_STDBY_Pos (4U)
9783 #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */
9784 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
9785 #define FLASH_OBR_USER_Pos (2U)
9786 #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */
9787 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
9788 #define FLASH_OBR_DATA0_Pos (10U)
9789 #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */
9790 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
9791 #define FLASH_OBR_DATA1_Pos (18U)
9792 #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */
9793 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
9794 
9795 /****************** Bit definition for FLASH_WRPR register ******************/
9796 #define FLASH_WRPR_WRP_Pos (0U)
9797 #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */
9798 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
9799 
9800 /*----------------------------------------------------------------------------*/
9801 
9802 /****************** Bit definition for FLASH_RDP register *******************/
9803 #define FLASH_RDP_RDP_Pos (0U)
9804 #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */
9805 #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */
9806 #define FLASH_RDP_nRDP_Pos (8U)
9807 #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */
9808 #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */
9809 
9810 /****************** Bit definition for FLASH_USER register ******************/
9811 #define FLASH_USER_USER_Pos (16U)
9812 #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */
9813 #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */
9814 #define FLASH_USER_nUSER_Pos (24U)
9815 #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */
9816 #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */
9817 
9818 /****************** Bit definition for FLASH_Data0 register *****************/
9819 #define FLASH_DATA0_DATA0_Pos (0U)
9820 #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */
9821 #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */
9822 #define FLASH_DATA0_nDATA0_Pos (8U)
9823 #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */
9824 #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */
9825 
9826 /****************** Bit definition for FLASH_Data1 register *****************/
9827 #define FLASH_DATA1_DATA1_Pos (16U)
9828 #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */
9829 #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */
9830 #define FLASH_DATA1_nDATA1_Pos (24U)
9831 #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */
9832 #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */
9833 
9834 /****************** Bit definition for FLASH_WRP0 register ******************/
9835 #define FLASH_WRP0_WRP0_Pos (0U)
9836 #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */
9837 #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
9838 #define FLASH_WRP0_nWRP0_Pos (8U)
9839 #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
9840 #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
9841 
9842 /****************** Bit definition for FLASH_WRP1 register ******************/
9843 #define FLASH_WRP1_WRP1_Pos (16U)
9844 #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */
9845 #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */
9846 #define FLASH_WRP1_nWRP1_Pos (24U)
9847 #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */
9848 #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */
9849 
9850 /****************** Bit definition for FLASH_WRP2 register ******************/
9851 #define FLASH_WRP2_WRP2_Pos (0U)
9852 #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */
9853 #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */
9854 #define FLASH_WRP2_nWRP2_Pos (8U)
9855 #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */
9856 #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */
9857 
9858 /****************** Bit definition for FLASH_WRP3 register ******************/
9859 #define FLASH_WRP3_WRP3_Pos (16U)
9860 #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */
9861 #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */
9862 #define FLASH_WRP3_nWRP3_Pos (24U)
9863 #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */
9864 #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */
9865 
9866 
9867 
9868 /**
9869  * @}
9870 */
9871 
9872 /**
9873  * @}
9874 */
9875 
9876 /** @addtogroup Exported_macro
9877  * @{
9878  */
9879 
9880 /****************************** ADC Instances *********************************/
9881 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
9882  ((INSTANCE) == ADC2))
9883 
9884 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
9885 
9886 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9887 
9888 #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
9889 
9890 /****************************** CAN Instances *********************************/
9891 #define IS_CAN_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CAN1)
9892 
9893 /****************************** CRC Instances *********************************/
9894 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
9895 
9896 /****************************** DAC Instances *********************************/
9897 
9898 /****************************** DMA Instances *********************************/
9899 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
9900  ((INSTANCE) == DMA1_Channel2) || \
9901  ((INSTANCE) == DMA1_Channel3) || \
9902  ((INSTANCE) == DMA1_Channel4) || \
9903  ((INSTANCE) == DMA1_Channel5) || \
9904  ((INSTANCE) == DMA1_Channel6) || \
9905  ((INSTANCE) == DMA1_Channel7))
9906 
9907 /******************************* GPIO Instances *******************************/
9908 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
9909  ((INSTANCE) == GPIOB) || \
9910  ((INSTANCE) == GPIOC) || \
9911  ((INSTANCE) == GPIOD) || \
9912  ((INSTANCE) == GPIOE))
9913 
9914 /**************************** GPIO Alternate Function Instances ***************/
9915 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9916 
9917 /**************************** GPIO Lock Instances *****************************/
9918 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
9919 
9920 /******************************** I2C Instances *******************************/
9921 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
9922  ((INSTANCE) == I2C2))
9923 
9924 /******************************* SMBUS Instances ******************************/
9925 #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE
9926 
9927 /****************************** IWDG Instances ********************************/
9928 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
9929 
9930 /******************************** SPI Instances *******************************/
9931 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
9932  ((INSTANCE) == SPI2))
9933 
9934 /****************************** START TIM Instances ***************************/
9935 /****************************** TIM Instances *********************************/
9936 #define IS_TIM_INSTANCE(INSTANCE)\
9937  (((INSTANCE) == TIM1) || \
9938  ((INSTANCE) == TIM2) || \
9939  ((INSTANCE) == TIM3) || \
9940  ((INSTANCE) == TIM4))
9941 
9942 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
9943 
9944 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
9945  (((INSTANCE) == TIM1) || \
9946  ((INSTANCE) == TIM2) || \
9947  ((INSTANCE) == TIM3) || \
9948  ((INSTANCE) == TIM4))
9949 
9950 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
9951  (((INSTANCE) == TIM1) || \
9952  ((INSTANCE) == TIM2) || \
9953  ((INSTANCE) == TIM3) || \
9954  ((INSTANCE) == TIM4))
9955 
9956 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
9957  (((INSTANCE) == TIM1) || \
9958  ((INSTANCE) == TIM2) || \
9959  ((INSTANCE) == TIM3) || \
9960  ((INSTANCE) == TIM4))
9961 
9962 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
9963  (((INSTANCE) == TIM1) || \
9964  ((INSTANCE) == TIM2) || \
9965  ((INSTANCE) == TIM3) || \
9966  ((INSTANCE) == TIM4))
9967 
9968 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
9969  (((INSTANCE) == TIM1) || \
9970  ((INSTANCE) == TIM2) || \
9971  ((INSTANCE) == TIM3) || \
9972  ((INSTANCE) == TIM4))
9973 
9974 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
9975  (((INSTANCE) == TIM1) || \
9976  ((INSTANCE) == TIM2) || \
9977  ((INSTANCE) == TIM3) || \
9978  ((INSTANCE) == TIM4))
9979 
9980 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
9981  (((INSTANCE) == TIM1) || \
9982  ((INSTANCE) == TIM2) || \
9983  ((INSTANCE) == TIM3) || \
9984  ((INSTANCE) == TIM4))
9985 
9986 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
9987  (((INSTANCE) == TIM1) || \
9988  ((INSTANCE) == TIM2) || \
9989  ((INSTANCE) == TIM3) || \
9990  ((INSTANCE) == TIM4))
9991 
9992 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
9993  (((INSTANCE) == TIM1) || \
9994  ((INSTANCE) == TIM2) || \
9995  ((INSTANCE) == TIM3) || \
9996  ((INSTANCE) == TIM4))
9997 
9998 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
9999  (((INSTANCE) == TIM1) || \
10000  ((INSTANCE) == TIM2) || \
10001  ((INSTANCE) == TIM3) || \
10002  ((INSTANCE) == TIM4))
10003 
10004 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
10005  (((INSTANCE) == TIM1) || \
10006  ((INSTANCE) == TIM2) || \
10007  ((INSTANCE) == TIM3) || \
10008  ((INSTANCE) == TIM4))
10009 
10010 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
10011  (((INSTANCE) == TIM1) || \
10012  ((INSTANCE) == TIM2) || \
10013  ((INSTANCE) == TIM3) || \
10014  ((INSTANCE) == TIM4))
10015 
10016 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
10017  (((INSTANCE) == TIM1) || \
10018  ((INSTANCE) == TIM2) || \
10019  ((INSTANCE) == TIM3) || \
10020  ((INSTANCE) == TIM4))
10021 
10022 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
10023  (((INSTANCE) == TIM1) || \
10024  ((INSTANCE) == TIM2) || \
10025  ((INSTANCE) == TIM3) || \
10026  ((INSTANCE) == TIM4))
10027 
10028 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
10029  ((INSTANCE) == TIM1)
10030 
10031 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
10032  ((((INSTANCE) == TIM1) && \
10033  (((CHANNEL) == TIM_CHANNEL_1) || \
10034  ((CHANNEL) == TIM_CHANNEL_2) || \
10035  ((CHANNEL) == TIM_CHANNEL_3) || \
10036  ((CHANNEL) == TIM_CHANNEL_4))) \
10037  || \
10038  (((INSTANCE) == TIM2) && \
10039  (((CHANNEL) == TIM_CHANNEL_1) || \
10040  ((CHANNEL) == TIM_CHANNEL_2) || \
10041  ((CHANNEL) == TIM_CHANNEL_3) || \
10042  ((CHANNEL) == TIM_CHANNEL_4))) \
10043  || \
10044  (((INSTANCE) == TIM3) && \
10045  (((CHANNEL) == TIM_CHANNEL_1) || \
10046  ((CHANNEL) == TIM_CHANNEL_2) || \
10047  ((CHANNEL) == TIM_CHANNEL_3) || \
10048  ((CHANNEL) == TIM_CHANNEL_4))) \
10049  || \
10050  (((INSTANCE) == TIM4) && \
10051  (((CHANNEL) == TIM_CHANNEL_1) || \
10052  ((CHANNEL) == TIM_CHANNEL_2) || \
10053  ((CHANNEL) == TIM_CHANNEL_3) || \
10054  ((CHANNEL) == TIM_CHANNEL_4))))
10055 
10056 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
10057  (((INSTANCE) == TIM1) && \
10058  (((CHANNEL) == TIM_CHANNEL_1) || \
10059  ((CHANNEL) == TIM_CHANNEL_2) || \
10060  ((CHANNEL) == TIM_CHANNEL_3)))
10061 
10062 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
10063  (((INSTANCE) == TIM1) || \
10064  ((INSTANCE) == TIM2) || \
10065  ((INSTANCE) == TIM3) || \
10066  ((INSTANCE) == TIM4))
10067 
10068 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
10069  ((INSTANCE) == TIM1)
10070 
10071 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
10072  (((INSTANCE) == TIM1) || \
10073  ((INSTANCE) == TIM2) || \
10074  ((INSTANCE) == TIM3) || \
10075  ((INSTANCE) == TIM4))
10076 
10077 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
10078  (((INSTANCE) == TIM1) || \
10079  ((INSTANCE) == TIM2) || \
10080  ((INSTANCE) == TIM3) || \
10081  ((INSTANCE) == TIM4))
10082 
10083 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
10084  (((INSTANCE) == TIM1) || \
10085  ((INSTANCE) == TIM2) || \
10086  ((INSTANCE) == TIM3) || \
10087  ((INSTANCE) == TIM4))
10088 
10089 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
10090  ((INSTANCE) == TIM1)
10091 
10092 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10093  ((INSTANCE) == TIM2) || \
10094  ((INSTANCE) == TIM3) || \
10095  ((INSTANCE) == TIM4))
10096 
10097 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
10098  ((INSTANCE) == TIM2) || \
10099  ((INSTANCE) == TIM3) || \
10100  ((INSTANCE) == TIM4))
10101 
10102 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U
10103 
10104 /****************************** END TIM Instances *****************************/
10105 
10106 
10107 /******************** USART Instances : Synchronous mode **********************/
10108 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10109  ((INSTANCE) == USART2) || \
10110  ((INSTANCE) == USART3))
10111 
10112 /******************** UART Instances : Asynchronous mode **********************/
10113 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10114  ((INSTANCE) == USART2) || \
10115  ((INSTANCE) == USART3))
10116 
10117 /******************** UART Instances : Half-Duplex mode **********************/
10118 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10119  ((INSTANCE) == USART2) || \
10120  ((INSTANCE) == USART3))
10121 
10122 /******************** UART Instances : LIN mode **********************/
10123 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10124  ((INSTANCE) == USART2) || \
10125  ((INSTANCE) == USART3))
10126 
10127 /****************** UART Instances : Hardware Flow control ********************/
10128 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10129  ((INSTANCE) == USART2) || \
10130  ((INSTANCE) == USART3))
10131 
10132 /********************* UART Instances : Smard card mode ***********************/
10133 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10134  ((INSTANCE) == USART2) || \
10135  ((INSTANCE) == USART3))
10136 
10137 /*********************** UART Instances : IRDA mode ***************************/
10138 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10139  ((INSTANCE) == USART2) || \
10140  ((INSTANCE) == USART3))
10141 
10142 /***************** UART Instances : Multi-Processor mode **********************/
10143 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10144  ((INSTANCE) == USART2) || \
10145  ((INSTANCE) == USART3))
10146 
10147 /***************** UART Instances : DMA mode available **********************/
10148 #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
10149  ((INSTANCE) == USART2) || \
10150  ((INSTANCE) == USART3))
10151 
10152 /****************************** RTC Instances *********************************/
10153 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
10154 
10155 /**************************** WWDG Instances *****************************/
10156 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
10157 
10158 /****************************** USB Instances ********************************/
10159 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
10160 
10161 
10162 
10163 #define RCC_HSE_MIN 4000000U
10164 #define RCC_HSE_MAX 16000000U
10165 
10166 #define RCC_MAX_FREQUENCY 72000000U
10167 
10168 /**
10169  * @}
10170  */
10171 /******************************************************************************/
10172 /* For a painless codes migration between the STM32F1xx device product */
10173 /* lines, the aliases defined below are put in place to overcome the */
10174 /* differences in the interrupt handlers and IRQn definitions. */
10175 /* No need to update developed interrupt code when moving across */
10176 /* product lines within the same STM32F1 Family */
10177 /******************************************************************************/
10178 
10179 /* Aliases for __IRQn */
10180 #define ADC1_IRQn ADC1_2_IRQn
10181 #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn
10182 #define TIM9_IRQn TIM1_BRK_IRQn
10183 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
10184 #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn
10185 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
10186 #define TIM11_IRQn TIM1_TRG_COM_IRQn
10187 #define TIM10_IRQn TIM1_UP_IRQn
10188 #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn
10189 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
10190 #define OTG_FS_WKUP_IRQn USBWakeUp_IRQn
10191 #define CEC_IRQn USBWakeUp_IRQn
10192 #define CAN1_TX_IRQn USB_HP_CAN1_TX_IRQn
10193 #define USB_HP_IRQn USB_HP_CAN1_TX_IRQn
10194 #define CAN1_RX0_IRQn USB_LP_CAN1_RX0_IRQn
10195 #define USB_LP_IRQn USB_LP_CAN1_RX0_IRQn
10196 
10197 
10198 /* Aliases for __IRQHandler */
10199 #define ADC1_IRQHandler ADC1_2_IRQHandler
10200 #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler
10201 #define TIM9_IRQHandler TIM1_BRK_IRQHandler
10202 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
10203 #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler
10204 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
10205 #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
10206 #define TIM10_IRQHandler TIM1_UP_IRQHandler
10207 #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler
10208 #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler
10209 #define OTG_FS_WKUP_IRQHandler USBWakeUp_IRQHandler
10210 #define CEC_IRQHandler USBWakeUp_IRQHandler
10211 #define CAN1_TX_IRQHandler USB_HP_CAN1_TX_IRQHandler
10212 #define USB_HP_IRQHandler USB_HP_CAN1_TX_IRQHandler
10213 #define CAN1_RX0_IRQHandler USB_LP_CAN1_RX0_IRQHandler
10214 #define USB_LP_IRQHandler USB_LP_CAN1_RX0_IRQHandler
10215 
10216 
10217 /**
10218  * @}
10219  */
10220 
10221 /**
10222  * @}
10223  */
10224 
10225 
10226 #ifdef __cplusplus
10227  }
10228 #endif /* __cplusplus */
10229 
10230 #endif /* __STM32F103xB_H */
10231 
10232 
10233 
10234  /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
SPI_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:464
ADC_TypeDef::JOFR4
__IO uint32_t JOFR4
Definition: stm32f103xb.h:154
CAN_TypeDef::FS1R
__IO uint32_t FS1R
Definition: stm32f103xb.h:254
GPIO_TypeDef::LCKR
__IO uint32_t LCKR
Definition: stm32f103xb.h:366
USB_TypeDef::RESERVED5
__IO uint16_t RESERVED5
Definition: stm32f103xb.h:535
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f103xb.h:160
FLASH_TypeDef::OBR
__IO uint32_t OBR
Definition: stm32f103xb.h:334
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32f103xb.h:462
SPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:467
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f103xb.h:149
CAN_FIFOMailBox_TypeDef::RDTR
__IO uint32_t RDTR
Definition: stm32f103xb.h:218
FLASH_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:330
GPIO_TypeDef::CRH
__IO uint32_t CRH
Definition: stm32f103xb.h:361
DMA_Channel_TypeDef::CPAR
__IO uint32_t CPAR
Definition: stm32f103xb.h:295
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32f103xb.h:109
ADC_TypeDef::SMPR2
__IO uint32_t SMPR2
Definition: stm32f103xb.h:150
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f103xb.h:161
USB_LP_CAN1_RX0_IRQn
@ USB_LP_CAN1_RX0_IRQn
Definition: stm32f103xb.h:103
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32f103xb.h:507
RCC_TypeDef::CFGR
__IO uint32_t CFGR
Definition: stm32f103xb.h:427
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32f103xb.h:87
TIM_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:479
BKP_TypeDef::DR5
__IO uint32_t DR5
Definition: stm32f103xb.h:188
CAN_FIFOMailBox_TypeDef::RDLR
__IO uint32_t RDLR
Definition: stm32f103xb.h:219
OB_TypeDef::Data1
__IO uint16_t Data1
Definition: stm32f103xb.h:347
WWDG_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:559
TIM_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:483
USB_TypeDef::EP6R
__IO uint16_t EP6R
Definition: stm32f103xb.h:536
CAN_FilterRegister_TypeDef::FR1
__IO uint32_t FR1
Definition: stm32f103xb.h:229
DMA_TypeDef::IFCR
__IO uint32_t IFCR
Definition: stm32f103xb.h:302
CAN_TypeDef::MSR
__IO uint32_t MSR
Definition: stm32f103xb.h:240
DMA_Channel_TypeDef::CNDTR
__IO uint32_t CNDTR
Definition: stm32f103xb.h:294
OB_TypeDef::WRP1
__IO uint16_t WRP1
Definition: stm32f103xb.h:349
IWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:407
EXTI_TypeDef::SWIER
__IO uint32_t SWIER
Definition: stm32f103xb.h:317
DMA_TypeDef
Definition: stm32f103xb.h:299
RCC_TypeDef::APB1ENR
__IO uint32_t APB1ENR
Definition: stm32f103xb.h:433
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32f103xb.h:73
ADC_TypeDef::SQR1
__IO uint32_t SQR1
Definition: stm32f103xb.h:157
BKP_TypeDef::DR4
__IO uint32_t DR4
Definition: stm32f103xb.h:187
TIM_TypeDef::EGR
__IO uint32_t EGR
Definition: stm32f103xb.h:484
TIM_TypeDef::DIER
__IO uint32_t DIER
Definition: stm32f103xb.h:482
EXTI_TypeDef::RTSR
__IO uint32_t RTSR
Definition: stm32f103xb.h:315
TIM_TypeDef::BDTR
__IO uint32_t BDTR
Definition: stm32f103xb.h:496
RCC_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f103xb.h:435
FLASH_TypeDef::WRPR
__IO uint32_t WRPR
Definition: stm32f103xb.h:335
ADC_TypeDef::LTR
__IO uint32_t LTR
Definition: stm32f103xb.h:156
USB_TypeDef::DADDR
__IO uint16_t DADDR
Definition: stm32f103xb.h:546
AFIO_TypeDef::MAPR2
__IO uint32_t MAPR2
Definition: stm32f103xb.h:379
OB_TypeDef::RDP
__IO uint16_t RDP
Definition: stm32f103xb.h:344
ADC_Common_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:174
USART_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:509
RTC_IRQn
@ RTC_IRQn
Definition: stm32f103xb.h:86
USB_TypeDef::EP0R
__IO uint16_t EP0R
Definition: stm32f103xb.h:524
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32f103xb.h:90
USB_TypeDef::EP5R
__IO uint16_t EP5R
Definition: stm32f103xb.h:534
CAN_TxMailBox_TypeDef::TDTR
__IO uint32_t TDTR
Definition: stm32f103xb.h:206
DMA_Channel_TypeDef::CMAR
__IO uint32_t CMAR
Definition: stm32f103xb.h:296
DMA1_Channel2_IRQn
@ DMA1_Channel2_IRQn
Definition: stm32f103xb.h:95
CAN_TypeDef
Controller Area Network.
Definition: stm32f103xb.h:237
BKP_TypeDef::DR9
__IO uint32_t DR9
Definition: stm32f103xb.h:192
BKP_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f103xb.h:196
OB_TypeDef::USER
__IO uint16_t USER
Definition: stm32f103xb.h:345
ADC_TypeDef::JOFR3
__IO uint32_t JOFR3
Definition: stm32f103xb.h:153
SPI_TypeDef::RXCRCR
__IO uint32_t RXCRCR
Definition: stm32f103xb.h:469
CAN_TypeDef::FA1R
__IO uint32_t FA1R
Definition: stm32f103xb.h:258
USART_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:510
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32f103xb.h:115
RCC_TypeDef::APB2RSTR
__IO uint32_t APB2RSTR
Definition: stm32f103xb.h:429
DMA_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32f103xb.h:301
USB_TypeDef::RESERVED2
__IO uint16_t RESERVED2
Definition: stm32f103xb.h:529
I2C_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f103xb.h:394
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32f103xb.h:78
core_cm3.h
CMSIS Cortex-M3 Core Peripheral Access Layer Header File.
USB_TypeDef::CNTR
__IO uint16_t CNTR
Definition: stm32f103xb.h:540
USART_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:512
BKP_TypeDef::DR10
__IO uint32_t DR10
Definition: stm32f103xb.h:193
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f103xb.h:155
I2C_TypeDef
Inter Integrated Circuit Interface.
Definition: stm32f103xb.h:385
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32f103xb.h:112
SPI_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:465
DBGMCU_TypeDef
Debug MCU.
Definition: stm32f103xb.h:281
DMA_Channel_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32f103xb.h:293
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32f103xb.h:91
FLASH_TypeDef::OPTKEYR
__IO uint32_t OPTKEYR
Definition: stm32f103xb.h:329
DMA1_Channel7_IRQn
@ DMA1_Channel7_IRQn
Definition: stm32f103xb.h:100
CAN_TypeDef::ESR
__IO uint32_t ESR
Definition: stm32f103xb.h:245
BKP_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f103xb.h:183
TIM_TypeDef::OR
__IO uint32_t OR
Definition: stm32f103xb.h:499
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f103xb.h:487
USB_TypeDef::EP4R
__IO uint16_t EP4R
Definition: stm32f103xb.h:532
USB_TypeDef::RESERVED9
__IO uint16_t RESERVED9
Definition: stm32f103xb.h:543
CAN_TxMailBox_TypeDef::TDHR
__IO uint32_t TDHR
Definition: stm32f103xb.h:208
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32f103xb.h:92
GPIO_TypeDef::BSRR
__IO uint32_t BSRR
Definition: stm32f103xb.h:364
TIM_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:480
DBGMCU_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:284
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32f103xb.h:106
RTC_TypeDef::ALRH
__IO uint32_t ALRH
Definition: stm32f103xb.h:454
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32f103xb.h:76
EXTI_TypeDef::PR
__IO uint32_t PR
Definition: stm32f103xb.h:318
USB_TypeDef::FNR
__IO uint16_t FNR
Definition: stm32f103xb.h:544
TIM_TypeDef::DMAR
__IO uint32_t DMAR
Definition: stm32f103xb.h:498
GPIO_TypeDef::IDR
__IO uint32_t IDR
Definition: stm32f103xb.h:362
FLASH_TypeDef::KEYR
__IO uint32_t KEYR
Definition: stm32f103xb.h:328
AFIO_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32f103xb.h:378
RTC_TypeDef::DIVL
__IO uint32_t DIVL
Definition: stm32f103xb.h:451
ADC_Common_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:172
USB_TypeDef::RESERVED3
__IO uint16_t RESERVED3
Definition: stm32f103xb.h:531
ADC_Common_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:171
CRC_TypeDef::RESERVED1
uint16_t RESERVED1
Definition: stm32f103xb.h:272
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f103xb.h:151
CAN_TypeDef::FMR
__IO uint32_t FMR
Definition: stm32f103xb.h:251
ADC_TypeDef::JDR4
__IO uint32_t JDR4
Definition: stm32f103xb.h:164
CAN_FIFOMailBox_TypeDef::RDHR
__IO uint32_t RDHR
Definition: stm32f103xb.h:220
WWDG_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:561
EXTI_TypeDef::IMR
__IO uint32_t IMR
Definition: stm32f103xb.h:313
OB_TypeDef::WRP0
__IO uint16_t WRP0
Definition: stm32f103xb.h:348
USART_TypeDef::GTPR
__IO uint32_t GTPR
Definition: stm32f103xb.h:515
WWDG_TypeDef::CFR
__IO uint32_t CFR
Definition: stm32f103xb.h:560
CAN_TypeDef::RF0R
__IO uint32_t RF0R
Definition: stm32f103xb.h:242
USART3_IRQn
@ USART3_IRQn
Definition: stm32f103xb.h:122
USB_TypeDef::ISTR
__IO uint16_t ISTR
Definition: stm32f103xb.h:542
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32f103xb.h:107
TIM_TypeDef::SMCR
__IO uint32_t SMCR
Definition: stm32f103xb.h:481
TIM_TypeDef::PSC
__IO uint32_t PSC
Definition: stm32f103xb.h:489
GPIO_TypeDef::CRL
__IO uint32_t CRL
Definition: stm32f103xb.h:360
TIM_TypeDef::CCR3
__IO uint32_t CCR3
Definition: stm32f103xb.h:494
TIM_TypeDef
TIM Timers.
Definition: stm32f103xb.h:477
ADC1_2_IRQn
@ ADC1_2_IRQn
Definition: stm32f103xb.h:101
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32f103xb.h:402
OB_TypeDef::WRP3
__IO uint16_t WRP3
Definition: stm32f103xb.h:351
AFIO_TypeDef
Alternate Function I/O.
Definition: stm32f103xb.h:373
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32f103xb.h:118
CAN1_SCE_IRQn
@ CAN1_SCE_IRQn
Definition: stm32f103xb.h:105
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32f103xb.h:110
BKP_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:195
CAN_TypeDef::FM1R
__IO uint32_t FM1R
Definition: stm32f103xb.h:252
CRC_TypeDef
CRC calculation unit.
Definition: stm32f103xb.h:267
GPIO_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f103xb.h:365
PWR_TypeDef
Power Control.
Definition: stm32f103xb.h:414
RCC_TypeDef
Reset and Clock Control.
Definition: stm32f103xb.h:424
CAN_TypeDef::RESERVED4
uint32_t RESERVED4
Definition: stm32f103xb.h:257
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:148
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32f103xb.h:74
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:165
PVD_IRQn
@ PVD_IRQn
Definition: stm32f103xb.h:84
RCC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:426
RTC_TypeDef::DIVH
__IO uint32_t DIVH
Definition: stm32f103xb.h:450
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32f103xb.h:111
EXTI_TypeDef::FTSR
__IO uint32_t FTSR
Definition: stm32f103xb.h:316
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32f103xb.h:80
CAN_TypeDef::FFA1R
__IO uint32_t FFA1R
Definition: stm32f103xb.h:256
CAN1_RX1_IRQn
@ CAN1_RX1_IRQn
Definition: stm32f103xb.h:104
BKP_TypeDef
Backup Registers
Definition: stm32f103xb.h:181
IRQn_Type
IRQn_Type
STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32f103xb.h:69
RCC_IRQn
@ RCC_IRQn
Definition: stm32f103xb.h:88
RTC_TypeDef::CRH
__IO uint32_t CRH
Definition: stm32f103xb.h:446
I2C_TypeDef::SR1
__IO uint32_t SR1
Definition: stm32f103xb.h:392
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:146
DMA1_Channel3_IRQn
@ DMA1_Channel3_IRQn
Definition: stm32f103xb.h:96
CAN_TypeDef::RESERVED3
uint32_t RESERVED3
Definition: stm32f103xb.h:255
RCC_TypeDef::APB1RSTR
__IO uint32_t APB1RSTR
Definition: stm32f103xb.h:430
TAMPER_IRQn
@ TAMPER_IRQn
Definition: stm32f103xb.h:85
BKP_TypeDef::DR1
__IO uint32_t DR1
Definition: stm32f103xb.h:184
USB_TypeDef::RESERVED1
__IO uint16_t RESERVED1
Definition: stm32f103xb.h:527
RTC_TypeDef::PRLH
__IO uint32_t PRLH
Definition: stm32f103xb.h:448
DBGMCU_TypeDef::IDCODE
__IO uint32_t IDCODE
Definition: stm32f103xb.h:283
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f103xb.h:144
FLASH_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:331
BKP_TypeDef::DR3
__IO uint32_t DR3
Definition: stm32f103xb.h:186
TIM_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32f103xb.h:497
DMA_Channel_TypeDef
DMA Controller.
Definition: stm32f103xb.h:291
FLASH_TypeDef::ACR
__IO uint32_t ACR
Definition: stm32f103xb.h:327
USART1_IRQn
@ USART1_IRQn
Definition: stm32f103xb.h:120
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32f103xb.h:123
USB_TypeDef::RESERVED8
__IO uint16_t RESERVED8
Definition: stm32f103xb.h:541
CRC_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:273
CAN_TypeDef::IER
__IO uint32_t IER
Definition: stm32f103xb.h:244
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32f103xb.h:311
RTC_TypeDef::CNTH
__IO uint32_t CNTH
Definition: stm32f103xb.h:452
USART_TypeDef::CR3
__IO uint32_t CR3
Definition: stm32f103xb.h:514
USB_TypeDef::EP1R
__IO uint16_t EP1R
Definition: stm32f103xb.h:526
USART_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:513
PWR_TypeDef::CSR
__IO uint32_t CSR
Definition: stm32f103xb.h:417
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32f103xb.h:114
system_stm32f1xx.h
PWR_TypeDef::CR
__IO uint32_t CR
Definition: stm32f103xb.h:416
I2C_TypeDef::OAR1
__IO uint32_t OAR1
Definition: stm32f103xb.h:389
SPI_TypeDef::I2SCFGR
__IO uint32_t I2SCFGR
Definition: stm32f103xb.h:471
CAN_FilterRegister_TypeDef
Controller Area Network FilterRegister.
Definition: stm32f103xb.h:227
SPI_TypeDef::TXCRCR
__IO uint32_t TXCRCR
Definition: stm32f103xb.h:470
RCC_TypeDef::BDCR
__IO uint32_t BDCR
Definition: stm32f103xb.h:434
IWDG_TypeDef::RLR
__IO uint32_t RLR
Definition: stm32f103xb.h:406
USB_TypeDef::EP3R
__IO uint16_t EP3R
Definition: stm32f103xb.h:530
BKP_TypeDef::DR2
__IO uint32_t DR2
Definition: stm32f103xb.h:185
CAN_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32f103xb.h:253
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32f103xb.h:117
CAN_TxMailBox_TypeDef::TDLR
__IO uint32_t TDLR
Definition: stm32f103xb.h:207
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32f103xb.h:75
ADC_TypeDef::SQR2
__IO uint32_t SQR2
Definition: stm32f103xb.h:158
CAN_TypeDef::BTR
__IO uint32_t BTR
Definition: stm32f103xb.h:246
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32f103xb.h:113
GPIO_TypeDef
General Purpose I/O.
Definition: stm32f103xb.h:358
USB_TypeDef::BTABLE
__IO uint16_t BTABLE
Definition: stm32f103xb.h:548
OB_TypeDef::Data0
__IO uint16_t Data0
Definition: stm32f103xb.h:346
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32f103xb.h:108
GPIO_TypeDef::ODR
__IO uint32_t ODR
Definition: stm32f103xb.h:363
USART_TypeDef::BRR
__IO uint32_t BRR
Definition: stm32f103xb.h:511
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32f103xb.h:119
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f103xb.h:486
__IO
#define __IO
Definition: core_armv8mbl.h:196
TIM_TypeDef::CNT
__IO uint32_t CNT
Definition: stm32f103xb.h:488
BKP_TypeDef::DR8
__IO uint32_t DR8
Definition: stm32f103xb.h:191
DMA1_Channel6_IRQn
@ DMA1_Channel6_IRQn
Definition: stm32f103xb.h:99
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32f103xb.h:557
ADC_Common_TypeDef
Definition: stm32f103xb.h:168
USB_TypeDef::RESERVEDC
__IO uint16_t RESERVEDC
Definition: stm32f103xb.h:549
CRC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:269
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32f103xb.h:93
USB_HP_CAN1_TX_IRQn
@ USB_HP_CAN1_TX_IRQn
Definition: stm32f103xb.h:102
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f103xb.h:485
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32f103xb.h:77
FLASH_TypeDef::RESERVED
__IO uint32_t RESERVED
Definition: stm32f103xb.h:333
I2C_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32f103xb.h:393
USB_TypeDef::RESERVEDB
__IO uint16_t RESERVEDB
Definition: stm32f103xb.h:547
CRC_TypeDef::IDR
__IO uint8_t IDR
Definition: stm32f103xb.h:270
ADC_TypeDef::SQR3
__IO uint32_t SQR3
Definition: stm32f103xb.h:159
USB_TypeDef::RESERVED6
__IO uint16_t RESERVED6
Definition: stm32f103xb.h:537
AFIO_TypeDef::EVCR
__IO uint32_t EVCR
Definition: stm32f103xb.h:375
TIM_TypeDef::RCR
__IO uint32_t RCR
Definition: stm32f103xb.h:491
DMA1_Channel5_IRQn
@ DMA1_Channel5_IRQn
Definition: stm32f103xb.h:98
EXTI_TypeDef::EMR
__IO uint32_t EMR
Definition: stm32f103xb.h:314
TIM_TypeDef::ARR
__IO uint32_t ARR
Definition: stm32f103xb.h:490
ADC_TypeDef::JDR2
__IO uint32_t JDR2
Definition: stm32f103xb.h:162
ADC_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:147
USB_TypeDef::RESERVEDA
__IO uint16_t RESERVEDA
Definition: stm32f103xb.h:545
TIM_TypeDef::CCR1
__IO uint32_t CCR1
Definition: stm32f103xb.h:492
USBWakeUp_IRQn
@ USBWakeUp_IRQn
Definition: stm32f103xb.h:125
USB_TypeDef::RESERVED0
__IO uint16_t RESERVED0
Definition: stm32f103xb.h:525
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32f103xb.h:89
USB_TypeDef::EP7R
__IO uint16_t EP7R
Definition: stm32f103xb.h:538
RTC_TypeDef::CNTL
__IO uint32_t CNTL
Definition: stm32f103xb.h:453
USB_TypeDef::EP2R
__IO uint16_t EP2R
Definition: stm32f103xb.h:528
USB_TypeDef::RESERVED4
__IO uint16_t RESERVED4
Definition: stm32f103xb.h:533
DMA1_Channel4_IRQn
@ DMA1_Channel4_IRQn
Definition: stm32f103xb.h:97
SPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:466
RTC_TypeDef::ALRL
__IO uint32_t ALRL
Definition: stm32f103xb.h:455
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32f103xb.h:83
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32f103xb.h:79
CAN_TypeDef::RF1R
__IO uint32_t RF1R
Definition: stm32f103xb.h:243
I2C_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:391
CRC_TypeDef::RESERVED0
uint8_t RESERVED0
Definition: stm32f103xb.h:271
I2C_TypeDef::TRISE
__IO uint32_t TRISE
Definition: stm32f103xb.h:395
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32f103xb.h:124
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32f103xb.h:72
ADC_Common_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:170
RCC_TypeDef::CIR
__IO uint32_t CIR
Definition: stm32f103xb.h:428
RTC_TypeDef::CRL
__IO uint32_t CRL
Definition: stm32f103xb.h:447
CAN_TxMailBox_TypeDef::TIR
__IO uint32_t TIR
Definition: stm32f103xb.h:205
OB_TypeDef::WRP2
__IO uint16_t WRP2
Definition: stm32f103xb.h:350
FLASH_TypeDef
FLASH Registers.
Definition: stm32f103xb.h:325
BKP_TypeDef::DR7
__IO uint32_t DR7
Definition: stm32f103xb.h:190
ADC_TypeDef::JDR3
__IO uint32_t JDR3
Definition: stm32f103xb.h:163
BKP_TypeDef::DR6
__IO uint32_t DR6
Definition: stm32f103xb.h:189
USART2_IRQn
@ USART2_IRQn
Definition: stm32f103xb.h:121
I2C_TypeDef::OAR2
__IO uint32_t OAR2
Definition: stm32f103xb.h:390
OB_TypeDef
Option Bytes Registers.
Definition: stm32f103xb.h:342
RCC_TypeDef::APB2ENR
__IO uint32_t APB2ENR
Definition: stm32f103xb.h:432
CAN_TypeDef::TSR
__IO uint32_t TSR
Definition: stm32f103xb.h:241
BKP_TypeDef::RTCCR
__IO uint32_t RTCCR
Definition: stm32f103xb.h:194
USB_TypeDef
Universal Serial Bus Full Speed Device.
Definition: stm32f103xb.h:522
AFIO_TypeDef::MAPR
__IO uint32_t MAPR
Definition: stm32f103xb.h:376
CAN_TxMailBox_TypeDef
Controller Area Network TxMailBox.
Definition: stm32f103xb.h:203
IWDG_TypeDef::KR
__IO uint32_t KR
Definition: stm32f103xb.h:404
TIM_TypeDef::CCR4
__IO uint32_t CCR4
Definition: stm32f103xb.h:495
CAN_FIFOMailBox_TypeDef
Controller Area Network FIFOMailBox.
Definition: stm32f103xb.h:215
SPI_TypeDef::CRCPR
__IO uint32_t CRCPR
Definition: stm32f103xb.h:468
CAN_FilterRegister_TypeDef::FR2
__IO uint32_t FR2
Definition: stm32f103xb.h:230
CAN_FIFOMailBox_TypeDef::RIR
__IO uint32_t RIR
Definition: stm32f103xb.h:217
CAN_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32f103xb.h:239
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32f103xb.h:116
RTC_TypeDef
Real-Time Clock.
Definition: stm32f103xb.h:444
TIM_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32f103xb.h:493
I2C_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:388
DMA1_Channel1_IRQn
@ DMA1_Channel1_IRQn
Definition: stm32f103xb.h:94
ADC_TypeDef::JOFR2
__IO uint32_t JOFR2
Definition: stm32f103xb.h:152
RCC_TypeDef::AHBENR
__IO uint32_t AHBENR
Definition: stm32f103xb.h:431
FLASH_TypeDef::AR
__IO uint32_t AR
Definition: stm32f103xb.h:332
RTC_TypeDef::PRLL
__IO uint32_t PRLL
Definition: stm32f103xb.h:449
IWDG_TypeDef::PR
__IO uint32_t PR
Definition: stm32f103xb.h:405
I2C_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32f103xb.h:387