SYSTEM

System Configuration functions. More...

Functions
void	LL_SetSystemCoreClock (uint32_t HCLKFrequency)
	This function sets directly SystemCoreClock CMSIS variable. More...
ErrorStatus	LL_PLL_ConfigSystemClock_HSI (LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	Update number of Flash wait states in line with new frequency and current voltage range. More...
ErrorStatus	LL_PLL_ConfigSystemClock_HSE (uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	This function configures system clock with HSE as clock source of the PLL. More...

Detailed Description

System Configuration functions.

===============================================================================
          ##### System Configuration functions #####
===============================================================================
   [..]
        System, AHB and APB buses clocks configuration

        (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is RCC_MAX_FREQUENCY Hz.

Function Documentation

LL_PLL_ConfigSystemClock_HSE()

ErrorStatus LL_PLL_ConfigSystemClock_HSE	(	uint32_t	HSEFrequency,
		uint32_t	HSEBypass,
		LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

This function configures system clock with HSE as clock source of the PLL.

Note

The application need to ensure that PLL is disabled.

Function is based on the following formula:

• PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
• PREDIV: Set to 2 for few devices
• PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed UTILS_PLL_OUTPUT_MAX

FLASH latency can be modified through this function.

Parameters

HSEFrequency	Value between Min_Data = RCC_HSE_MIN and Max_Data = RCC_HSE_MAX
HSEBypass	This parameter can be one of the following values: LL_UTILS_HSEBYPASS_ON LL_UTILS_HSEBYPASS_OFF
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 399 of file stm32f1xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
  uint32_t pllfreq = 0U;
 
  /* Check the parameters */
  assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency));
  assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass));
 
  /* Check if one of the PLL is enabled */
  if (UTILS_PLL_IsBusy() == SUCCESS)
  {
    assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->Prediv));
 
    /* Calculate the new PLL output frequency */
    pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct);
 
    /* Enable HSE if not enabled */
    if (LL_RCC_HSE_IsReady() != 1U)
    {
      /* Check if need to enable HSE bypass feature or not */
      if (HSEBypass == LL_UTILS_HSEBYPASS_ON)
      {
        LL_RCC_HSE_EnableBypass();
      }
      else
      {
        LL_RCC_HSE_DisableBypass();
      }
 
      /* Enable HSE */
      LL_RCC_HSE_Enable();
      while (LL_RCC_HSE_IsReady() != 1U)
      {
        /* Wait for HSE ready */
      }
    }
 
    /* Configure PLL */
    LL_RCC_PLL_ConfigDomain_SYS((RCC_CFGR_PLLSRC | UTILS_PLLInitStruct->Prediv), UTILS_PLLInitStruct->PLLMul);
 
    /* Enable PLL and switch system clock to PLL */
    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  }
  else
  {
    /* Current PLL configuration cannot be modified */
    status = ERROR;
  }
 
  return status;
}

LL_PLL_ConfigSystemClock_HSI()

ErrorStatus LL_PLL_ConfigSystemClock_HSI	(	LL_UTILS_PLLInitTypeDef *	UTILS_PLLInitStruct,
		LL_UTILS_ClkInitTypeDef *	UTILS_ClkInitStruct
	)

Update number of Flash wait states in line with new frequency and current voltage range.

Parameters

Frequency

SYSCLK frequency

Return values

An	ErrorStatus enumeration value: SUCCESS: Latency has been modified ERROR: Latency cannot be modified

This function configures system clock with HSI as clock source of the PLL

Note

The application need to ensure that PLL is disabled.

Function is based on the following formula:

• PLL output frequency = ((HSI frequency / PREDIV) * PLLMUL)
• PREDIV: Set to 2 for few devices
• PLLMUL: The application software must set correctly the PLL multiplication factor to not exceed 72MHz

FLASH latency can be modified through this function.

Parameters

UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: Max frequency configuration done ERROR: Max frequency configuration not done

Definition at line 334 of file stm32f1xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
  uint32_t pllfreq = 0U;
 
  /* Check if one of the PLL is enabled */
  if (UTILS_PLL_IsBusy() == SUCCESS)
  {
#if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
    /* Check PREDIV value */
    assert_param(IS_LL_UTILS_PREDIV_VALUE(UTILS_PLLInitStruct->PLLDiv));
#else
    /* Force PREDIV value to 2 */
    UTILS_PLLInitStruct->Prediv = LL_RCC_PREDIV_DIV_2;
#endif /*RCC_PLLSRC_PREDIV1_SUPPORT*/
    /* Calculate the new PLL output frequency */
    pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct);
 
    /* Enable HSI if not enabled */
    if (LL_RCC_HSI_IsReady() != 1U)
    {
      LL_RCC_HSI_Enable();
      while (LL_RCC_HSI_IsReady() != 1U)
      {
        /* Wait for HSI ready */
      }
    }
 
    /* Configure PLL */
    LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSI_DIV_2, UTILS_PLLInitStruct->PLLMul);
 
    /* Enable PLL and switch system clock to PLL */
    status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct);
  }
  else
  {
    /* Current PLL configuration cannot be modified */
    status = ERROR;
  }
 
  return status;
}

LL_SetSystemCoreClock()

void LL_SetSystemCoreClock

(

uint32_t

HCLKFrequency

)

This function sets directly SystemCoreClock CMSIS variable.

Note

Variable can be calculated also through SystemCoreClockUpdate function.

Parameters

HCLKFrequency

HCLK frequency in Hz (can be calculated thanks to RCC helper macro)

Return values

None

Definition at line 240 of file stm32f1xx_ll_utils.c.

{
  /* HCLK clock frequency */
  SystemCoreClock = HCLKFrequency;
}