UTILS Private functions

Functions
static uint32_t	UTILS_GetPLLOutputFrequency (uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct)
	Function to check that PLL can be modified. More...
static ErrorStatus	UTILS_EnablePLLAndSwitchSystem (uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct)
	Function to enable PLL and switch system clock to PLL. More...
static ErrorStatus	UTILS_PLL_IsBusy (void)
	Function to check that PLL can be modified. More...

Detailed Description

Function Documentation

UTILS_EnablePLLAndSwitchSystem()

static ErrorStatus UTILS_EnablePLLAndSwitchSystem ( uint32_t  SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *  UTILS_ClkInitStruct  )

static

Function to enable PLL and switch system clock to PLL.

Parameters

SYSCLK_Frequency	SYSCLK frequency
UTILS_ClkInitStruct	pointer to a LL_UTILS_ClkInitTypeDef structure that contains the configuration information for the BUS prescalers.

Return values

An	ErrorStatus enumeration value: SUCCESS: No problem to switch system to PLL ERROR: Problem to switch system to PLL

Definition at line 535 of file stm32f1xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
#if defined(FLASH_ACR_LATENCY)
  uint32_t sysclk_frequency_current = 0U;
#endif /* FLASH_ACR_LATENCY */
 
  assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider));
  assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider));
  assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider));
 
#if defined(FLASH_ACR_LATENCY)
  /* Calculate current SYSCLK frequency */
  sysclk_frequency_current = (SystemCoreClock << AHBPrescTable[LL_RCC_GetAHBPrescaler() >> RCC_CFGR_HPRE_Pos]);
#endif /* FLASH_ACR_LATENCY */
 
  /* Increasing the number of wait states because of higher CPU frequency */
#if defined (FLASH_ACR_LATENCY)
  if (sysclk_frequency_current < SYSCLK_Frequency)
  {
    /* Set FLASH latency to highest latency */
    status = LL_SetFlashLatency(SYSCLK_Frequency);
  }
#endif /* FLASH_ACR_LATENCY */
 
  /* Update system clock configuration */
  if (status == SUCCESS)
  {
#if defined(RCC_PLL2_SUPPORT)
    if (LL_RCC_PLL_GetMainSource() != LL_RCC_PLLSOURCE_HSI_DIV_2)
    {
      /* Enable PLL2 */
      LL_RCC_PLL2_Enable();
      while (LL_RCC_PLL2_IsReady() != 1U)
      {
        /* Wait for PLL2 ready */
      }
    }
#endif /* RCC_PLL2_SUPPORT */
    /* Enable PLL */
    LL_RCC_PLL_Enable();
    while (LL_RCC_PLL_IsReady() != 1U)
    {
      /* Wait for PLL ready */
    }
 
    /* Sysclk activation on the main PLL */
    LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider);
    LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
    while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL)
    {
      /* Wait for system clock switch to PLL */
    }
 
    /* Set APB1 & APB2 prescaler*/
    LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider);
    LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider);
  }
 
  /* Decreasing the number of wait states because of lower CPU frequency */
#if defined (FLASH_ACR_LATENCY)
  if (sysclk_frequency_current > SYSCLK_Frequency)
  {
    /* Set FLASH latency to lowest latency */
    status = LL_SetFlashLatency(SYSCLK_Frequency);
  }
#endif /* FLASH_ACR_LATENCY */
 
  /* Update SystemCoreClock variable */
  if (status == SUCCESS)
  {
    LL_SetSystemCoreClock(__LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider));
  }
 
  return status;
}

UTILS_GetPLLOutputFrequency()

static uint32_t UTILS_GetPLLOutputFrequency ( uint32_t  PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *  UTILS_PLLInitStruct  )

static

Function to check that PLL can be modified.

Parameters

PLL_InputFrequency	PLL input frequency (in Hz)
UTILS_PLLInitStruct	pointer to a LL_UTILS_PLLInitTypeDef structure that contains the configuration information for the PLL.

Return values

PLL	output frequency (in Hz)

Definition at line 471 of file stm32f1xx_ll_utils.c.

{
  uint32_t pllfreq = 0U;
 
  /* Check the parameters */
  assert_param(IS_LL_UTILS_PLLMUL_VALUE(UTILS_PLLInitStruct->PLLMul));
 
  /* Check different PLL parameters according to RM                          */
#if defined (RCC_CFGR2_PREDIV1)
  pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / (UTILS_PLLInitStruct->Prediv + 1U), UTILS_PLLInitStruct->PLLMul);
#else
  pllfreq = __LL_RCC_CALC_PLLCLK_FREQ(PLL_InputFrequency / ((UTILS_PLLInitStruct->Prediv >> RCC_CFGR_PLLXTPRE_Pos) + 1U), UTILS_PLLInitStruct->PLLMul);
#endif /*RCC_CFGR2_PREDIV1SRC*/
  assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq));
 
  return pllfreq;
}

UTILS_PLL_IsBusy()

static ErrorStatus UTILS_PLL_IsBusy ( void  )

static

Function to check that PLL can be modified.

Return values

An	ErrorStatus enumeration value: SUCCESS: PLL modification can be done ERROR: PLL is busy

Definition at line 495 of file stm32f1xx_ll_utils.c.

{
  ErrorStatus status = SUCCESS;
 
  /* Check if PLL is busy*/
  if (LL_RCC_PLL_IsReady() != 0U)
  {
    /* PLL configuration cannot be modified */
    status = ERROR;
  }
#if defined(RCC_PLL2_SUPPORT)
  /* Check if PLL2 is busy*/
  if (LL_RCC_PLL2_IsReady() != 0U)
  {
    /* PLL2 configuration cannot be modified */
    status = ERROR;
  }
#endif /* RCC_PLL2_SUPPORT */
 
#if defined(RCC_PLLI2S_SUPPORT)
  /* Check if PLLI2S  is busy*/
  if (LL_RCC_PLLI2S_IsReady() != 0U)
  {
    /* PLLI2S configuration cannot be modified */
    status = ERROR;
  }
#endif /* RCC_PLLI2S_SUPPORT */
 
  return status;
}