Header file of RCC HAL module. More...

#include "stm32f1xx_hal_def.h"
#include "stm32f1xx_hal_rcc_ex.h"

Data Structures
struct	RCC_PLLInitTypeDef
	RCC PLL configuration structure definition. More...

struct	RCC_ClkInitTypeDef
	RCC System, AHB and APB busses clock configuration structure definition. More...

Macros
#define	RCC_PLLSOURCE_HSI_DIV2 0x00000000U

#define	RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC

#define	RCC_OSCILLATORTYPE_NONE 0x00000000U

#define	RCC_OSCILLATORTYPE_HSE 0x00000001U

#define	RCC_OSCILLATORTYPE_HSI 0x00000002U

#define	RCC_OSCILLATORTYPE_LSE 0x00000004U

#define	RCC_OSCILLATORTYPE_LSI 0x00000008U

#define	RCC_HSE_OFF 0x00000000U

#define	RCC_HSE_ON RCC_CR_HSEON

#define	RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))

#define	RCC_LSE_OFF 0x00000000U

#define	RCC_LSE_ON RCC_BDCR_LSEON

#define	RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))

#define	RCC_HSI_OFF 0x00000000U

#define	RCC_HSI_ON RCC_CR_HSION

#define	RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */

#define	RCC_LSI_OFF 0x00000000U

#define	RCC_LSI_ON RCC_CSR_LSION

#define	RCC_PLL_NONE 0x00000000U

#define	RCC_PLL_OFF 0x00000001U

#define	RCC_PLL_ON 0x00000002U

#define	RCC_CLOCKTYPE_SYSCLK 0x00000001U

#define	RCC_CLOCKTYPE_HCLK 0x00000002U

#define	RCC_CLOCKTYPE_PCLK1 0x00000004U

#define	RCC_CLOCKTYPE_PCLK2 0x00000008U

#define	RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

#define	RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

#define	RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL

#define	RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

#define	RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

#define	RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL

#define	RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1

#define	RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2

#define	RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4

#define	RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8

#define	RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16

#define	RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64

#define	RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128

#define	RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256

#define	RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512

#define	RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1

#define	RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2

#define	RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4

#define	RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8

#define	RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16

#define	RCC_RTCCLKSOURCE_NO_CLK 0x00000000U

#define	RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE

#define	RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI

#define	RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE

#define	RCC_MCO1 0x00000000U

#define	RCC_MCO RCC_MCO1

#define	RCC_MCODIV_1 0x00000000U

#define	RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)

#define	RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)

#define	RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)

#define	RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)

#define	RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)

#define	RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)

#define	RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSIRDY_Pos))

#define	RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_HSERDY_Pos))

#define	RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) \| RCC_CR_PLLRDY_Pos))

#define	RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LSIRDY_Pos))

#define	RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PINRSTF_Pos))

#define	RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_PORRSTF_Pos))

#define	RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_SFTRSTF_Pos))

#define	RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_IWDGRSTF_Pos))

#define	RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_WWDGRSTF_Pos))

#define	RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) \| RCC_CSR_LPWRRSTF_Pos))

#define	RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) \| RCC_BDCR_LSERDY_Pos))

#define	__HAL_RCC_DMA1_CLK_ENABLE()

#define	__HAL_RCC_SRAM_CLK_ENABLE()

#define	__HAL_RCC_FLITF_CLK_ENABLE()

#define	__HAL_RCC_CRC_CLK_ENABLE()

#define	__HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))

#define	__HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))

#define	__HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))

#define	__HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))

#define	__HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)

#define	__HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)

#define	__HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)

#define	__HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)

#define	__HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)

#define	__HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)

#define	__HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)

#define	__HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)

#define	__HAL_RCC_TIM2_CLK_ENABLE()

#define	__HAL_RCC_TIM3_CLK_ENABLE()

#define	__HAL_RCC_WWDG_CLK_ENABLE()

#define	__HAL_RCC_USART2_CLK_ENABLE()

#define	__HAL_RCC_I2C1_CLK_ENABLE()

#define	__HAL_RCC_BKP_CLK_ENABLE()

#define	__HAL_RCC_PWR_CLK_ENABLE()

#define	__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))

#define	__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))

#define	__HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))

#define	__HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))

#define	__HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))

#define	__HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))

#define	__HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))

#define	__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)

#define	__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)

#define	__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)

#define	__HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)

#define	__HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)

#define	__HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)

#define	__HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)

#define	__HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)

#define	__HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)

#define	__HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)

#define	__HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)

#define	__HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)

#define	__HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)

#define	__HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)

#define	__HAL_RCC_AFIO_CLK_ENABLE()

#define	__HAL_RCC_GPIOA_CLK_ENABLE()

#define	__HAL_RCC_GPIOB_CLK_ENABLE()

#define	__HAL_RCC_GPIOC_CLK_ENABLE()

#define	__HAL_RCC_GPIOD_CLK_ENABLE()

#define	__HAL_RCC_ADC1_CLK_ENABLE()

#define	__HAL_RCC_TIM1_CLK_ENABLE()

#define	__HAL_RCC_SPI1_CLK_ENABLE()

#define	__HAL_RCC_USART1_CLK_ENABLE()

#define	__HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))

#define	__HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))

#define	__HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))

#define	__HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))

#define	__HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))

#define	__HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))

#define	__HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))

#define	__HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))

#define	__HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))

#define	__HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)

#define	__HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)

#define	__HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)

#define	__HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)

#define	__HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)

#define	__HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)

#define	__HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)

#define	__HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)

#define	__HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)

#define	__HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)

#define	__HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)

#define	__HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)

#define	__HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)

#define	__HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)

#define	__HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)

#define	__HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)

#define	__HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)

#define	__HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)

#define	__HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)

#define	__HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))

#define	__HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))

#define	__HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))

#define	__HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))

#define	__HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))

#define	__HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_BKPRST))

#define	__HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))

#define	__HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)

#define	__HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))

#define	__HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))

#define	__HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))

#define	__HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))

#define	__HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))

#define	__HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))

#define	__HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))

#define	__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)

#define	__HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_AFIORST))

#define	__HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPARST))

#define	__HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPBRST))

#define	__HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPCRST))

#define	__HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_IOPDRST))

#define	__HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))

#define	__HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))

#define	__HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))

#define	__HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))

#define	__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)

#define	__HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))

#define	__HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))

#define	__HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))

#define	__HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))

#define	__HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))

#define	__HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))

#define	__HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))

#define	__HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))

#define	__HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))

#define	__HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = ENABLE)
	Macros to enable or disable the Internal High Speed oscillator (HSI). More...

#define	__HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) RCC_CR_HSION_BB = DISABLE)

#define	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
	Macro to adjust the Internal High Speed oscillator (HSI) calibration value. More...

#define	__HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = ENABLE)
	Macro to enable the Internal Low Speed oscillator (LSI). More...

#define	__HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) RCC_CSR_LSION_BB = DISABLE)
	Macro to disable the Internal Low Speed oscillator (LSI). More...

#define	__HAL_RCC_HSE_CONFIG(__STATE__)
	Macro to configure the External High Speed oscillator (HSE). More...

#define	__HAL_RCC_LSE_CONFIG(__STATE__)
	Macro to configure the External Low Speed oscillator (LSE). More...

#define	__HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = ENABLE)
	Macro to enable the main PLL. More...

#define	__HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) RCC_CR_PLLON_BB = DISABLE)
	Macro to disable the main PLL. More...

#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC \| RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) \| (__PLLMUL__) ))
	Macro to configure the main PLL clock source and multiplication factors. More...

#define	__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
	Get oscillator clock selected as PLL input clock. More...

#define	__HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
	Macro to configure the system clock source. More...

#define	__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
	Macro to get the clock source used as system clock. More...

#define	__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
	Macro to configure the MCO clock. More...

#define	__HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
	Macro to configure the RTC clock (RTCCLK). More...

#define	__HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
	Macro to get the RTC clock source. More...

#define	__HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = ENABLE)
	Macro to enable the the RTC clock. More...

#define	__HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) RCC_BDCR_RTCEN_BB = DISABLE)
	Macro to disable the the RTC clock. More...

#define	__HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = ENABLE)
	Macro to force the Backup domain reset. More...

#define	__HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) RCC_BDCR_BDRST_BB = DISABLE)
	Macros to release the Backup domain reset. More...

#define	__HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
	Enable RCC interrupt. More...

#define	__HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
	Disable RCC interrupt. More...

#define	__HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
	Clear the RCC's interrupt pending bits. More...

#define	__HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
	Check the RCC's interrupt has occurred or not. More...

#define	__HAL_RCC_CLEAR_RESET_FLAGS() ((__IO uint32_t )RCC_CSR_RMVF_BB = ENABLE)
	Set RMVF bit to clear the reset flags. The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST. More...

#define	__HAL_RCC_GET_FLAG(__FLAG__)
	Check RCC flag is set or not. More...

#define	RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */

#define	RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

#define	CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */

#define	HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

#define	HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

#define	LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

#define	PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */

#define	RCC_OFFSET (RCC_BASE - PERIPH_BASE)

#define	RCC_CR_OFFSET 0x00U

#define	RCC_CFGR_OFFSET 0x04U

#define	RCC_CIR_OFFSET 0x08U

#define	RCC_BDCR_OFFSET 0x20U

#define	RCC_CSR_OFFSET 0x24U

#define	RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)

#define	RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)

#define	RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)

#define	RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)

#define	RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)

#define	RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos

#define	RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))

#define	RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos

#define	RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))

#define	RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos

#define	RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))

#define	RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos

#define	RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))

#define	RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos

#define	RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))

#define	RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos

#define	RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))

#define	RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos

#define	RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))

#define	RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos

#define	RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))

#define	RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos

#define	RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))

#define	RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos

#define	RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))

#define	RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))

#define	RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))

#define	RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))

#define	CR_REG_INDEX ((uint8_t)1)

#define	BDCR_REG_INDEX ((uint8_t)2)

#define	CSR_REG_INDEX ((uint8_t)3)

#define	RCC_FLAG_MASK ((uint8_t)0x1F)

#define	__HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE

#define	__HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE

#define	__HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET

#define	__HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET

#define	IS_RCC_PLLSOURCE(__SOURCE__)

#define	IS_RCC_OSCILLATORTYPE(__OSCILLATOR__)

#define	IS_RCC_HSE(__HSE__)

#define	IS_RCC_LSE(__LSE__)

#define	IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))

#define	IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)

#define	IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))

#define	IS_RCC_PLL(__PLL__)

#define	IS_RCC_CLOCKTYPE(CLK)

#define	IS_RCC_SYSCLKSOURCE(__SOURCE__)

#define	IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__)

#define	IS_RCC_HCLK(__HCLK__)

#define	IS_RCC_PCLK(__PCLK__)

#define	IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)

#define	IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))

#define	IS_RCC_RTCCLKSOURCE(__SOURCE__)

Functions
HAL_StatusTypeDef	HAL_RCC_DeInit (void)

HAL_StatusTypeDef	HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)

HAL_StatusTypeDef	HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)

void	HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)

void	HAL_RCC_EnableCSS (void)

void	HAL_RCC_DisableCSS (void)

uint32_t	HAL_RCC_GetSysClockFreq (void)

uint32_t	HAL_RCC_GetHCLKFreq (void)

uint32_t	HAL_RCC_GetPCLK1Freq (void)

uint32_t	HAL_RCC_GetPCLK2Freq (void)

void	HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)

void	HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)

void	HAL_RCC_NMI_IRQHandler (void)

void	HAL_RCC_CSSCallback (void)

Detailed Description

Header file of RCC HAL module.

Author: MCD Application Team

Attention

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Definition in file stm32f1xx_hal_rcc.h.

Data Structures

Macros

Functions

Detailed Description

© Copyright (c) 2016 STMicroelectronics. All rights reserved.