TIM Timers. More...

#include <stm32f103xb.h>

Data Fields
__IO uint32_t	CR1

__IO uint32_t	CR2

__IO uint32_t	SMCR

__IO uint32_t	DIER

__IO uint32_t	SR

__IO uint32_t	EGR

__IO uint32_t	CCMR1

__IO uint32_t	CCMR2

__IO uint32_t	CCER

__IO uint32_t	CNT

__IO uint32_t	PSC

__IO uint32_t	ARR

__IO uint32_t	RCR

__IO uint32_t	CCR1

__IO uint32_t	CCR2

__IO uint32_t	CCR3

__IO uint32_t	CCR4

__IO uint32_t	BDTR

__IO uint32_t	DCR

__IO uint32_t	DMAR

__IO uint32_t	OR

Detailed Description

TIM Timers.

Definition at line 477 of file stm32f103xb.h.

Field Documentation

◆ ARR

__IO uint32_t TIM_TypeDef::ARR

TIM auto-reload register, Address offset: 0x2C

Definition at line 490 of file stm32f103xb.h.

◆ BDTR

__IO uint32_t TIM_TypeDef::BDTR

TIM break and dead-time register, Address offset: 0x44

Definition at line 496 of file stm32f103xb.h.

◆ CCER

__IO uint32_t TIM_TypeDef::CCER

TIM capture/compare enable register, Address offset: 0x20

Definition at line 487 of file stm32f103xb.h.

◆ CCMR1

__IO uint32_t TIM_TypeDef::CCMR1

TIM capture/compare mode register 1, Address offset: 0x18

Definition at line 485 of file stm32f103xb.h.

◆ CCMR2

__IO uint32_t TIM_TypeDef::CCMR2

TIM capture/compare mode register 2, Address offset: 0x1C

Definition at line 486 of file stm32f103xb.h.

◆ CCR1

__IO uint32_t TIM_TypeDef::CCR1

TIM capture/compare register 1, Address offset: 0x34

Definition at line 492 of file stm32f103xb.h.

◆ CCR2

__IO uint32_t TIM_TypeDef::CCR2

TIM capture/compare register 2, Address offset: 0x38

Definition at line 493 of file stm32f103xb.h.

◆ CCR3

__IO uint32_t TIM_TypeDef::CCR3

TIM capture/compare register 3, Address offset: 0x3C

Definition at line 494 of file stm32f103xb.h.

◆ CCR4

__IO uint32_t TIM_TypeDef::CCR4

TIM capture/compare register 4, Address offset: 0x40

Definition at line 495 of file stm32f103xb.h.

◆ CNT

__IO uint32_t TIM_TypeDef::CNT

TIM counter register, Address offset: 0x24

Definition at line 488 of file stm32f103xb.h.

◆ CR1

__IO uint32_t TIM_TypeDef::CR1

TIM control register 1, Address offset: 0x00

Definition at line 479 of file stm32f103xb.h.

◆ CR2

__IO uint32_t TIM_TypeDef::CR2

TIM control register 2, Address offset: 0x04

Definition at line 480 of file stm32f103xb.h.

◆ DCR

__IO uint32_t TIM_TypeDef::DCR

TIM DMA control register, Address offset: 0x48

Definition at line 497 of file stm32f103xb.h.

◆ DIER

__IO uint32_t TIM_TypeDef::DIER

TIM DMA/interrupt enable register, Address offset: 0x0C

Definition at line 482 of file stm32f103xb.h.

◆ DMAR

__IO uint32_t TIM_TypeDef::DMAR

TIM DMA address for full transfer register, Address offset: 0x4C

Definition at line 498 of file stm32f103xb.h.

◆ EGR

__IO uint32_t TIM_TypeDef::EGR

TIM event generation register, Address offset: 0x14

Definition at line 484 of file stm32f103xb.h.

◆ OR

__IO uint32_t TIM_TypeDef::OR

TIM option register, Address offset: 0x50

Definition at line 499 of file stm32f103xb.h.

◆ PSC

__IO uint32_t TIM_TypeDef::PSC

TIM prescaler register, Address offset: 0x28

Definition at line 489 of file stm32f103xb.h.

◆ RCR

__IO uint32_t TIM_TypeDef::RCR

TIM repetition counter register, Address offset: 0x30

Definition at line 491 of file stm32f103xb.h.

◆ SMCR

__IO uint32_t TIM_TypeDef::SMCR

TIM slave Mode Control register, Address offset: 0x08

Definition at line 481 of file stm32f103xb.h.

◆ SR

__IO uint32_t TIM_TypeDef::SR

TIM status register, Address offset: 0x10

Definition at line 483 of file stm32f103xb.h.

The documentation for this struct was generated from the following file:

STM32F103C8T6_powermeter-interface/Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h

Data Fields