DIY Logging Volt/Ampmeter
stm32f1xx_ll_tim.c
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1 /**
2  ******************************************************************************
3  * @file stm32f1xx_ll_tim.c
4  * @author MCD Application Team
5  * @brief TIM LL module driver.
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
10  * All rights reserved.</center></h2>
11  *
12  * This software component is licensed by ST under BSD 3-Clause license,
13  * the "License"; You may not use this file except in compliance with the
14  * License. You may obtain a copy of the License at:
15  * opensource.org/licenses/BSD-3-Clause
16  *
17  ******************************************************************************
18  */
19 #if defined(USE_FULL_LL_DRIVER)
20 
21 /* Includes ------------------------------------------------------------------*/
22 #include "stm32f1xx_ll_tim.h"
23 #include "stm32f1xx_ll_bus.h"
24 
25 #ifdef USE_FULL_ASSERT
26 #include "stm32_assert.h"
27 #else
28 #define assert_param(expr) ((void)0U)
29 #endif /* USE_FULL_ASSERT */
30 
31 /** @addtogroup STM32F1xx_LL_Driver
32  * @{
33  */
34 
35 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)
36 
37 /** @addtogroup TIM_LL
38  * @{
39  */
40 
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /* Private macros ------------------------------------------------------------*/
45 /** @addtogroup TIM_LL_Private_Macros
46  * @{
47  */
48 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
49  || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
50  || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
51  || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
52  || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
53 
54 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
55  || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
56  || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
57 
58 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
59  || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
60  || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
61  || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
62  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
63  || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
64  || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
65  || ((__VALUE__) == LL_TIM_OCMODE_PWM2))
66 
67 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
68  || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
69 
70 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
71  || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
72 
73 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
74  || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
75 
76 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
77  || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
78  || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
79 
80 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
81  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
82  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
83  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
84 
85 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
86  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
87  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
88  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
89  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
90  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
91  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
92  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
93  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
94  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
95  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
96  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
97  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
98  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
99  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
100  || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
101 
102 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
103  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
104 
105 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
106  || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
107  || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
108 
109 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
110  || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
111 
112 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
113  || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
114 
115 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
116  || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
117 
118 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
119  || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \
120  || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \
121  || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
122 
123 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
124  || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
125 
126 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
127  || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
128 
129 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
130  || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
131 /**
132  * @}
133  */
134 
135 
136 /* Private function prototypes -----------------------------------------------*/
137 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
138  * @{
139  */
140 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
141 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
142 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
143 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
144 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
145 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
146 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
147 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
148 /**
149  * @}
150  */
151 
152 /* Exported functions --------------------------------------------------------*/
153 /** @addtogroup TIM_LL_Exported_Functions
154  * @{
155  */
156 
157 /** @addtogroup TIM_LL_EF_Init
158  * @{
159  */
160 
161 /**
162  * @brief Set TIMx registers to their reset values.
163  * @param TIMx Timer instance
164  * @retval An ErrorStatus enumeration value:
165  * - SUCCESS: TIMx registers are de-initialized
166  * - ERROR: invalid TIMx instance
167  */
168 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
169 {
170  ErrorStatus result = SUCCESS;
171 
172  /* Check the parameters */
173  assert_param(IS_TIM_INSTANCE(TIMx));
174 
175  if (TIMx == TIM2)
176  {
177  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
178  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
179  }
180 #if defined(TIM1)
181  else if (TIMx == TIM1)
182  {
183  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
184  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
185  }
186 #endif
187 #if defined(TIM3)
188  else if (TIMx == TIM3)
189  {
190  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
191  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
192  }
193 #endif
194 #if defined(TIM4)
195  else if (TIMx == TIM4)
196  {
197  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
198  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
199  }
200 #endif
201 #if defined(TIM5)
202  else if (TIMx == TIM5)
203  {
204  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
205  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
206  }
207 #endif
208 #if defined(TIM6)
209  else if (TIMx == TIM6)
210  {
211  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
212  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
213  }
214 #endif
215 #if defined (TIM7)
216  else if (TIMx == TIM7)
217  {
218  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
219  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
220  }
221 #endif
222 #if defined(TIM8)
223  else if (TIMx == TIM8)
224  {
225  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
226  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
227  }
228 #endif
229 #if defined(TIM9)
230  else if (TIMx == TIM9)
231  {
232  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
233  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
234  }
235 #endif
236 #if defined(TIM10)
237  else if (TIMx == TIM10)
238  {
239  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
240  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
241  }
242 #endif
243 #if defined(TIM11)
244  else if (TIMx == TIM11)
245  {
246  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
247  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
248  }
249 #endif
250 #if defined(TIM12)
251  else if (TIMx == TIM12)
252  {
253  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
254  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
255  }
256 #endif
257 #if defined(TIM13)
258  else if (TIMx == TIM13)
259  {
260  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
261  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
262  }
263 #endif
264 #if defined(TIM14)
265  else if (TIMx == TIM14)
266  {
267  LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
268  LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
269  }
270 #endif
271 #if defined(TIM15)
272  else if (TIMx == TIM15)
273  {
274  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM15);
275  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM15);
276  }
277 #endif
278 #if defined(TIM16)
279  else if (TIMx == TIM16)
280  {
281  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM16);
282  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM16);
283  }
284 #endif
285 #if defined(TIM17)
286  else if (TIMx == TIM17)
287  {
288  LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM17);
289  LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM17);
290  }
291 #endif
292  else
293  {
294  result = ERROR;
295  }
296 
297  return result;
298 }
299 
300 /**
301  * @brief Set the fields of the time base unit configuration data structure
302  * to their default values.
303  * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
304  * @retval None
305  */
306 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
307 {
308  /* Set the default configuration */
309  TIM_InitStruct->Prescaler = (uint16_t)0x0000;
310  TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP;
311  TIM_InitStruct->Autoreload = 0xFFFFFFFFU;
312  TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1;
313  TIM_InitStruct->RepetitionCounter = 0x00000000U;
314 }
315 
316 /**
317  * @brief Configure the TIMx time base unit.
318  * @param TIMx Timer Instance
319  * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
320  * @retval An ErrorStatus enumeration value:
321  * - SUCCESS: TIMx registers are de-initialized
322  * - ERROR: not applicable
323  */
324 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
325 {
326  uint32_t tmpcr1;
327 
328  /* Check the parameters */
329  assert_param(IS_TIM_INSTANCE(TIMx));
330  assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
331  assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
332 
333  tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
334 
335  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
336  {
337  /* Select the Counter Mode */
338  MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
339  }
340 
341  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
342  {
343  /* Set the clock division */
344  MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
345  }
346 
347  /* Write to TIMx CR1 */
348  LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
349 
350  /* Set the Autoreload value */
351  LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
352 
353  /* Set the Prescaler value */
354  LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
355 
356  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
357  {
358  /* Set the Repetition Counter value */
359  LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
360  }
361 
362  /* Generate an update event to reload the Prescaler
363  and the repetition counter value (if applicable) immediately */
364  LL_TIM_GenerateEvent_UPDATE(TIMx);
365 
366  return SUCCESS;
367 }
368 
369 /**
370  * @brief Set the fields of the TIMx output channel configuration data
371  * structure to their default values.
372  * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
373  * @retval None
374  */
375 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
376 {
377  /* Set the default configuration */
378  TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN;
379  TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE;
380  TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE;
381  TIM_OC_InitStruct->CompareValue = 0x00000000U;
382  TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH;
383  TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH;
384  TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW;
385  TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
386 }
387 
388 /**
389  * @brief Configure the TIMx output channel.
390  * @param TIMx Timer Instance
391  * @param Channel This parameter can be one of the following values:
392  * @arg @ref LL_TIM_CHANNEL_CH1
393  * @arg @ref LL_TIM_CHANNEL_CH2
394  * @arg @ref LL_TIM_CHANNEL_CH3
395  * @arg @ref LL_TIM_CHANNEL_CH4
396  * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
397  * @retval An ErrorStatus enumeration value:
398  * - SUCCESS: TIMx output channel is initialized
399  * - ERROR: TIMx output channel is not initialized
400  */
401 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
402 {
403  ErrorStatus result = ERROR;
404 
405  switch (Channel)
406  {
407  case LL_TIM_CHANNEL_CH1:
408  result = OC1Config(TIMx, TIM_OC_InitStruct);
409  break;
410  case LL_TIM_CHANNEL_CH2:
411  result = OC2Config(TIMx, TIM_OC_InitStruct);
412  break;
413  case LL_TIM_CHANNEL_CH3:
414  result = OC3Config(TIMx, TIM_OC_InitStruct);
415  break;
416  case LL_TIM_CHANNEL_CH4:
417  result = OC4Config(TIMx, TIM_OC_InitStruct);
418  break;
419  default:
420  break;
421  }
422 
423  return result;
424 }
425 
426 /**
427  * @brief Set the fields of the TIMx input channel configuration data
428  * structure to their default values.
429  * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
430  * @retval None
431  */
432 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
433 {
434  /* Set the default configuration */
435  TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING;
436  TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
437  TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1;
438  TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1;
439 }
440 
441 /**
442  * @brief Configure the TIMx input channel.
443  * @param TIMx Timer Instance
444  * @param Channel This parameter can be one of the following values:
445  * @arg @ref LL_TIM_CHANNEL_CH1
446  * @arg @ref LL_TIM_CHANNEL_CH2
447  * @arg @ref LL_TIM_CHANNEL_CH3
448  * @arg @ref LL_TIM_CHANNEL_CH4
449  * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
450  * @retval An ErrorStatus enumeration value:
451  * - SUCCESS: TIMx output channel is initialized
452  * - ERROR: TIMx output channel is not initialized
453  */
454 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
455 {
456  ErrorStatus result = ERROR;
457 
458  switch (Channel)
459  {
460  case LL_TIM_CHANNEL_CH1:
461  result = IC1Config(TIMx, TIM_IC_InitStruct);
462  break;
463  case LL_TIM_CHANNEL_CH2:
464  result = IC2Config(TIMx, TIM_IC_InitStruct);
465  break;
466  case LL_TIM_CHANNEL_CH3:
467  result = IC3Config(TIMx, TIM_IC_InitStruct);
468  break;
469  case LL_TIM_CHANNEL_CH4:
470  result = IC4Config(TIMx, TIM_IC_InitStruct);
471  break;
472  default:
473  break;
474  }
475 
476  return result;
477 }
478 
479 /**
480  * @brief Fills each TIM_EncoderInitStruct field with its default value
481  * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
482  * @retval None
483  */
484 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
485 {
486  /* Set the default configuration */
487  TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1;
488  TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
489  TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
490  TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
491  TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
492  TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING;
493  TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
494  TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1;
495  TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1;
496 }
497 
498 /**
499  * @brief Configure the encoder interface of the timer instance.
500  * @param TIMx Timer Instance
501  * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
502  * @retval An ErrorStatus enumeration value:
503  * - SUCCESS: TIMx registers are de-initialized
504  * - ERROR: not applicable
505  */
506 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
507 {
508  uint32_t tmpccmr1;
509  uint32_t tmpccer;
510 
511  /* Check the parameters */
512  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
513  assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
514  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
515  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
516  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
517  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
518  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
519  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
520  assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
521  assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
522 
523  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
524  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
525 
526  /* Get the TIMx CCMR1 register value */
527  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
528 
529  /* Get the TIMx CCER register value */
530  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
531 
532  /* Configure TI1 */
533  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
534  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
535  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
536  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
537 
538  /* Configure TI2 */
539  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC);
540  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
541  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
542  tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
543 
544  /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
545  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
546  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
547  tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
548  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
549 
550  /* Set encoder mode */
551  LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
552 
553  /* Write to TIMx CCMR1 */
554  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
555 
556  /* Write to TIMx CCER */
557  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
558 
559  return SUCCESS;
560 }
561 
562 /**
563  * @brief Set the fields of the TIMx Hall sensor interface configuration data
564  * structure to their default values.
565  * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
566  * @retval None
567  */
568 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
569 {
570  /* Set the default configuration */
571  TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING;
572  TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1;
573  TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1;
574  TIM_HallSensorInitStruct->CommutationDelay = 0U;
575 }
576 
577 /**
578  * @brief Configure the Hall sensor interface of the timer instance.
579  * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
580  * to the TI1 input channel
581  * @note TIMx slave mode controller is configured in reset mode.
582  Selected internal trigger is TI1F_ED.
583  * @note Channel 1 is configured as input, IC1 is mapped on TRC.
584  * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
585  * between 2 changes on the inputs. It gives information about motor speed.
586  * @note Channel 2 is configured in output PWM 2 mode.
587  * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
588  * @note OC2REF is selected as trigger output on TRGO.
589  * @param TIMx Timer Instance
590  * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
591  * @retval An ErrorStatus enumeration value:
592  * - SUCCESS: TIMx registers are de-initialized
593  * - ERROR: not applicable
594  */
595 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
596 {
597  uint32_t tmpcr2;
598  uint32_t tmpccmr1;
599  uint32_t tmpccer;
600  uint32_t tmpsmcr;
601 
602  /* Check the parameters */
603  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
604  assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
605  assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
606  assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
607 
608  /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
609  TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
610 
611  /* Get the TIMx CR2 register value */
612  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
613 
614  /* Get the TIMx CCMR1 register value */
615  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
616 
617  /* Get the TIMx CCER register value */
618  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
619 
620  /* Get the TIMx SMCR register value */
621  tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
622 
623  /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
624  tmpcr2 |= TIM_CR2_TI1S;
625 
626  /* OC2REF signal is used as trigger output (TRGO) */
627  tmpcr2 |= LL_TIM_TRGO_OC2REF;
628 
629  /* Configure the slave mode controller */
630  tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
631  tmpsmcr |= LL_TIM_TS_TI1F_ED;
632  tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
633 
634  /* Configure input channel 1 */
635  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC);
636  tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
637  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
638  tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
639 
640  /* Configure input channel 2 */
641  tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE);
642  tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
643 
644  /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
645  tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
646  tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
647  tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
648 
649  /* Write to TIMx CR2 */
650  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
651 
652  /* Write to TIMx SMCR */
653  LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
654 
655  /* Write to TIMx CCMR1 */
656  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
657 
658  /* Write to TIMx CCER */
659  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
660 
661  /* Write to TIMx CCR2 */
662  LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
663 
664  return SUCCESS;
665 }
666 
667 /**
668  * @brief Set the fields of the Break and Dead Time configuration data structure
669  * to their default values.
670  * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
671  * @retval None
672  */
673 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
674 {
675  /* Set the default configuration */
676  TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE;
677  TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE;
678  TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF;
679  TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00;
680  TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE;
681  TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW;
682  TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
683 }
684 
685 /**
686  * @brief Configure the Break and Dead Time feature of the timer instance.
687  * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked
688  * depending on the LOCK configuration, it can be necessary to configure all of
689  * them during the first write access to the TIMx_BDTR register.
690  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
691  * a timer instance provides a break input.
692  * @param TIMx Timer Instance
693  * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
694  * @retval An ErrorStatus enumeration value:
695  * - SUCCESS: Break and Dead Time is initialized
696  * - ERROR: not applicable
697  */
698 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
699 {
700  uint32_t tmpbdtr = 0;
701 
702  /* Check the parameters */
703  assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
704  assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
705  assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
706  assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
707  assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
708  assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
709  assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
710 
711  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
712  the OSSI State, the dead time value and the Automatic Output Enable Bit */
713 
714  /* Set the BDTR bits */
715  MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
716  MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
717  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
718  MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
719  MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
720  MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
721  MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
722  MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
723 
724  /* Set TIMx_BDTR */
725  LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
726 
727  return SUCCESS;
728 }
729 /**
730  * @}
731  */
732 
733 /**
734  * @}
735  */
736 
737 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
738  * @brief Private functions
739  * @{
740  */
741 /**
742  * @brief Configure the TIMx output channel 1.
743  * @param TIMx Timer Instance
744  * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
745  * @retval An ErrorStatus enumeration value:
746  * - SUCCESS: TIMx registers are de-initialized
747  * - ERROR: not applicable
748  */
749 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
750 {
751  uint32_t tmpccmr1;
752  uint32_t tmpccer;
753  uint32_t tmpcr2;
754 
755  /* Check the parameters */
756  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
757  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
758  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
759  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
760  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
761  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
762 
763  /* Disable the Channel 1: Reset the CC1E Bit */
764  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
765 
766  /* Get the TIMx CCER register value */
767  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
768 
769  /* Get the TIMx CR2 register value */
770  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
771 
772  /* Get the TIMx CCMR1 register value */
773  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
774 
775  /* Reset Capture/Compare selection Bits */
776  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
777 
778  /* Set the Output Compare Mode */
779  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
780 
781  /* Set the Output Compare Polarity */
782  MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
783 
784  /* Set the Output State */
785  MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
786 
787  if (IS_TIM_BREAK_INSTANCE(TIMx))
788  {
789  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
790  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
791 
792  /* Set the complementary output Polarity */
793  MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
794 
795  /* Set the complementary output State */
796  MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
797 
798  /* Set the Output Idle state */
799  MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
800 
801  /* Set the complementary output Idle state */
802  MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
803  }
804 
805  /* Write to TIMx CR2 */
806  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
807 
808  /* Write to TIMx CCMR1 */
809  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
810 
811  /* Set the Capture Compare Register value */
812  LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
813 
814  /* Write to TIMx CCER */
815  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
816 
817  return SUCCESS;
818 }
819 
820 /**
821  * @brief Configure the TIMx output channel 2.
822  * @param TIMx Timer Instance
823  * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
824  * @retval An ErrorStatus enumeration value:
825  * - SUCCESS: TIMx registers are de-initialized
826  * - ERROR: not applicable
827  */
828 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
829 {
830  uint32_t tmpccmr1;
831  uint32_t tmpccer;
832  uint32_t tmpcr2;
833 
834  /* Check the parameters */
835  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
836  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
837  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
838  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
839  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
840  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
841 
842  /* Disable the Channel 2: Reset the CC2E Bit */
843  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
844 
845  /* Get the TIMx CCER register value */
846  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
847 
848  /* Get the TIMx CR2 register value */
849  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
850 
851  /* Get the TIMx CCMR1 register value */
852  tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
853 
854  /* Reset Capture/Compare selection Bits */
855  CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
856 
857  /* Select the Output Compare Mode */
858  MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
859 
860  /* Set the Output Compare Polarity */
861  MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
862 
863  /* Set the Output State */
864  MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
865 
866  if (IS_TIM_BREAK_INSTANCE(TIMx))
867  {
868  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
869  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
870 
871  /* Set the complementary output Polarity */
872  MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
873 
874  /* Set the complementary output State */
875  MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
876 
877  /* Set the Output Idle state */
878  MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
879 
880  /* Set the complementary output Idle state */
881  MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
882  }
883 
884  /* Write to TIMx CR2 */
885  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
886 
887  /* Write to TIMx CCMR1 */
888  LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
889 
890  /* Set the Capture Compare Register value */
891  LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
892 
893  /* Write to TIMx CCER */
894  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
895 
896  return SUCCESS;
897 }
898 
899 /**
900  * @brief Configure the TIMx output channel 3.
901  * @param TIMx Timer Instance
902  * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
903  * @retval An ErrorStatus enumeration value:
904  * - SUCCESS: TIMx registers are de-initialized
905  * - ERROR: not applicable
906  */
907 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
908 {
909  uint32_t tmpccmr2;
910  uint32_t tmpccer;
911  uint32_t tmpcr2;
912 
913  /* Check the parameters */
914  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
915  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
916  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
917  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
918  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
919  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
920 
921  /* Disable the Channel 3: Reset the CC3E Bit */
922  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
923 
924  /* Get the TIMx CCER register value */
925  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
926 
927  /* Get the TIMx CR2 register value */
928  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
929 
930  /* Get the TIMx CCMR2 register value */
931  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
932 
933  /* Reset Capture/Compare selection Bits */
934  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
935 
936  /* Select the Output Compare Mode */
937  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
938 
939  /* Set the Output Compare Polarity */
940  MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
941 
942  /* Set the Output State */
943  MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
944 
945  if (IS_TIM_BREAK_INSTANCE(TIMx))
946  {
947  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
948  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
949 
950  /* Set the complementary output Polarity */
951  MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
952 
953  /* Set the complementary output State */
954  MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
955 
956  /* Set the Output Idle state */
957  MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
958 
959  /* Set the complementary output Idle state */
960  MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
961  }
962 
963  /* Write to TIMx CR2 */
964  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
965 
966  /* Write to TIMx CCMR2 */
967  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
968 
969  /* Set the Capture Compare Register value */
970  LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
971 
972  /* Write to TIMx CCER */
973  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
974 
975  return SUCCESS;
976 }
977 
978 /**
979  * @brief Configure the TIMx output channel 4.
980  * @param TIMx Timer Instance
981  * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
982  * @retval An ErrorStatus enumeration value:
983  * - SUCCESS: TIMx registers are de-initialized
984  * - ERROR: not applicable
985  */
986 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
987 {
988  uint32_t tmpccmr2;
989  uint32_t tmpccer;
990  uint32_t tmpcr2;
991 
992  /* Check the parameters */
993  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
994  assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
995  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
996  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
997  assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
998  assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
999 
1000  /* Disable the Channel 4: Reset the CC4E Bit */
1001  CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1002 
1003  /* Get the TIMx CCER register value */
1004  tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1005 
1006  /* Get the TIMx CR2 register value */
1007  tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1008 
1009  /* Get the TIMx CCMR2 register value */
1010  tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1011 
1012  /* Reset Capture/Compare selection Bits */
1013  CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1014 
1015  /* Select the Output Compare Mode */
1016  MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1017 
1018  /* Set the Output Compare Polarity */
1019  MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1020 
1021  /* Set the Output State */
1022  MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1023 
1024  if (IS_TIM_BREAK_INSTANCE(TIMx))
1025  {
1026  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1027  assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1028 
1029  /* Set the Output Idle state */
1030  MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1031  }
1032 
1033  /* Write to TIMx CR2 */
1034  LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1035 
1036  /* Write to TIMx CCMR2 */
1037  LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1038 
1039  /* Set the Capture Compare Register value */
1040  LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1041 
1042  /* Write to TIMx CCER */
1043  LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1044 
1045  return SUCCESS;
1046 }
1047 
1048 
1049 /**
1050  * @brief Configure the TIMx input channel 1.
1051  * @param TIMx Timer Instance
1052  * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1053  * @retval An ErrorStatus enumeration value:
1054  * - SUCCESS: TIMx registers are de-initialized
1055  * - ERROR: not applicable
1056  */
1057 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1058 {
1059  /* Check the parameters */
1060  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1061  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1062  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1063  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1064  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1065 
1066  /* Disable the Channel 1: Reset the CC1E Bit */
1067  TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1068 
1069  /* Select the Input and set the filter and the prescaler value */
1070  MODIFY_REG(TIMx->CCMR1,
1071  (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1072  (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1073 
1074  /* Select the Polarity and set the CC1E Bit */
1075  MODIFY_REG(TIMx->CCER,
1076  (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1077  (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1078 
1079  return SUCCESS;
1080 }
1081 
1082 /**
1083  * @brief Configure the TIMx input channel 2.
1084  * @param TIMx Timer Instance
1085  * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1086  * @retval An ErrorStatus enumeration value:
1087  * - SUCCESS: TIMx registers are de-initialized
1088  * - ERROR: not applicable
1089  */
1090 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1091 {
1092  /* Check the parameters */
1093  assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1094  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1095  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1096  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1097  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1098 
1099  /* Disable the Channel 2: Reset the CC2E Bit */
1100  TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1101 
1102  /* Select the Input and set the filter and the prescaler value */
1103  MODIFY_REG(TIMx->CCMR1,
1104  (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1105  (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1106 
1107  /* Select the Polarity and set the CC2E Bit */
1108  MODIFY_REG(TIMx->CCER,
1109  (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1110  ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1111 
1112  return SUCCESS;
1113 }
1114 
1115 /**
1116  * @brief Configure the TIMx input channel 3.
1117  * @param TIMx Timer Instance
1118  * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1119  * @retval An ErrorStatus enumeration value:
1120  * - SUCCESS: TIMx registers are de-initialized
1121  * - ERROR: not applicable
1122  */
1123 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1124 {
1125  /* Check the parameters */
1126  assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1127  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1128  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1129  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1130  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1131 
1132  /* Disable the Channel 3: Reset the CC3E Bit */
1133  TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1134 
1135  /* Select the Input and set the filter and the prescaler value */
1136  MODIFY_REG(TIMx->CCMR2,
1137  (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1138  (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1139 
1140  /* Select the Polarity and set the CC3E Bit */
1141  MODIFY_REG(TIMx->CCER,
1142  (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1143  ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1144 
1145  return SUCCESS;
1146 }
1147 
1148 /**
1149  * @brief Configure the TIMx input channel 4.
1150  * @param TIMx Timer Instance
1151  * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1152  * @retval An ErrorStatus enumeration value:
1153  * - SUCCESS: TIMx registers are de-initialized
1154  * - ERROR: not applicable
1155  */
1156 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1157 {
1158  /* Check the parameters */
1159  assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1160  assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1161  assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1162  assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1163  assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1164 
1165  /* Disable the Channel 4: Reset the CC4E Bit */
1166  TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1167 
1168  /* Select the Input and set the filter and the prescaler value */
1169  MODIFY_REG(TIMx->CCMR2,
1170  (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1171  (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1172 
1173  /* Select the Polarity and set the CC4E Bit */
1174  MODIFY_REG(TIMx->CCER,
1175  TIM_CCER_CC4P,
1176  ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1177 
1178  return SUCCESS;
1179 }
1180 
1181 
1182 /**
1183  * @}
1184  */
1185 
1186 /**
1187  * @}
1188  */
1189 
1190 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
1191 
1192 /**
1193  * @}
1194  */
1195 
1196 #endif /* USE_FULL_LL_DRIVER */
1197 
1198 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
TIM_CR2_OIS1N
#define TIM_CR2_OIS1N
Definition: stm32f103xb.h:3863
TIM_CCER_CC1P
#define TIM_CCER_CC1P
Definition: stm32f103xb.h:4195
IS_TIM_CC1_INSTANCE
#define IS_TIM_CC1_INSTANCE(INSTANCE)
Definition: stm32f103xb.h:9944
IS_TIM_ENCODER_INTERFACE_INSTANCE
#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)
Definition: stm32f103xb.h:9998
TIM_CCMR1_OC2M
#define TIM_CCMR1_OC2M
Definition: stm32f103xb.h:4071
ERROR
@ ERROR
Definition: stm32f1xx.h:167
TIM_SMCR_SMS
#define TIM_SMCR_SMS
Definition: stm32f103xb.h:3883
TIM_CR2_OIS2N
#define TIM_CR2_OIS2N
Definition: stm32f103xb.h:3869
TIM_CCMR1_OC2FE
#define TIM_CCMR1_OC2FE
Definition: stm32f103xb.h:4064
TIM_CR1_CMS
#define TIM_CR1_CMS
Definition: stm32f103xb.h:3823
TIM_CCER_CC3NE
#define TIM_CCER_CC3NE
Definition: stm32f103xb.h:4222
TIM_CR1_CKD
#define TIM_CR1_CKD
Definition: stm32f103xb.h:3833
TIM_CCER_CC1E
#define TIM_CCER_CC1E
Definition: stm32f103xb.h:4192
TIM_CCMR1_OC1M
#define TIM_CCMR1_OC1M
Definition: stm32f103xb.h:4047
IS_TIM_CC2_INSTANCE
#define IS_TIM_CC2_INSTANCE(INSTANCE)
Definition: stm32f103xb.h:9950
IS_TIM_CC3_INSTANCE
#define IS_TIM_CC3_INSTANCE(INSTANCE)
Definition: stm32f103xb.h:9956
TIM_CCMR2_IC3F
#define TIM_CCMR2_IC3F
Definition: stm32f103xb.h:4169
TIM_CCER_CC3NP
#define TIM_CCER_CC3NP
Definition: stm32f103xb.h:4225
TIM_TypeDef::CCER
__IO uint32_t CCER
Definition: stm32f103xb.h:487
stm32f1xx_ll_bus.h
Header file of BUS LL module.
TIM_CCER_CC3E
#define TIM_CCER_CC3E
Definition: stm32f103xb.h:4216
TIM3
#define TIM3
Definition: stm32f103xb.h:649
TIM_CR2_OIS3
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Definition: stm32f103xb.h:3872
TIM_BDTR_MOE
#define TIM_BDTR_MOE
Definition: stm32f103xb.h:4309
stm32f1xx_ll_tim.h
Header file of TIM LL module.
assert_param
#define assert_param(expr)
Definition: stm32_assert.h:44
TIM_CR2_OIS3N
#define TIM_CR2_OIS3N
Definition: stm32f103xb.h:3875
TIM_CCER_CC4P
#define TIM_CCER_CC4P
Definition: stm32f103xb.h:4231
TIM_TypeDef
TIM Timers.
Definition: stm32f103xb.h:477
TIM_CCMR1_OC2CE
#define TIM_CCMR1_OC2CE
Definition: stm32f103xb.h:4078
TIM_CCMR2_IC3PSC
#define TIM_CCMR2_IC3PSC
Definition: stm32f103xb.h:4163
TIM_CCER_CC2NE
#define TIM_CCER_CC2NE
Definition: stm32f103xb.h:4210
TIM2
#define TIM2
Definition: stm32f103xb.h:648
stm32_assert.h
STM32 assert file.
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#define TIM4
Definition: stm32f103xb.h:650
TIM_CCMR1_CC1S
#define TIM_CCMR1_CC1S
Definition: stm32f103xb.h:4034
TIM_CCMR2_CC3S
#define TIM_CCMR2_CC3S
Definition: stm32f103xb.h:4113
TIM_CCER_CC2NP
#define TIM_CCER_CC2NP
Definition: stm32f103xb.h:4213
TIM_BDTR_OSSI
#define TIM_BDTR_OSSI
Definition: stm32f103xb.h:4294
MODIFY_REG
#define MODIFY_REG(REG, CLEARMASK, SETMASK)
Definition: stm32f1xx.h:190
TIM_CCMR2_OC4M
#define TIM_CCMR2_OC4M
Definition: stm32f103xb.h:4150
TIM_CCMR2_IC4PSC
#define TIM_CCMR2_IC4PSC
Definition: stm32f103xb.h:4177
TIM_CCMR1_OC2PE
#define TIM_CCMR1_OC2PE
Definition: stm32f103xb.h:4067
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#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)
Definition: stm32f103xb.h:10071
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Definition: stm32f103xb.h:4204
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Definition: stm32f103xb.h:10028
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Definition: stm32f103xb.h:4058
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Definition: stm32f103xb.h:4090
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#define TIM_CR2_TI1S
Definition: stm32f103xb.h:3857
TIM_TypeDef::CCMR2
__IO uint32_t CCMR2
Definition: stm32f103xb.h:486
TIM_CR2_OIS2
#define TIM_CR2_OIS2
Definition: stm32f103xb.h:3866
TIM1
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Definition: stm32f103xb.h:4297
TIM_CCER_CC4E
#define TIM_CCER_CC4E
Definition: stm32f103xb.h:4228
TIM_TypeDef::CCMR1
__IO uint32_t CCMR1
Definition: stm32f103xb.h:485
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#define TIM_BDTR_BKE
Definition: stm32f103xb.h:4300
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Definition: stm32f103xb.h:3860
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Definition: stm32f103xb.h:4198
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Definition: stm32f103xb.h:9936
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Definition: stm32f103xb.h:9962
SUCCESS
@ SUCCESS
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Definition: stm32f103xb.h:4207
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Definition: stm32f103xb.h:4126
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Definition: stm32f103xb.h:4201
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Definition: stm32f103xb.h:4183
TIM_CCER_CC3P
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Definition: stm32f103xb.h:4219
CLEAR_BIT
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Definition: stm32f1xx.h:180
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Definition: stm32f103xb.h:10068
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Definition: stm32f103xb.h:10097
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Definition: stm32f103xb.h:3890
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Definition: stm32f103xb.h:4276
ErrorStatus
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Definition: stm32f103xb.h:4288