Header file of BUS LL module. 
- Author
 - MCD Application Team 
                    ##### RCC Limitations #####
==============================================================================
  [..]
    A delay between an RCC peripheral clock enable and the effective peripheral
    enabling should be taken into account in order to manage the peripheral read/write
    from/to registers.
    (+) This delay depends on the peripheral mapping.
      (++) AHB & APB peripherals, 1 dummy read is necessary
  [..]
    Workarounds:
    (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
        inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 
- Attention
 
© Copyright (c) 2016 STMicroelectronics. All rights reserved.
This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause 
Definition in file stm32f1xx_ll_bus.h.