DIY Logging Volt/Ampmeter
stm32f1xx_ll_adc.h
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1 /**
2  ******************************************************************************
3  * @file stm32f1xx_ll_adc.h
4  * @author MCD Application Team
5  * @brief Header file of ADC LL module.
6  ******************************************************************************
7  * @attention
8  *
9  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10  * All rights reserved.</center></h2>
11  *
12  * This software component is licensed by ST under BSD 3-Clause license,
13  * the "License"; You may not use this file except in compliance with the
14  * License. You may obtain a copy of the License at:
15  * opensource.org/licenses/BSD-3-Clause
16  *
17  ******************************************************************************
18  */
19 
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32F1xx_LL_ADC_H
22 #define __STM32F1xx_LL_ADC_H
23 
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27 
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32f1xx.h"
30 
31 /** @addtogroup STM32F1xx_LL_Driver
32  * @{
33  */
34 
35 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
36 
37 /** @defgroup ADC_LL ADC
38  * @{
39  */
40 
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 
44 /* Private constants ---------------------------------------------------------*/
45 /** @defgroup ADC_LL_Private_Constants ADC Private Constants
46  * @{
47  */
48 
49 /* Internal mask for ADC group regular sequencer: */
50 /* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */
51 /* - sequencer register offset */
52 /* - sequencer rank bits position into the selected register */
53 
54 /* Internal register offset for ADC group regular sequencer configuration */
55 /* (offset placed into a spare area of literal definition) */
56 #define ADC_SQR1_REGOFFSET 0x00000000U
57 #define ADC_SQR2_REGOFFSET 0x00000100U
58 #define ADC_SQR3_REGOFFSET 0x00000200U
59 #define ADC_SQR4_REGOFFSET 0x00000300U
60 
61 #define ADC_REG_SQRX_REGOFFSET_MASK (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
62 #define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
63 
64 /* Definition of ADC group regular sequencer bits information to be inserted */
65 /* into ADC group regular sequencer ranks literals definition. */
66 #define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ1) */
67 #define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ2) */
68 #define ADC_REG_RANK_3_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ3) */
69 #define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ4) */
70 #define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ5) */
71 #define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR3_SQ6) */
72 #define ADC_REG_RANK_7_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ7) */
73 #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ8) */
74 #define ADC_REG_RANK_9_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ9) */
75 #define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ10) */
76 #define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ11) */
77 #define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (25U) /* Value equivalent to POSITION_VAL(ADC_SQR2_SQ12) */
78 #define ADC_REG_RANK_13_SQRX_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ13) */
79 #define ADC_REG_RANK_14_SQRX_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ14) */
80 #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ15) */
81 #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (15U) /* Value equivalent to POSITION_VAL(ADC_SQR1_SQ16) */
82 
83 /* Internal mask for ADC group injected sequencer: */
84 /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */
85 /* - data register offset */
86 /* - offset register offset */
87 /* - sequencer rank bits position into the selected register */
88 
89 /* Internal register offset for ADC group injected data register */
90 /* (offset placed into a spare area of literal definition) */
91 #define ADC_JDR1_REGOFFSET 0x00000000U
92 #define ADC_JDR2_REGOFFSET 0x00000100U
93 #define ADC_JDR3_REGOFFSET 0x00000200U
94 #define ADC_JDR4_REGOFFSET 0x00000300U
95 
96 /* Internal register offset for ADC group injected offset configuration */
97 /* (offset placed into a spare area of literal definition) */
98 #define ADC_JOFR1_REGOFFSET 0x00000000U
99 #define ADC_JOFR2_REGOFFSET 0x00001000U
100 #define ADC_JOFR3_REGOFFSET 0x00002000U
101 #define ADC_JOFR4_REGOFFSET 0x00003000U
102 
103 #define ADC_INJ_JDRX_REGOFFSET_MASK (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
104 #define ADC_INJ_JOFRX_REGOFFSET_MASK (ADC_JOFR1_REGOFFSET | ADC_JOFR2_REGOFFSET | ADC_JOFR3_REGOFFSET | ADC_JOFR4_REGOFFSET)
105 #define ADC_INJ_RANK_ID_JSQR_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
106 
107 /* Internal mask for ADC channel: */
108 /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */
109 /* - channel identifier defined by number */
110 /* - channel differentiation between external channels (connected to */
111 /* GPIO pins) and internal channels (connected to internal paths) */
112 /* - channel sampling time defined by SMPRx register offset */
113 /* and SMPx bits positions into SMPRx register */
114 #define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CR1_AWDCH)
115 #define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS ( 0U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */
116 #define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
117 /* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
118 #define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 0x0000001FU /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */
119 
120 /* Channel differentiation between external and internal channels */
121 #define ADC_CHANNEL_ID_INTERNAL_CH 0x80000000U /* Marker of internal channel */
122 #define ADC_CHANNEL_ID_INTERNAL_CH_2 0x40000000U /* Marker of internal channel for other ADC instances, in case of different ADC internal channels mapped on same channel number on different ADC instances */
123 #define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
124 
125 /* Internal register offset for ADC channel sampling time configuration */
126 /* (offset placed into a spare area of literal definition) */
127 #define ADC_SMPR1_REGOFFSET 0x00000000U
128 #define ADC_SMPR2_REGOFFSET 0x02000000U
129 #define ADC_CHANNEL_SMPRX_REGOFFSET_MASK (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
130 
131 #define ADC_CHANNEL_SMPx_BITOFFSET_MASK 0x01F00000U
132 #define ADC_CHANNEL_SMPx_BITOFFSET_POS (20U) /* Value equivalent to POSITION_VAL(ADC_CHANNEL_SMPx_BITOFFSET_MASK) */
133 
134 /* Definition of channels ID number information to be inserted into */
135 /* channels literals definition. */
136 #define ADC_CHANNEL_0_NUMBER 0x00000000U
137 #define ADC_CHANNEL_1_NUMBER ( ADC_CR1_AWDCH_0)
138 #define ADC_CHANNEL_2_NUMBER ( ADC_CR1_AWDCH_1 )
139 #define ADC_CHANNEL_3_NUMBER ( ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
140 #define ADC_CHANNEL_4_NUMBER ( ADC_CR1_AWDCH_2 )
141 #define ADC_CHANNEL_5_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
142 #define ADC_CHANNEL_6_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
143 #define ADC_CHANNEL_7_NUMBER ( ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
144 #define ADC_CHANNEL_8_NUMBER ( ADC_CR1_AWDCH_3 )
145 #define ADC_CHANNEL_9_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0)
146 #define ADC_CHANNEL_10_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 )
147 #define ADC_CHANNEL_11_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
148 #define ADC_CHANNEL_12_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 )
149 #define ADC_CHANNEL_13_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0)
150 #define ADC_CHANNEL_14_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 )
151 #define ADC_CHANNEL_15_NUMBER ( ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0)
152 #define ADC_CHANNEL_16_NUMBER (ADC_CR1_AWDCH_4 )
153 #define ADC_CHANNEL_17_NUMBER (ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0)
154 
155 /* Definition of channels sampling time information to be inserted into */
156 /* channels literals definition. */
157 #define ADC_CHANNEL_0_SMP (ADC_SMPR2_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP0) */
158 #define ADC_CHANNEL_1_SMP (ADC_SMPR2_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP1) */
159 #define ADC_CHANNEL_2_SMP (ADC_SMPR2_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP2) */
160 #define ADC_CHANNEL_3_SMP (ADC_SMPR2_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP3) */
161 #define ADC_CHANNEL_4_SMP (ADC_SMPR2_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP4) */
162 #define ADC_CHANNEL_5_SMP (ADC_SMPR2_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP5) */
163 #define ADC_CHANNEL_6_SMP (ADC_SMPR2_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP6) */
164 #define ADC_CHANNEL_7_SMP (ADC_SMPR2_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP7) */
165 #define ADC_CHANNEL_8_SMP (ADC_SMPR2_REGOFFSET | ((24U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP8) */
166 #define ADC_CHANNEL_9_SMP (ADC_SMPR2_REGOFFSET | ((27U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR2_SMP9) */
167 #define ADC_CHANNEL_10_SMP (ADC_SMPR1_REGOFFSET | (( 0U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP10) */
168 #define ADC_CHANNEL_11_SMP (ADC_SMPR1_REGOFFSET | (( 3U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP11) */
169 #define ADC_CHANNEL_12_SMP (ADC_SMPR1_REGOFFSET | (( 6U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP12) */
170 #define ADC_CHANNEL_13_SMP (ADC_SMPR1_REGOFFSET | (( 9U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP13) */
171 #define ADC_CHANNEL_14_SMP (ADC_SMPR1_REGOFFSET | ((12U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP14) */
172 #define ADC_CHANNEL_15_SMP (ADC_SMPR1_REGOFFSET | ((15U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP15) */
173 #define ADC_CHANNEL_16_SMP (ADC_SMPR1_REGOFFSET | ((18U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP16) */
174 #define ADC_CHANNEL_17_SMP (ADC_SMPR1_REGOFFSET | ((21U) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to POSITION_VAL(ADC_SMPR1_SMP17) */
175 
176 /* Internal mask for ADC analog watchdog: */
177 /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */
178 /* (concatenation of multiple bits used in different analog watchdogs, */
179 /* (feature of several watchdogs not available on all STM32 families)). */
180 /* - analog watchdog 1: monitored channel defined by number, */
181 /* selection of ADC group (ADC groups regular and-or injected). */
182 
183 /* Internal register offset for ADC analog watchdog channel configuration */
184 #define ADC_AWD_CR1_REGOFFSET 0x00000000U
185 
186 #define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET)
187 
188 #define ADC_AWD_CR1_CHANNEL_MASK (ADC_CR1_AWDCH | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL)
189 #define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK)
190 
191 /* Internal register offset for ADC analog watchdog threshold configuration */
192 #define ADC_AWD_TR1_HIGH_REGOFFSET 0x00000000U
193 #define ADC_AWD_TR1_LOW_REGOFFSET 0x00000001U
194 #define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_HIGH_REGOFFSET | ADC_AWD_TR1_LOW_REGOFFSET)
195 
196 /* ADC registers bits positions */
197 #define ADC_CR1_DUALMOD_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_CR1_DUALMOD) */
198 
199 /**
200  * @}
201  */
202 
203 
204 /* Private macros ------------------------------------------------------------*/
205 /** @defgroup ADC_LL_Private_Macros ADC Private Macros
206  * @{
207  */
208 
209 /**
210  * @brief Driver macro reserved for internal use: isolate bits with the
211  * selected mask and shift them to the register LSB
212  * (shift mask on register position bit 0).
213  * @param __BITS__ Bits in register 32 bits
214  * @param __MASK__ Mask in register 32 bits
215  * @retval Bits in register 32 bits
216  */
217 #define __ADC_MASK_SHIFT(__BITS__, __MASK__) \
218  (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__)))
219 
220 /**
221  * @brief Driver macro reserved for internal use: set a pointer to
222  * a register from a register basis from which an offset
223  * is applied.
224  * @param __REG__ Register basis from which the offset is applied.
225  * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
226  * @retval Pointer to register address
227  */
228 #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
229  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
230 
231 /**
232  * @}
233  */
234 
235 
236 /* Exported types ------------------------------------------------------------*/
237 #if defined(USE_FULL_LL_DRIVER)
238 /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
239  * @{
240  */
241 
242 /**
243  * @brief Structure definition of some features of ADC common parameters
244  * and multimode
245  * (all ADC instances belonging to the same ADC common instance).
246  * @note The setting of these parameters by function @ref LL_ADC_CommonInit()
247  * is conditioned to ADC instances state (all ADC instances
248  * sharing the same ADC common instance):
249  * All ADC instances sharing the same ADC common instance must be
250  * disabled.
251  */
252 typedef struct
253 {
254  uint32_t Multimode; /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).
255  This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
256 
257  This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */
258 } LL_ADC_CommonInitTypeDef;
259 /**
260  * @brief Structure definition of some features of ADC instance.
261  * @note These parameters have an impact on ADC scope: ADC instance.
262  * Affects both group regular and group injected (availability
263  * of ADC group injected depends on STM32 families).
264  * Refer to corresponding unitary functions into
265  * @ref ADC_LL_EF_Configuration_ADC_Instance .
266  * @note The setting of these parameters by function @ref LL_ADC_Init()
267  * is conditioned to ADC state:
268  * ADC instance must be disabled.
269  * This condition is applied to all ADC features, for efficiency
270  * and compatibility over all STM32 families. However, the different
271  * features can be set under different ADC state conditions
272  * (setting possible with ADC enabled without conversion on going,
273  * ADC enabled with conversion on going, ...)
274  * Each feature can be updated afterwards with a unitary function
275  * and potentially with ADC in a different state than disabled,
276  * refer to description of each function for setting
277  * conditioned to ADC state.
278  */
279 typedef struct
280 {
281  uint32_t DataAlignment; /*!< Set ADC conversion data alignment.
282  This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
283 
284  This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */
285 
286  uint32_t SequencersScanMode; /*!< Set ADC scan selection.
287  This parameter can be a value of @ref ADC_LL_EC_SCAN_SELECTION
288 
289  This feature can be modified afterwards using unitary function @ref LL_ADC_SetSequencersScanMode(). */
290 
291 } LL_ADC_InitTypeDef;
292 
293 /**
294  * @brief Structure definition of some features of ADC group regular.
295  * @note These parameters have an impact on ADC scope: ADC group regular.
296  * Refer to corresponding unitary functions into
297  * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
298  * (functions with prefix "REG").
299  * @note The setting of these parameters by function @ref LL_ADC_REG_Init()
300  * is conditioned to ADC state:
301  * ADC instance must be disabled.
302  * This condition is applied to all ADC features, for efficiency
303  * and compatibility over all STM32 families. However, the different
304  * features can be set under different ADC state conditions
305  * (setting possible with ADC enabled without conversion on going,
306  * ADC enabled with conversion on going, ...)
307  * Each feature can be updated afterwards with a unitary function
308  * and potentially with ADC in a different state than disabled,
309  * refer to description of each function for setting
310  * conditioned to ADC state.
311  */
312 typedef struct
313 {
314  uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
315  This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
316  @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
317  (only trigger polarity available on this STM32 serie).
318 
319  This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */
320 
321  uint32_t SequencerLength; /*!< Set ADC group regular sequencer length.
322  This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
323  @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
324 
325  This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */
326 
327  uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
328  This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
329  @note This parameter has an effect only if group regular sequencer is enabled
330  (scan length of 2 ranks or more).
331 
332  This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */
333 
334  uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).
335  This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
336  Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.
337 
338  This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */
339 
340  uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode.
341  This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
342 
343  This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */
344 
345 } LL_ADC_REG_InitTypeDef;
346 
347 /**
348  * @brief Structure definition of some features of ADC group injected.
349  * @note These parameters have an impact on ADC scope: ADC group injected.
350  * Refer to corresponding unitary functions into
351  * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
352  * (functions with prefix "INJ").
353  * @note The setting of these parameters by function @ref LL_ADC_INJ_Init()
354  * is conditioned to ADC state:
355  * ADC instance must be disabled.
356  * This condition is applied to all ADC features, for efficiency
357  * and compatibility over all STM32 families. However, the different
358  * features can be set under different ADC state conditions
359  * (setting possible with ADC enabled without conversion on going,
360  * ADC enabled with conversion on going, ...)
361  * Each feature can be updated afterwards with a unitary function
362  * and potentially with ADC in a different state than disabled,
363  * refer to description of each function for setting
364  * conditioned to ADC state.
365  */
366 typedef struct
367 {
368  uint32_t TriggerSource; /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external IP (timer event, external interrupt line).
369  This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
370  @note On this STM32 serie, external trigger is set with trigger polarity: rising edge
371  (only trigger polarity available on this STM32 serie).
372 
373  This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */
374 
375  uint32_t SequencerLength; /*!< Set ADC group injected sequencer length.
376  This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
377  @note This parameter is discarded if scan mode is disabled (refer to parameter 'ADC_SequencersScanMode').
378 
379  This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */
380 
381  uint32_t SequencerDiscont; /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.
382  This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
383  @note This parameter has an effect only if group injected sequencer is enabled
384  (scan length of 2 ranks or more).
385 
386  This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */
387 
388  uint32_t TrigAuto; /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.
389  This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
390  Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.
391 
392  This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */
393 
394 } LL_ADC_INJ_InitTypeDef;
395 
396 /**
397  * @}
398  */
399 #endif /* USE_FULL_LL_DRIVER */
400 
401 /* Exported constants --------------------------------------------------------*/
402 /** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
403  * @{
404  */
405 
406 /** @defgroup ADC_LL_EC_FLAG ADC flags
407  * @brief Flags defines which can be used with LL_ADC_ReadReg function
408  * @{
409  */
410 #define LL_ADC_FLAG_STRT ADC_SR_STRT /*!< ADC flag ADC group regular conversion start */
411 #define LL_ADC_FLAG_EOS ADC_SR_EOC /*!< ADC flag ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
412 #define LL_ADC_FLAG_JSTRT ADC_SR_JSTRT /*!< ADC flag ADC group injected conversion start */
413 #define LL_ADC_FLAG_JEOS ADC_SR_JEOC /*!< ADC flag ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
414 #define LL_ADC_FLAG_AWD1 ADC_SR_AWD /*!< ADC flag ADC analog watchdog 1 */
415 #if defined(ADC_MULTIMODE_SUPPORT)
416 #define LL_ADC_FLAG_EOS_MST ADC_SR_EOC /*!< ADC flag ADC multimode master group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
417 #define LL_ADC_FLAG_EOS_SLV ADC_SR_EOC /*!< ADC flag ADC multimode slave group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
418 #define LL_ADC_FLAG_JEOS_MST ADC_SR_JEOC /*!< ADC flag ADC multimode master group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
419 #define LL_ADC_FLAG_JEOS_SLV ADC_SR_JEOC /*!< ADC flag ADC multimode slave group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
420 #define LL_ADC_FLAG_AWD1_MST ADC_SR_AWD /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */
421 #define LL_ADC_FLAG_AWD1_SLV ADC_SR_AWD /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave (on STM32F1, this flag must be read from ADC instance slave: ADC2) */
422 #endif
423 /**
424  * @}
425  */
426 
427 /** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
428  * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions
429  * @{
430  */
431 #define LL_ADC_IT_EOS ADC_CR1_EOCIE /*!< ADC interruption ADC group regular end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group regular end of unitary conversion. Flag noted as "EOC" is corresponding to flag "EOS" in other STM32 families) */
432 #define LL_ADC_IT_JEOS ADC_CR1_JEOCIE /*!< ADC interruption ADC group injected end of sequence conversions (Note: on this STM32 serie, there is no flag ADC group injected end of unitary conversion. Flag noted as "JEOC" is corresponding to flag "JEOS" in other STM32 families) */
433 #define LL_ADC_IT_AWD1 ADC_CR1_AWDIE /*!< ADC interruption ADC analog watchdog 1 */
434 /**
435  * @}
436  */
437 
438 /** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose
439  * @{
440  */
441 /* List of ADC registers intended to be used (most commonly) with */
442 /* DMA transfer. */
443 /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */
444 #define LL_ADC_DMA_REG_REGULAR_DATA 0x00000000U /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */
445 #if defined(ADC_MULTIMODE_SUPPORT)
446 #define LL_ADC_DMA_REG_REGULAR_DATA_MULTI 0x00000001U /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */
447 #endif
448 /**
449  * @}
450  */
451 
452 /** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels
453  * @{
454  */
455 /* Note: Other measurement paths to internal channels may be available */
456 /* (connections to other peripherals). */
457 /* If they are not listed below, they do not require any specific */
458 /* path enable. In this case, Access to measurement path is done */
459 /* only by selecting the corresponding ADC internal channel. */
460 #define LL_ADC_PATH_INTERNAL_NONE 0x00000000U /*!< ADC measurement pathes all disabled */
461 #define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel VrefInt */
462 #define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CR2_TSVREFE) /*!< ADC measurement path to internal channel temperature sensor */
463 /**
464  * @}
465  */
466 
467 /** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution
468  * @{
469  */
470 #define LL_ADC_RESOLUTION_12B 0x00000000U /*!< ADC resolution 12 bits */
471 /**
472  * @}
473  */
474 
475 /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment
476  * @{
477  */
478 #define LL_ADC_DATA_ALIGN_RIGHT 0x00000000U /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/
479 #define LL_ADC_DATA_ALIGN_LEFT (ADC_CR2_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/
480 /**
481  * @}
482  */
483 
484 /** @defgroup ADC_LL_EC_SCAN_SELECTION ADC instance - Scan selection
485  * @{
486  */
487 #define LL_ADC_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC conversion is performed in unitary conversion mode (one channel converted, that defined in rank 1). Configuration of both groups regular and injected sequencers (sequence length, ...) is discarded: equivalent to length of 1 rank.*/
488 #define LL_ADC_SEQ_SCAN_ENABLE (ADC_CR1_SCAN) /*!< ADC conversions are performed in sequence conversions mode, according to configuration of both groups regular and injected sequencers (sequence length, ...). */
489 /**
490  * @}
491  */
492 
493 /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups
494  * @{
495  */
496 #define LL_ADC_GROUP_REGULAR 0x00000001U /*!< ADC group regular (available on all STM32 devices) */
497 #define LL_ADC_GROUP_INJECTED 0x00000002U /*!< ADC group injected (not available on all STM32 devices)*/
498 #define LL_ADC_GROUP_REGULAR_INJECTED 0x00000003U /*!< ADC both groups regular and injected */
499 /**
500  * @}
501  */
502 
503 /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number
504  * @{
505  */
506 #define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */
507 #define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */
508 #define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */
509 #define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */
510 #define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */
511 #define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */
512 #define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */
513 #define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */
514 #define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */
515 #define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */
516 #define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */
517 #define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */
518 #define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */
519 #define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */
520 #define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */
521 #define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */
522 #define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */
523 #define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */
524 #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F1, ADC channel available only on ADC instance: ADC1. */
525 #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */
526 /**
527  * @}
528  */
529 
530 /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source
531  * @{
532  */
533 /* ADC group regular external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
534 #define LL_ADC_REG_TRIG_SOFTWARE (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger internal: SW start. */
535 #define LL_ADC_REG_TRIG_EXT_TIM1_CH3 (ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
536 /* ADC group regular external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
537 #define LL_ADC_REG_TRIG_EXT_TIM1_CH1 0x00000000U /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
538 #define LL_ADC_REG_TRIG_EXT_TIM1_CH2 (ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
539 #define LL_ADC_REG_TRIG_EXT_TIM2_CH2 (ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
540 #define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CR2_EXTSEL_2) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */
541 #define LL_ADC_REG_TRIG_EXT_TIM4_CH4 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
542 #define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */
543 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
544 /* Note: TIM8_TRGO is available on ADC1 and ADC2 only in high-density and */
545 /* XL-density devices. */
546 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
547 /* A remap of trigger must be done at top level (refer to */
548 /* AFIO peripheral). */
549 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).*/
550 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
551 #if defined (STM32F103xE) || defined (STM32F103xG)
552 /* ADC group regular external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
553 #define LL_ADC_REG_TRIG_EXT_TIM3_CH1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
554 #define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
555 #define LL_ADC_REG_TRIG_EXT_TIM8_CH1 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM8 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
556 #define LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */
557 #define LL_ADC_REG_TRIG_EXT_TIM5_CH1 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
558 #define LL_ADC_REG_TRIG_EXT_TIM5_CH3 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: TIM5 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
559 #endif
560 /**
561  * @}
562  */
563 
564 /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge
565  * @{
566  */
567 #define LL_ADC_REG_TRIG_EXT_RISING ADC_CR2_EXTTRIG /*!< ADC group regular conversion trigger polarity set to rising edge */
568 /**
569  * @}
570  */
571 
572 /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode
573 * @{
574 */
575 #define LL_ADC_REG_CONV_SINGLE 0x00000000U /*!< ADC conversions are performed in single mode: one conversion per trigger */
576 #define LL_ADC_REG_CONV_CONTINUOUS (ADC_CR2_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */
577 /**
578  * @}
579  */
580 
581 /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data
582  * @{
583  */
584 #define LL_ADC_REG_DMA_TRANSFER_NONE 0x00000000U /*!< ADC conversions are not transferred by DMA */
585 #define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CR2_DMA) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */
586 /**
587  * @}
588  */
589 
590 /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length
591  * @{
592  */
593 #define LL_ADC_REG_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
594 #define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS ( ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */
595 #define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS ( ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */
596 #define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS ( ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */
597 #define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS ( ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */
598 #define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */
599 #define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */
600 #define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS ( ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */
601 #define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS (ADC_SQR1_L_3 ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */
602 #define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */
603 #define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */
604 #define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */
605 #define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */
606 #define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */
607 #define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */
608 #define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */
609 /**
610  * @}
611  */
612 
613 /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode
614  * @{
615  */
616 #define LL_ADC_REG_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group regular sequencer discontinuous mode disable */
617 #define LL_ADC_REG_SEQ_DISCONT_1RANK ( ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */
618 #define LL_ADC_REG_SEQ_DISCONT_2RANKS ( ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */
619 #define LL_ADC_REG_SEQ_DISCONT_3RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */
620 #define LL_ADC_REG_SEQ_DISCONT_4RANKS ( ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */
621 #define LL_ADC_REG_SEQ_DISCONT_5RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */
622 #define LL_ADC_REG_SEQ_DISCONT_6RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */
623 #define LL_ADC_REG_SEQ_DISCONT_7RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */
624 #define LL_ADC_REG_SEQ_DISCONT_8RANKS (ADC_CR1_DISCNUM_2 | ADC_CR1_DISCNUM_1 | ADC_CR1_DISCNUM_0 | ADC_CR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */
625 /**
626  * @}
627  */
628 
629 /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks
630  * @{
631  */
632 #define LL_ADC_REG_RANK_1 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */
633 #define LL_ADC_REG_RANK_2 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */
634 #define LL_ADC_REG_RANK_3 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */
635 #define LL_ADC_REG_RANK_4 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */
636 #define LL_ADC_REG_RANK_5 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */
637 #define LL_ADC_REG_RANK_6 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */
638 #define LL_ADC_REG_RANK_7 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */
639 #define LL_ADC_REG_RANK_8 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */
640 #define LL_ADC_REG_RANK_9 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 9 */
641 #define LL_ADC_REG_RANK_10 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */
642 #define LL_ADC_REG_RANK_11 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */
643 #define LL_ADC_REG_RANK_12 (ADC_SQR2_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */
644 #define LL_ADC_REG_RANK_13 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */
645 #define LL_ADC_REG_RANK_14 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */
646 #define LL_ADC_REG_RANK_15 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */
647 #define LL_ADC_REG_RANK_16 (ADC_SQR1_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */
648 /**
649  * @}
650  */
651 
652 /** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE ADC group injected - Trigger source
653  * @{
654  */
655 /* ADC group injected external triggers for ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device) */
656 #define LL_ADC_INJ_TRIG_SOFTWARE (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger internal: SW start. */
657 #define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO 0x00000000U /*!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */
658 #define LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
659 /* ADC group injected external triggers for ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device) */
660 #define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */
661 #define LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
662 #define LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (ADC_CR2_JEXTSEL_2) /*!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
663 #define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0) /*!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */
664 #define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1) /*!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). */
665 #if defined (STM32F101xE) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F105xC) || defined (STM32F107xC)
666 /* Note: TIM8_CH4 is available on ADC1 and ADC2 only in high-density and */
667 /* XL-density devices. */
668 /* Note: To use TIM8_TRGO on ADC1 or ADC2, a remap of trigger must be done */
669 /* A remap of trigger must be done at top level (refer to */
670 /* AFIO peripheral). */
671 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). Available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral). */
672 #endif /* STM32F101xE || STM32F103xE || STM32F103xG || STM32F105xC || STM32F107xC */
673 #if defined (STM32F103xE) || defined (STM32F103xG)
674 /* ADC group injected external triggers for ADC instances: ADC3 (for ADC instances ADCx available on the selected device) */
675 #define LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM4 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
676 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
677 #define LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /*!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
678 #define LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /*!< ADC group injected conversion trigger from external IP: TIM5 TRGO. Trigger edge set to rising edge (default setting). */
679 #define LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /*!< ADC group injected conversion trigger from external IP: TIM5 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */
680 #endif
681 /**
682  * @}
683  */
684 
685 /** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE ADC group injected - Trigger edge
686  * @{
687  */
688 #define LL_ADC_INJ_TRIG_EXT_RISING ADC_CR2_JEXTTRIG /*!< ADC group injected conversion trigger polarity set to rising edge */
689 /**
690  * @}
691  */
692 
693 /** @defgroup ADC_LL_EC_INJ_TRIG_AUTO ADC group injected - Automatic trigger mode
694 * @{
695 */
696 #define LL_ADC_INJ_TRIG_INDEPENDENT 0x00000000U /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */
697 #define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR (ADC_CR1_JAUTO) /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */
698 /**
699  * @}
700  */
701 
702 
703 /** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH ADC group injected - Sequencer scan length
704  * @{
705  */
706 #define LL_ADC_INJ_SEQ_SCAN_DISABLE 0x00000000U /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
707 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS ( ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */
708 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS (ADC_JSQR_JL_1 ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */
709 #define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */
710 /**
711  * @}
712  */
713 
714 /** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE ADC group injected - Sequencer discontinuous mode
715  * @{
716  */
717 #define LL_ADC_INJ_SEQ_DISCONT_DISABLE 0x00000000U /*!< ADC group injected sequencer discontinuous mode disable */
718 #define LL_ADC_INJ_SEQ_DISCONT_1RANK (ADC_CR1_JDISCEN) /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */
719 /**
720  * @}
721  */
722 
723 /** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
724  * @{
725  */
726 #define LL_ADC_INJ_RANK_1 (ADC_JDR1_REGOFFSET | ADC_JOFR1_REGOFFSET | 0x00000001U) /*!< ADC group injected sequencer rank 1 */
727 #define LL_ADC_INJ_RANK_2 (ADC_JDR2_REGOFFSET | ADC_JOFR2_REGOFFSET | 0x00000002U) /*!< ADC group injected sequencer rank 2 */
728 #define LL_ADC_INJ_RANK_3 (ADC_JDR3_REGOFFSET | ADC_JOFR3_REGOFFSET | 0x00000003U) /*!< ADC group injected sequencer rank 3 */
729 #define LL_ADC_INJ_RANK_4 (ADC_JDR4_REGOFFSET | ADC_JOFR4_REGOFFSET | 0x00000004U) /*!< ADC group injected sequencer rank 4 */
730 /**
731  * @}
732  */
733 
734 /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time
735  * @{
736  */
737 #define LL_ADC_SAMPLINGTIME_1CYCLE_5 0x00000000U /*!< Sampling time 1.5 ADC clock cycle */
738 #define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR2_SMP0_0) /*!< Sampling time 7.5 ADC clock cycles */
739 #define LL_ADC_SAMPLINGTIME_13CYCLES_5 (ADC_SMPR2_SMP0_1) /*!< Sampling time 13.5 ADC clock cycles */
740 #define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 28.5 ADC clock cycles */
741 #define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR2_SMP0_2) /*!< Sampling time 41.5 ADC clock cycles */
742 #define LL_ADC_SAMPLINGTIME_55CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_0) /*!< Sampling time 55.5 ADC clock cycles */
743 #define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1) /*!< Sampling time 71.5 ADC clock cycles */
744 #define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR2_SMP0_2 | ADC_SMPR2_SMP0_1 | ADC_SMPR2_SMP0_0) /*!< Sampling time 239.5 ADC clock cycles */
745 /**
746  * @}
747  */
748 
749 /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
750  * @{
751  */
752 #define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
753 /**
754  * @}
755  */
756 
757 /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels
758  * @{
759  */
760 #define LL_ADC_AWD_DISABLE 0x00000000U /*!< ADC analog watchdog monitoring disabled */
761 #define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */
762 #define LL_ADC_AWD_ALL_CHANNELS_INJ ( ADC_CR1_JAWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */
763 #define LL_ADC_AWD_ALL_CHANNELS_REG_INJ ( ADC_CR1_JAWDEN | ADC_CR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */
764 #define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */
765 #define LL_ADC_AWD_CHANNEL_0_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */
766 #define LL_ADC_AWD_CHANNEL_0_REG_INJ ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */
767 #define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */
768 #define LL_ADC_AWD_CHANNEL_1_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */
769 #define LL_ADC_AWD_CHANNEL_1_REG_INJ ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */
770 #define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */
771 #define LL_ADC_AWD_CHANNEL_2_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */
772 #define LL_ADC_AWD_CHANNEL_2_REG_INJ ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */
773 #define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */
774 #define LL_ADC_AWD_CHANNEL_3_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */
775 #define LL_ADC_AWD_CHANNEL_3_REG_INJ ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */
776 #define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */
777 #define LL_ADC_AWD_CHANNEL_4_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */
778 #define LL_ADC_AWD_CHANNEL_4_REG_INJ ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */
779 #define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */
780 #define LL_ADC_AWD_CHANNEL_5_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */
781 #define LL_ADC_AWD_CHANNEL_5_REG_INJ ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */
782 #define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */
783 #define LL_ADC_AWD_CHANNEL_6_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */
784 #define LL_ADC_AWD_CHANNEL_6_REG_INJ ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */
785 #define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */
786 #define LL_ADC_AWD_CHANNEL_7_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */
787 #define LL_ADC_AWD_CHANNEL_7_REG_INJ ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */
788 #define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */
789 #define LL_ADC_AWD_CHANNEL_8_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */
790 #define LL_ADC_AWD_CHANNEL_8_REG_INJ ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */
791 #define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */
792 #define LL_ADC_AWD_CHANNEL_9_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */
793 #define LL_ADC_AWD_CHANNEL_9_REG_INJ ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */
794 #define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */
795 #define LL_ADC_AWD_CHANNEL_10_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */
796 #define LL_ADC_AWD_CHANNEL_10_REG_INJ ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */
797 #define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */
798 #define LL_ADC_AWD_CHANNEL_11_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */
799 #define LL_ADC_AWD_CHANNEL_11_REG_INJ ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */
800 #define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */
801 #define LL_ADC_AWD_CHANNEL_12_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */
802 #define LL_ADC_AWD_CHANNEL_12_REG_INJ ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */
803 #define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */
804 #define LL_ADC_AWD_CHANNEL_13_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */
805 #define LL_ADC_AWD_CHANNEL_13_REG_INJ ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */
806 #define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */
807 #define LL_ADC_AWD_CHANNEL_14_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */
808 #define LL_ADC_AWD_CHANNEL_14_REG_INJ ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */
809 #define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */
810 #define LL_ADC_AWD_CHANNEL_15_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */
811 #define LL_ADC_AWD_CHANNEL_15_REG_INJ ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */
812 #define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */
813 #define LL_ADC_AWD_CHANNEL_16_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */
814 #define LL_ADC_AWD_CHANNEL_16_REG_INJ ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */
815 #define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */
816 #define LL_ADC_AWD_CHANNEL_17_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */
817 #define LL_ADC_AWD_CHANNEL_17_REG_INJ ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */
818 #define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */
819 #define LL_ADC_AWD_CH_VREFINT_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */
820 #define LL_ADC_AWD_CH_VREFINT_REG_INJ ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */
821 #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */
822 #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */
823 #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */
824 /**
825  * @}
826  */
827 
828 /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds
829  * @{
830  */
831 #define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD_TR1_HIGH_REGOFFSET) /*!< ADC analog watchdog threshold high */
832 #define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD_TR1_LOW_REGOFFSET) /*!< ADC analog watchdog threshold low */
833 /**
834  * @}
835  */
836 
837 #if !defined(ADC_MULTIMODE_SUPPORT)
838 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
839  * @{
840  */
841 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
842 /**
843  * @}
844  */
845 #endif
846 #if defined(ADC_MULTIMODE_SUPPORT)
847 /** @defgroup ADC_LL_EC_MULTI_MODE Multimode - Mode
848  * @{
849  */
850 #define LL_ADC_MULTI_INDEPENDENT 0x00000000U /*!< ADC dual mode disabled (ADC independent mode) */
851 #define LL_ADC_MULTI_DUAL_REG_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: group regular simultaneous */
852 #define LL_ADC_MULTI_DUAL_REG_INTERL_FAST ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES" on other STM32 devices)) */
853 #define LL_ADC_MULTI_DUAL_REG_INTERL_SLOW (ADC_CR1_DUALMOD_3 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
854 #define LL_ADC_MULTI_DUAL_INJ_SIMULT ( ADC_CR1_DUALMOD_2 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected simultaneous slow (delay between ADC sampling phases: 14 ADC clock cycles) (equivalent to multimode sampling delay set to "LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES" on other STM32 devices)) */
855 #define LL_ADC_MULTI_DUAL_INJ_ALTERN (ADC_CR1_DUALMOD_3 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */
856 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM ( ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */
857 #define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT ( ADC_CR1_DUALMOD_1 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */
858 #define LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM ( ADC_CR1_DUALMOD_1 | ADC_CR1_DUALMOD_0) /*!< ADC dual mode enabled: Combined group regular interleaved fast (delay between ADC sampling phases: 7 ADC clock cycles) + group injected simultaneous */
859 #define LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM ( ADC_CR1_DUALMOD_2 ) /*!< ADC dual mode enabled: Combined group regular interleaved slow (delay between ADC sampling phases: 14 ADC clock cycles) + group injected simultaneous */
860 
861 /**
862  * @}
863  */
864 
865 /** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE Multimode - ADC master or slave
866  * @{
867  */
868 #define LL_ADC_MULTI_MASTER ( ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: ADC master */
869 #define LL_ADC_MULTI_SLAVE (ADC_DR_ADC2DATA ) /*!< In multimode, selection among several ADC instances: ADC slave */
870 #define LL_ADC_MULTI_MASTER_SLAVE (ADC_DR_ADC2DATA | ADC_DR_DATA) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */
871 /**
872  * @}
873  */
874 
875 #endif /* ADC_MULTIMODE_SUPPORT */
876 
877 
878 /** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays
879  * @note Only ADC IP HW delays are defined in ADC LL driver driver,
880  * not timeout values.
881  * For details on delays values, refer to descriptions in source code
882  * above each literal definition.
883  * @{
884  */
885 
886 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
887 /* not timeout values. */
888 /* Timeout values for ADC operations are dependent to device clock */
889 /* configuration (system clock versus ADC clock), */
890 /* and therefore must be defined in user application. */
891 /* Indications for estimation of ADC timeout delays, for this */
892 /* STM32 serie: */
893 /* - ADC enable time: maximum delay is 1us */
894 /* (refer to device datasheet, parameter "tSTAB") */
895 /* - ADC conversion time: duration depending on ADC clock and ADC */
896 /* configuration. */
897 /* (refer to device reference manual, section "Timing") */
898 
899 /* Delay for temperature sensor stabilization time. */
900 /* Literal set to maximum value (refer to device datasheet, */
901 /* parameter "tSTART"). */
902 /* Unit: us */
903 #define LL_ADC_DELAY_TEMPSENSOR_STAB_US (10U) /*!< Delay for internal voltage reference stabilization time */
904 
905 /* Delay required between ADC disable and ADC calibration start. */
906 /* Note: On this STM32 serie, before starting a calibration, */
907 /* ADC must be disabled. */
908 /* A minimum number of ADC clock cycles are required */
909 /* between ADC disable state and calibration start. */
910 /* Refer to literal @ref LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES. */
911 /* Wait time can be computed in user application by waiting for the */
912 /* equivalent number of CPU cycles, by taking into account */
913 /* ratio of CPU clock versus ADC clock prescalers. */
914 /* Unit: ADC clock cycles. */
915 #define LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between ADC disable and ADC calibration start */
916 
917 /* Delay required between end of ADC Enable and the start of ADC calibration. */
918 /* Note: On this STM32 serie, a minimum number of ADC clock cycles */
919 /* are required between the end of ADC enable and the start of ADC */
920 /* calibration. */
921 /* Wait time can be computed in user application by waiting for the */
922 /* equivalent number of CPU cycles, by taking into account */
923 /* ratio of CPU clock versus ADC clock prescalers. */
924 /* Unit: ADC clock cycles. */
925 #define LL_ADC_DELAY_ENABLE_CALIB_ADC_CYCLES (2U) /*!< Delay required between end of ADC enable and the start of ADC calibration */
926 
927 /**
928  * @}
929  */
930 
931 /**
932  * @}
933  */
934 
935 
936 /* Exported macro ------------------------------------------------------------*/
937 /** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
938  * @{
939  */
940 
941 /** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
942  * @{
943  */
944 
945 /**
946  * @brief Write a value in ADC register
947  * @param __INSTANCE__ ADC Instance
948  * @param __REG__ Register to be written
949  * @param __VALUE__ Value to be written in the register
950  * @retval None
951  */
952 #define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
953 
954 /**
955  * @brief Read a value in ADC register
956  * @param __INSTANCE__ ADC Instance
957  * @param __REG__ Register to be read
958  * @retval Register value
959  */
960 #define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
961 /**
962  * @}
963  */
964 
965 /** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
966  * @{
967  */
968 
969 /**
970  * @brief Helper macro to get ADC channel number in decimal format
971  * from literals LL_ADC_CHANNEL_x.
972  * @note Example:
973  * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
974  * will return decimal number "4".
975  * @note The input can be a value from functions where a channel
976  * number is returned, either defined with number
977  * or with bitfield (only one bit must be set).
978  * @param __CHANNEL__ This parameter can be one of the following values:
979  * @arg @ref LL_ADC_CHANNEL_0
980  * @arg @ref LL_ADC_CHANNEL_1
981  * @arg @ref LL_ADC_CHANNEL_2
982  * @arg @ref LL_ADC_CHANNEL_3
983  * @arg @ref LL_ADC_CHANNEL_4
984  * @arg @ref LL_ADC_CHANNEL_5
985  * @arg @ref LL_ADC_CHANNEL_6
986  * @arg @ref LL_ADC_CHANNEL_7
987  * @arg @ref LL_ADC_CHANNEL_8
988  * @arg @ref LL_ADC_CHANNEL_9
989  * @arg @ref LL_ADC_CHANNEL_10
990  * @arg @ref LL_ADC_CHANNEL_11
991  * @arg @ref LL_ADC_CHANNEL_12
992  * @arg @ref LL_ADC_CHANNEL_13
993  * @arg @ref LL_ADC_CHANNEL_14
994  * @arg @ref LL_ADC_CHANNEL_15
995  * @arg @ref LL_ADC_CHANNEL_16
996  * @arg @ref LL_ADC_CHANNEL_17
997  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
998  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
999  *
1000  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
1001  * @retval Value between Min_Data=0 and Max_Data=18
1002  */
1003 #define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
1004  (((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
1005 
1006 /**
1007  * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
1008  * from number in decimal format.
1009  * @note Example:
1010  * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
1011  * will return a data equivalent to "LL_ADC_CHANNEL_4".
1012  * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18
1013  * @retval Returned value can be one of the following values:
1014  * @arg @ref LL_ADC_CHANNEL_0
1015  * @arg @ref LL_ADC_CHANNEL_1
1016  * @arg @ref LL_ADC_CHANNEL_2
1017  * @arg @ref LL_ADC_CHANNEL_3
1018  * @arg @ref LL_ADC_CHANNEL_4
1019  * @arg @ref LL_ADC_CHANNEL_5
1020  * @arg @ref LL_ADC_CHANNEL_6
1021  * @arg @ref LL_ADC_CHANNEL_7
1022  * @arg @ref LL_ADC_CHANNEL_8
1023  * @arg @ref LL_ADC_CHANNEL_9
1024  * @arg @ref LL_ADC_CHANNEL_10
1025  * @arg @ref LL_ADC_CHANNEL_11
1026  * @arg @ref LL_ADC_CHANNEL_12
1027  * @arg @ref LL_ADC_CHANNEL_13
1028  * @arg @ref LL_ADC_CHANNEL_14
1029  * @arg @ref LL_ADC_CHANNEL_15
1030  * @arg @ref LL_ADC_CHANNEL_16
1031  * @arg @ref LL_ADC_CHANNEL_17
1032  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1033  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1034  *
1035  * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
1036  * (1) For ADC channel read back from ADC register,
1037  * comparison with internal channel parameter to be done
1038  * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1039  */
1040 #define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
1041  (((__DECIMAL_NB__) <= 9U) \
1042  ? ( \
1043  ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1044  (ADC_SMPR2_REGOFFSET | (((uint32_t) (3U * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1045  ) \
1046  : \
1047  ( \
1048  ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \
1049  (ADC_SMPR1_REGOFFSET | (((uint32_t) (3U * ((__DECIMAL_NB__) - 10U))) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) \
1050  ) \
1051  )
1052 
1053 /**
1054  * @brief Helper macro to determine whether the selected channel
1055  * corresponds to literal definitions of driver.
1056  * @note The different literal definitions of ADC channels are:
1057  * - ADC internal channel:
1058  * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
1059  * - ADC external channel (channel connected to a GPIO pin):
1060  * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
1061  * @note The channel parameter must be a value defined from literal
1062  * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1063  * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1064  * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
1065  * must not be a value from functions where a channel number is
1066  * returned from ADC registers,
1067  * because internal and external channels share the same channel
1068  * number in ADC registers. The differentiation is made only with
1069  * parameters definitions of driver.
1070  * @param __CHANNEL__ This parameter can be one of the following values:
1071  * @arg @ref LL_ADC_CHANNEL_0
1072  * @arg @ref LL_ADC_CHANNEL_1
1073  * @arg @ref LL_ADC_CHANNEL_2
1074  * @arg @ref LL_ADC_CHANNEL_3
1075  * @arg @ref LL_ADC_CHANNEL_4
1076  * @arg @ref LL_ADC_CHANNEL_5
1077  * @arg @ref LL_ADC_CHANNEL_6
1078  * @arg @ref LL_ADC_CHANNEL_7
1079  * @arg @ref LL_ADC_CHANNEL_8
1080  * @arg @ref LL_ADC_CHANNEL_9
1081  * @arg @ref LL_ADC_CHANNEL_10
1082  * @arg @ref LL_ADC_CHANNEL_11
1083  * @arg @ref LL_ADC_CHANNEL_12
1084  * @arg @ref LL_ADC_CHANNEL_13
1085  * @arg @ref LL_ADC_CHANNEL_14
1086  * @arg @ref LL_ADC_CHANNEL_15
1087  * @arg @ref LL_ADC_CHANNEL_16
1088  * @arg @ref LL_ADC_CHANNEL_17
1089  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1090  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1091  *
1092  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
1093  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).
1094  * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
1095  */
1096 #define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
1097  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U)
1098 
1099 /**
1100  * @brief Helper macro to convert a channel defined from parameter
1101  * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1102  * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1103  * to its equivalent parameter definition of a ADC external channel
1104  * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
1105  * @note The channel parameter can be, additionally to a value
1106  * defined from parameter definition of a ADC internal channel
1107  * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
1108  * a value defined from parameter definition of
1109  * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1110  * or a value from functions where a channel number is returned
1111  * from ADC registers.
1112  * @param __CHANNEL__ This parameter can be one of the following values:
1113  * @arg @ref LL_ADC_CHANNEL_0
1114  * @arg @ref LL_ADC_CHANNEL_1
1115  * @arg @ref LL_ADC_CHANNEL_2
1116  * @arg @ref LL_ADC_CHANNEL_3
1117  * @arg @ref LL_ADC_CHANNEL_4
1118  * @arg @ref LL_ADC_CHANNEL_5
1119  * @arg @ref LL_ADC_CHANNEL_6
1120  * @arg @ref LL_ADC_CHANNEL_7
1121  * @arg @ref LL_ADC_CHANNEL_8
1122  * @arg @ref LL_ADC_CHANNEL_9
1123  * @arg @ref LL_ADC_CHANNEL_10
1124  * @arg @ref LL_ADC_CHANNEL_11
1125  * @arg @ref LL_ADC_CHANNEL_12
1126  * @arg @ref LL_ADC_CHANNEL_13
1127  * @arg @ref LL_ADC_CHANNEL_14
1128  * @arg @ref LL_ADC_CHANNEL_15
1129  * @arg @ref LL_ADC_CHANNEL_16
1130  * @arg @ref LL_ADC_CHANNEL_17
1131  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1132  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1133  *
1134  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
1135  * @retval Returned value can be one of the following values:
1136  * @arg @ref LL_ADC_CHANNEL_0
1137  * @arg @ref LL_ADC_CHANNEL_1
1138  * @arg @ref LL_ADC_CHANNEL_2
1139  * @arg @ref LL_ADC_CHANNEL_3
1140  * @arg @ref LL_ADC_CHANNEL_4
1141  * @arg @ref LL_ADC_CHANNEL_5
1142  * @arg @ref LL_ADC_CHANNEL_6
1143  * @arg @ref LL_ADC_CHANNEL_7
1144  * @arg @ref LL_ADC_CHANNEL_8
1145  * @arg @ref LL_ADC_CHANNEL_9
1146  * @arg @ref LL_ADC_CHANNEL_10
1147  * @arg @ref LL_ADC_CHANNEL_11
1148  * @arg @ref LL_ADC_CHANNEL_12
1149  * @arg @ref LL_ADC_CHANNEL_13
1150  * @arg @ref LL_ADC_CHANNEL_14
1151  * @arg @ref LL_ADC_CHANNEL_15
1152  * @arg @ref LL_ADC_CHANNEL_16
1153  * @arg @ref LL_ADC_CHANNEL_17
1154  */
1155 #define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
1156  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
1157 
1158 /**
1159  * @brief Helper macro to determine whether the internal channel
1160  * selected is available on the ADC instance selected.
1161  * @note The channel parameter must be a value defined from parameter
1162  * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
1163  * LL_ADC_CHANNEL_TEMPSENSOR, ...),
1164  * must not be a value defined from parameter definition of
1165  * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
1166  * or a value from functions where a channel number is
1167  * returned from ADC registers,
1168  * because internal and external channels share the same channel
1169  * number in ADC registers. The differentiation is made only with
1170  * parameters definitions of driver.
1171  * @param __ADC_INSTANCE__ ADC instance
1172  * @param __CHANNEL__ This parameter can be one of the following values:
1173  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1174  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1175  *
1176  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
1177  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
1178  * Value "1" if the internal channel selected is available on the ADC instance selected.
1179  */
1180 #define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
1181  (((__ADC_INSTANCE__) == ADC1) \
1182  ? ( \
1183  ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \
1184  ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \
1185  ) \
1186  : \
1187  (0U) \
1188  )
1189 
1190 /**
1191  * @brief Helper macro to define ADC analog watchdog parameter:
1192  * define a single channel to monitor with analog watchdog
1193  * from sequencer channel and groups definition.
1194  * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
1195  * Example:
1196  * LL_ADC_SetAnalogWDMonitChannels(
1197  * ADC1, LL_ADC_AWD1,
1198  * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
1199  * @param __CHANNEL__ This parameter can be one of the following values:
1200  * @arg @ref LL_ADC_CHANNEL_0
1201  * @arg @ref LL_ADC_CHANNEL_1
1202  * @arg @ref LL_ADC_CHANNEL_2
1203  * @arg @ref LL_ADC_CHANNEL_3
1204  * @arg @ref LL_ADC_CHANNEL_4
1205  * @arg @ref LL_ADC_CHANNEL_5
1206  * @arg @ref LL_ADC_CHANNEL_6
1207  * @arg @ref LL_ADC_CHANNEL_7
1208  * @arg @ref LL_ADC_CHANNEL_8
1209  * @arg @ref LL_ADC_CHANNEL_9
1210  * @arg @ref LL_ADC_CHANNEL_10
1211  * @arg @ref LL_ADC_CHANNEL_11
1212  * @arg @ref LL_ADC_CHANNEL_12
1213  * @arg @ref LL_ADC_CHANNEL_13
1214  * @arg @ref LL_ADC_CHANNEL_14
1215  * @arg @ref LL_ADC_CHANNEL_15
1216  * @arg @ref LL_ADC_CHANNEL_16
1217  * @arg @ref LL_ADC_CHANNEL_17
1218  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
1219  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
1220  *
1221  * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
1222  * (1) For ADC channel read back from ADC register,
1223  * comparison with internal channel parameter to be done
1224  * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
1225  * @param __GROUP__ This parameter can be one of the following values:
1226  * @arg @ref LL_ADC_GROUP_REGULAR
1227  * @arg @ref LL_ADC_GROUP_INJECTED
1228  * @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
1229  * @retval Returned value can be one of the following values:
1230  * @arg @ref LL_ADC_AWD_DISABLE
1231  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
1232  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
1233  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
1234  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
1235  * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
1236  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
1237  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
1238  * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
1239  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
1240  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
1241  * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
1242  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
1243  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
1244  * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
1245  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
1246  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
1247  * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
1248  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
1249  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
1250  * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
1251  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
1252  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
1253  * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
1254  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
1255  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
1256  * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
1257  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
1258  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
1259  * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
1260  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
1261  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
1262  * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
1263  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
1264  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
1265  * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
1266  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
1267  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
1268  * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
1269  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
1270  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
1271  * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
1272  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
1273  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
1274  * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
1275  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
1276  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
1277  * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
1278  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
1279  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
1280  * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
1281  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
1282  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
1283  * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
1284  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
1285  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
1286  * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
1287  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
1288  * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
1289  * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
1290  * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
1291  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
1292  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
1293  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
1294  *
1295  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
1296  */
1297 #define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \
1298  (((__GROUP__) == LL_ADC_GROUP_REGULAR) \
1299  ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1300  : \
1301  ((__GROUP__) == LL_ADC_GROUP_INJECTED) \
1302  ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) \
1303  : \
1304  (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) \
1305  )
1306 
1307 /**
1308  * @brief Helper macro to set the value of ADC analog watchdog threshold high
1309  * or low in function of ADC resolution, when ADC resolution is
1310  * different of 12 bits.
1311  * @note To be used with function @ref LL_ADC_SetAnalogWDThresholds().
1312  * Example, with a ADC resolution of 8 bits, to set the value of
1313  * analog watchdog threshold high (on 8 bits):
1314  * LL_ADC_SetAnalogWDThresholds
1315  * (< ADCx param >,
1316  * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
1317  * );
1318  * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1319  * @arg @ref LL_ADC_RESOLUTION_12B
1320  * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
1321  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1322  */
1323 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
1324 /* This macro has been kept anyway for compatibility with other */
1325 /* STM32 families featuring different ADC resolutions. */
1326 #define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
1327  ((__AWD_THRESHOLD__) << (0U))
1328 
1329 /**
1330  * @brief Helper macro to get the value of ADC analog watchdog threshold high
1331  * or low in function of ADC resolution, when ADC resolution is
1332  * different of 12 bits.
1333  * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds().
1334  * Example, with a ADC resolution of 8 bits, to get the value of
1335  * analog watchdog threshold high (on 8 bits):
1336  * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
1337  * (LL_ADC_RESOLUTION_8B,
1338  * LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
1339  * );
1340  * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1341  * @arg @ref LL_ADC_RESOLUTION_12B
1342  * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
1343  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1344  */
1345 /* Note: On this STM32 serie, ADC is fixed to resolution 12 bits. */
1346 /* This macro has been kept anyway for compatibility with other */
1347 /* STM32 families featuring different ADC resolutions. */
1348 #define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
1349  (__AWD_THRESHOLD_12_BITS__)
1350 
1351 #if defined(ADC_MULTIMODE_SUPPORT)
1352 /**
1353  * @brief Helper macro to get the ADC multimode conversion data of ADC master
1354  * or ADC slave from raw value with both ADC conversion data concatenated.
1355  * @note This macro is intended to be used when multimode transfer by DMA
1356  * is enabled.
1357  * In this case the transferred data need to processed with this macro
1358  * to separate the conversion data of ADC master and ADC slave.
1359  * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
1360  * @arg @ref LL_ADC_MULTI_MASTER
1361  * @arg @ref LL_ADC_MULTI_SLAVE
1362  * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
1363  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
1364  */
1365 #define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
1366  (((__ADC_MULTI_CONV_DATA__) >> POSITION_VAL((__ADC_MULTI_MASTER_SLAVE__))) & ADC_DR_DATA)
1367 #endif
1368 
1369 /**
1370  * @brief Helper macro to select the ADC common instance
1371  * to which is belonging the selected ADC instance.
1372  * @note ADC common register instance can be used for:
1373  * - Set parameters common to several ADC instances
1374  * - Multimode (for devices with several ADC instances)
1375  * Refer to functions having argument "ADCxy_COMMON" as parameter.
1376  * @note On STM32F1, there is no common ADC instance.
1377  * However, ADC instance ADC1 has a role of common ADC instance
1378  * for ADC1 and ADC2:
1379  * this instance is used to manage internal channels
1380  * and multimode (these features are managed in ADC common
1381  * instances on some other STM32 devices).
1382  * ADC instance ADC3 (if available on the selected device)
1383  * has no ADC common instance.
1384  * @param __ADCx__ ADC instance
1385  * @retval ADC common register instance
1386  */
1387 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1388 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1389  ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2)) \
1390  ? ( \
1391  (ADC12_COMMON) \
1392  ) \
1393  : \
1394  ( \
1395  (0U) \
1396  ) \
1397  )
1398 #elif defined(ADC1) && defined(ADC2)
1399 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1400  (ADC12_COMMON)
1401 #else
1402 #define __LL_ADC_COMMON_INSTANCE(__ADCx__) \
1403  (ADC1_COMMON)
1404 #endif
1405 
1406 /**
1407  * @brief Helper macro to check if all ADC instances sharing the same
1408  * ADC common instance are disabled.
1409  * @note This check is required by functions with setting conditioned to
1410  * ADC state:
1411  * All ADC instances of the ADC common group must be disabled.
1412  * Refer to functions having argument "ADCxy_COMMON" as parameter.
1413  * @note On devices with only 1 ADC common instance, parameter of this macro
1414  * is useless and can be ignored (parameter kept for compatibility
1415  * with devices featuring several ADC common instances).
1416  * @note On STM32F1, there is no common ADC instance.
1417  * However, ADC instance ADC1 has a role of common ADC instance
1418  * for ADC1 and ADC2:
1419  * this instance is used to manage internal channels
1420  * and multimode (these features are managed in ADC common
1421  * instances on some other STM32 devices).
1422  * ADC instance ADC3 (if available on the selected device)
1423  * has no ADC common instance.
1424  * @param __ADCXY_COMMON__ ADC common instance
1425  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1426  * @retval Value "0" if all ADC instances sharing the same ADC common instance
1427  * are disabled.
1428  * Value "1" if at least one ADC instance sharing the same ADC common instance
1429  * is enabled.
1430  */
1431 #if defined(ADC1) && defined(ADC2) && defined(ADC3)
1432 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1433  (((__ADCXY_COMMON__) == ADC12_COMMON) \
1434  ? ( \
1435  (LL_ADC_IsEnabled(ADC1) | \
1436  LL_ADC_IsEnabled(ADC2) ) \
1437  ) \
1438  : \
1439  ( \
1440  LL_ADC_IsEnabled(ADC3) \
1441  ) \
1442  )
1443 #elif defined(ADC1) && defined(ADC2)
1444 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1445  (LL_ADC_IsEnabled(ADC1) | \
1446  LL_ADC_IsEnabled(ADC2) )
1447 #else
1448 #define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
1449  LL_ADC_IsEnabled(ADC1)
1450 #endif
1451 
1452 /**
1453  * @brief Helper macro to define the ADC conversion data full-scale digital
1454  * value corresponding to the selected ADC resolution.
1455  * @note ADC conversion data full-scale corresponds to voltage range
1456  * determined by analog voltage references Vref+ and Vref-
1457  * (refer to reference manual).
1458  * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1459  * @arg @ref LL_ADC_RESOLUTION_12B
1460  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1461  */
1462 #define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1463  (0xFFFU)
1464 
1465 
1466 /**
1467  * @brief Helper macro to calculate the voltage (unit: mVolt)
1468  * corresponding to a ADC conversion data (unit: digital value).
1469  * @note Analog reference voltage (Vref+) must be known from
1470  * user board environment or can be calculated using ADC measurement.
1471  * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
1472  * @param __ADC_DATA__ ADC conversion data (resolution 12 bits)
1473  * (unit: digital value).
1474  * @param __ADC_RESOLUTION__ This parameter can be one of the following values:
1475  * @arg @ref LL_ADC_RESOLUTION_12B
1476  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
1477  */
1478 #define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
1479  __ADC_DATA__,\
1480  __ADC_RESOLUTION__) \
1481  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \
1482  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
1483  )
1484 
1485 
1486 /**
1487  * @brief Helper macro to calculate the temperature (unit: degree Celsius)
1488  * from ADC conversion data of internal temperature sensor.
1489  * @note Computation is using temperature sensor typical values
1490  * (refer to device datasheet).
1491  * @note Calculation formula:
1492  * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
1493  * / Avg_Slope + CALx_TEMP
1494  * with TS_ADC_DATA = temperature sensor raw data measured by ADC
1495  * (unit: digital value)
1496  * Avg_Slope = temperature sensor slope
1497  * (unit: uV/Degree Celsius)
1498  * TS_TYP_CALx_VOLT = temperature sensor digital value at
1499  * temperature CALx_TEMP (unit: mV)
1500  * Caution: Calculation relevancy under reserve the temperature sensor
1501  * of the current device has characteristics in line with
1502  * datasheet typical values.
1503  * If temperature sensor calibration values are available on
1504  * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
1505  * temperature calculation will be more accurate using
1506  * helper macro @ref __LL_ADC_CALC_TEMPERATURE().
1507  * @note As calculation input, the analog reference voltage (Vref+) must be
1508  * defined as it impacts the ADC LSB equivalent voltage.
1509  * @note Analog reference voltage (Vref+) must be known from
1510  * user board environment or can be calculated using ADC measurement.
1511  * @note ADC measurement data must correspond to a resolution of 12bits
1512  * (full scale digital value 4095). If not the case, the data must be
1513  * preliminarily rescaled to an equivalent resolution of 12 bits.
1514  * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).
1515  * On STM32F1, refer to device datasheet parameter "Avg_Slope".
1516  * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).
1517  * On STM32F1, refer to device datasheet parameter "V25".
1518  * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)
1519  * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV)
1520  * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value).
1521  * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured.
1522  * This parameter can be one of the following values:
1523  * @arg @ref LL_ADC_RESOLUTION_12B
1524  * @retval Temperature (unit: degree Celsius)
1525  */
1526 #define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
1527  __TEMPSENSOR_TYP_CALX_V__,\
1528  __TEMPSENSOR_CALX_TEMP__,\
1529  __VREFANALOG_VOLTAGE__,\
1530  __TEMPSENSOR_ADC_DATA__,\
1531  __ADC_RESOLUTION__) \
1532  ((( ( \
1533  (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \
1534  * 1000) \
1535  - \
1536  (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \
1537  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \
1538  * 1000) \
1539  ) \
1540  ) / (__TEMPSENSOR_TYP_AVGSLOPE__) \
1541  ) + (__TEMPSENSOR_CALX_TEMP__) \
1542  )
1543 
1544 /**
1545  * @}
1546  */
1547 
1548 /**
1549  * @}
1550  */
1551 
1552 
1553 /* Exported functions --------------------------------------------------------*/
1554 /** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
1555  * @{
1556  */
1557 
1558 /** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
1559  * @{
1560  */
1561 /* Note: LL ADC functions to set DMA transfer are located into sections of */
1562 /* configuration of ADC instance, groups and multimode (if available): */
1563 /* @ref LL_ADC_REG_SetDMATransfer(), ... */
1564 
1565 /**
1566  * @brief Function to help to configure DMA transfer from ADC: retrieve the
1567  * ADC register address from ADC instance and a list of ADC registers
1568  * intended to be used (most commonly) with DMA transfer.
1569  * @note These ADC registers are data registers:
1570  * when ADC conversion data is available in ADC data registers,
1571  * ADC generates a DMA transfer request.
1572  * @note This macro is intended to be used with LL DMA driver, refer to
1573  * function "LL_DMA_ConfigAddresses()".
1574  * Example:
1575  * LL_DMA_ConfigAddresses(DMA1,
1576  * LL_DMA_CHANNEL_1,
1577  * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
1578  * (uint32_t)&< array or variable >,
1579  * LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
1580  * @note For devices with several ADC: in multimode, some devices
1581  * use a different data register outside of ADC instance scope
1582  * (common data register). This macro manages this register difference,
1583  * only ADC instance has to be set as parameter.
1584  * @note On STM32F1, only ADC instances ADC1 and ADC3 have DMA transfer
1585  * capability, not ADC2 (ADC2 and ADC3 instances not available on
1586  * all devices).
1587  * @note On STM32F1, multimode can be used only with ADC1 and ADC2, not ADC3.
1588  * Therefore, the corresponding parameter of data transfer
1589  * for multimode can be used only with ADC1 and ADC2.
1590  * (ADC2 and ADC3 instances not available on all devices).
1591  * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr
1592  * @param ADCx ADC instance
1593  * @param Register This parameter can be one of the following values:
1594  * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
1595  * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
1596  *
1597  * (1) Available on devices with several ADC instances.
1598  * @retval ADC register address
1599  */
1600 #if defined(ADC_MULTIMODE_SUPPORT)
1601 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1602 {
1603  register uint32_t data_reg_addr = 0U;
1604 
1605  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
1606  {
1607  /* Retrieve address of register DR */
1608  data_reg_addr = (uint32_t)&(ADCx->DR);
1609  }
1610  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
1611  {
1612  /* Retrieve address of register of multimode data */
1613  data_reg_addr = (uint32_t)&(ADC12_COMMON->DR);
1614  }
1615 
1616  return data_reg_addr;
1617 }
1618 #else
1619 __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)
1620 {
1621  /* Retrieve address of register DR */
1622  return (uint32_t)&(ADCx->DR);
1623 }
1624 #endif
1625 
1626 /**
1627  * @}
1628  */
1629 
1630 /** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances
1631  * @{
1632  */
1633 
1634 /**
1635  * @brief Set parameter common to several ADC: measurement path to internal
1636  * channels (VrefInt, temperature sensor, ...).
1637  * @note One or several values can be selected.
1638  * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1639  * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1640  * @note Stabilization time of measurement path to internal channel:
1641  * After enabling internal paths, before starting ADC conversion,
1642  * a delay is required for internal voltage reference and
1643  * temperature sensor stabilization time.
1644  * Refer to device datasheet.
1645  * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.
1646  * @note ADC internal channel sampling time constraint:
1647  * For ADC conversion of internal channels,
1648  * a sampling time minimum value is required.
1649  * Refer to device datasheet.
1650  * @rmtoll CR2 TSVREFE LL_ADC_SetCommonPathInternalCh
1651  * @param ADCxy_COMMON ADC common instance
1652  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1653  * @param PathInternal This parameter can be a combination of the following values:
1654  * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1655  * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1656  * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1657  * @retval None
1658  */
1659 __STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
1660 {
1661  MODIFY_REG(ADCxy_COMMON->CR2, (ADC_CR2_TSVREFE), PathInternal);
1662 }
1663 
1664 /**
1665  * @brief Get parameter common to several ADC: measurement path to internal
1666  * channels (VrefInt, temperature sensor, ...).
1667  * @note One or several values can be selected.
1668  * Example: (LL_ADC_PATH_INTERNAL_VREFINT |
1669  * LL_ADC_PATH_INTERNAL_TEMPSENSOR)
1670  * @rmtoll CR2 TSVREFE LL_ADC_GetCommonPathInternalCh
1671  * @param ADCxy_COMMON ADC common instance
1672  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1673  * @retval Returned value can be a combination of the following values:
1674  * @arg @ref LL_ADC_PATH_INTERNAL_NONE
1675  * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
1676  * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
1677  */
1678 __STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)
1679 {
1680  return (uint32_t)(READ_BIT(ADCxy_COMMON->CR2, ADC_CR2_TSVREFE));
1681 }
1682 
1683 /**
1684  * @}
1685  */
1686 
1687 /** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
1688  * @{
1689  */
1690 
1691 /**
1692  * @brief Set ADC conversion data alignment.
1693  * @note Refer to reference manual for alignments formats
1694  * dependencies to ADC resolutions.
1695  * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1696  * @param ADCx ADC instance
1697  * @param DataAlignment This parameter can be one of the following values:
1698  * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1699  * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1700  * @retval None
1701  */
1702 __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
1703 {
1704  MODIFY_REG(ADCx->CR2, ADC_CR2_ALIGN, DataAlignment);
1705 }
1706 
1707 /**
1708  * @brief Get ADC conversion data alignment.
1709  * @note Refer to reference manual for alignments formats
1710  * dependencies to ADC resolutions.
1711  * @rmtoll CR2 ALIGN LL_ADC_SetDataAlignment
1712  * @param ADCx ADC instance
1713  * @retval Returned value can be one of the following values:
1714  * @arg @ref LL_ADC_DATA_ALIGN_RIGHT
1715  * @arg @ref LL_ADC_DATA_ALIGN_LEFT
1716  */
1717 __STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx)
1718 {
1719  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_ALIGN));
1720 }
1721 
1722 /**
1723  * @brief Set ADC sequencers scan mode, for all ADC groups
1724  * (group regular, group injected).
1725  * @note According to sequencers scan mode :
1726  * - If disabled: ADC conversion is performed in unitary conversion
1727  * mode (one channel converted, that defined in rank 1).
1728  * Configuration of sequencers of all ADC groups
1729  * (sequencer scan length, ...) is discarded: equivalent to
1730  * scan length of 1 rank.
1731  * - If enabled: ADC conversions are performed in sequence conversions
1732  * mode, according to configuration of sequencers of
1733  * each ADC group (sequencer scan length, ...).
1734  * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1735  * and to function @ref LL_ADC_INJ_SetSequencerLength().
1736  * @rmtoll CR1 SCAN LL_ADC_SetSequencersScanMode
1737  * @param ADCx ADC instance
1738  * @param ScanMode This parameter can be one of the following values:
1739  * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1740  * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1741  * @retval None
1742  */
1743 __STATIC_INLINE void LL_ADC_SetSequencersScanMode(ADC_TypeDef *ADCx, uint32_t ScanMode)
1744 {
1745  MODIFY_REG(ADCx->CR1, ADC_CR1_SCAN, ScanMode);
1746 }
1747 
1748 /**
1749  * @brief Get ADC sequencers scan mode, for all ADC groups
1750  * (group regular, group injected).
1751  * @note According to sequencers scan mode :
1752  * - If disabled: ADC conversion is performed in unitary conversion
1753  * mode (one channel converted, that defined in rank 1).
1754  * Configuration of sequencers of all ADC groups
1755  * (sequencer scan length, ...) is discarded: equivalent to
1756  * scan length of 1 rank.
1757  * - If enabled: ADC conversions are performed in sequence conversions
1758  * mode, according to configuration of sequencers of
1759  * each ADC group (sequencer scan length, ...).
1760  * Refer to function @ref LL_ADC_REG_SetSequencerLength()
1761  * and to function @ref LL_ADC_INJ_SetSequencerLength().
1762  * @rmtoll CR1 SCAN LL_ADC_GetSequencersScanMode
1763  * @param ADCx ADC instance
1764  * @retval Returned value can be one of the following values:
1765  * @arg @ref LL_ADC_SEQ_SCAN_DISABLE
1766  * @arg @ref LL_ADC_SEQ_SCAN_ENABLE
1767  */
1768 __STATIC_INLINE uint32_t LL_ADC_GetSequencersScanMode(ADC_TypeDef *ADCx)
1769 {
1770  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_SCAN));
1771 }
1772 
1773 /**
1774  * @}
1775  */
1776 
1777 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
1778  * @{
1779  */
1780 
1781 /**
1782  * @brief Set ADC group regular conversion trigger source:
1783  * internal (SW start) or from external IP (timer event,
1784  * external interrupt line).
1785  * @note On this STM32 serie, external trigger is set with trigger polarity:
1786  * rising edge (only trigger polarity available on this STM32 serie).
1787  * @note Availability of parameters of trigger sources from timer
1788  * depends on timers availability on the selected device.
1789  * @rmtoll CR2 EXTSEL LL_ADC_REG_SetTriggerSource
1790  * @param ADCx ADC instance
1791  * @param TriggerSource This parameter can be one of the following values:
1792  * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
1793  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
1794  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
1795  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
1796  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
1797  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
1798  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
1799  * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
1800  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
1801  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
1802  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
1803  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
1804  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
1805  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
1806  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
1807  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
1808  *
1809  * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
1810  * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
1811  * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
1812  * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
1813  * @retval None
1814  */
1815 __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
1816 {
1817 /* Note: On this STM32 serie, ADC group regular external trigger edge */
1818 /* is used to perform a ADC conversion start. */
1819 /* This function does not set external trigger edge. */
1820 /* This feature is set using function */
1821 /* @ref LL_ADC_REG_StartConversionExtTrig(). */
1822  MODIFY_REG(ADCx->CR2, ADC_CR2_EXTSEL, (TriggerSource & ADC_CR2_EXTSEL));
1823 }
1824 
1825 /**
1826  * @brief Get ADC group regular conversion trigger source:
1827  * internal (SW start) or from external IP (timer event,
1828  * external interrupt line).
1829  * @note To determine whether group regular trigger source is
1830  * internal (SW start) or external, without detail
1831  * of which peripheral is selected as external trigger,
1832  * (equivalent to
1833  * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
1834  * use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
1835  * @note Availability of parameters of trigger sources from timer
1836  * depends on timers availability on the selected device.
1837  * @rmtoll CR2 EXTSEL LL_ADC_REG_GetTriggerSource
1838  * @param ADCx ADC instance
1839  * @retval Returned value can be one of the following values:
1840  * @arg @ref LL_ADC_REG_TRIG_SOFTWARE
1841  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3 (1)
1842  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1 (2)
1843  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2 (2)
1844  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2 (2)
1845  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO (2)
1846  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4 (2)
1847  * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (2)
1848  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (2)(4)
1849  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC3 (3)
1850  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1 (3)
1851  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3 (3)
1852  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1 (3)
1853  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO (3)
1854  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH1 (3)
1855  * @arg @ref LL_ADC_REG_TRIG_EXT_TIM5_CH3 (3)
1856  *
1857  * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
1858  * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
1859  * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
1860  * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
1861  */
1862 __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)
1863 {
1864  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL));
1865 }
1866 
1867 /**
1868  * @brief Get ADC group regular conversion trigger source internal (SW start)
1869  or external.
1870  * @note In case of group regular trigger source set to external trigger,
1871  * to determine which peripheral is selected as external trigger,
1872  * use function @ref LL_ADC_REG_GetTriggerSource().
1873  * @rmtoll CR2 EXTSEL LL_ADC_REG_IsTriggerSourceSWStart
1874  * @param ADCx ADC instance
1875  * @retval Value "0" if trigger source external trigger
1876  * Value "1" if trigger source SW start.
1877  */
1878 __STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
1879 {
1880  return (READ_BIT(ADCx->CR2, ADC_CR2_EXTSEL) == (LL_ADC_REG_TRIG_SOFTWARE));
1881 }
1882 
1883 
1884 /**
1885  * @brief Set ADC group regular sequencer length and scan direction.
1886  * @note Description of ADC group regular sequencer features:
1887  * - For devices with sequencer fully configurable
1888  * (function "LL_ADC_REG_SetSequencerRanks()" available):
1889  * sequencer length and each rank affectation to a channel
1890  * are configurable.
1891  * This function performs configuration of:
1892  * - Sequence length: Number of ranks in the scan sequence.
1893  * - Sequence direction: Unless specified in parameters, sequencer
1894  * scan direction is forward (from rank 1 to rank n).
1895  * Sequencer ranks are selected using
1896  * function "LL_ADC_REG_SetSequencerRanks()".
1897  * - For devices with sequencer not fully configurable
1898  * (function "LL_ADC_REG_SetSequencerChannels()" available):
1899  * sequencer length and each rank affectation to a channel
1900  * are defined by channel number.
1901  * This function performs configuration of:
1902  * - Sequence length: Number of ranks in the scan sequence is
1903  * defined by number of channels set in the sequence,
1904  * rank of each channel is fixed by channel HW number.
1905  * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
1906  * - Sequence direction: Unless specified in parameters, sequencer
1907  * scan direction is forward (from lowest channel number to
1908  * highest channel number).
1909  * Sequencer ranks are selected using
1910  * function "LL_ADC_REG_SetSequencerChannels()".
1911  * @note On this STM32 serie, group regular sequencer configuration
1912  * is conditioned to ADC instance sequencer mode.
1913  * If ADC instance sequencer mode is disabled, sequencers of
1914  * all groups (group regular, group injected) can be configured
1915  * but their execution is disabled (limited to rank 1).
1916  * Refer to function @ref LL_ADC_SetSequencersScanMode().
1917  * @note Sequencer disabled is equivalent to sequencer of 1 rank:
1918  * ADC conversion on only 1 channel.
1919  * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
1920  * @param ADCx ADC instance
1921  * @param SequencerNbRanks This parameter can be one of the following values:
1922  * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
1923  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
1924  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
1925  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
1926  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
1927  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
1928  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
1929  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
1930  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
1931  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
1932  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
1933  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
1934  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
1935  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
1936  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
1937  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
1938  * @retval None
1939  */
1940 __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
1941 {
1942  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
1943 }
1944 
1945 /**
1946  * @brief Get ADC group regular sequencer length and scan direction.
1947  * @note Description of ADC group regular sequencer features:
1948  * - For devices with sequencer fully configurable
1949  * (function "LL_ADC_REG_SetSequencerRanks()" available):
1950  * sequencer length and each rank affectation to a channel
1951  * are configurable.
1952  * This function retrieves:
1953  * - Sequence length: Number of ranks in the scan sequence.
1954  * - Sequence direction: Unless specified in parameters, sequencer
1955  * scan direction is forward (from rank 1 to rank n).
1956  * Sequencer ranks are selected using
1957  * function "LL_ADC_REG_SetSequencerRanks()".
1958  * - For devices with sequencer not fully configurable
1959  * (function "LL_ADC_REG_SetSequencerChannels()" available):
1960  * sequencer length and each rank affectation to a channel
1961  * are defined by channel number.
1962  * This function retrieves:
1963  * - Sequence length: Number of ranks in the scan sequence is
1964  * defined by number of channels set in the sequence,
1965  * rank of each channel is fixed by channel HW number.
1966  * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
1967  * - Sequence direction: Unless specified in parameters, sequencer
1968  * scan direction is forward (from lowest channel number to
1969  * highest channel number).
1970  * Sequencer ranks are selected using
1971  * function "LL_ADC_REG_SetSequencerChannels()".
1972  * @note On this STM32 serie, group regular sequencer configuration
1973  * is conditioned to ADC instance sequencer mode.
1974  * If ADC instance sequencer mode is disabled, sequencers of
1975  * all groups (group regular, group injected) can be configured
1976  * but their execution is disabled (limited to rank 1).
1977  * Refer to function @ref LL_ADC_SetSequencersScanMode().
1978  * @note Sequencer disabled is equivalent to sequencer of 1 rank:
1979  * ADC conversion on only 1 channel.
1980  * @rmtoll SQR1 L LL_ADC_REG_SetSequencerLength
1981  * @param ADCx ADC instance
1982  * @retval Returned value can be one of the following values:
1983  * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
1984  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
1985  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
1986  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
1987  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
1988  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
1989  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
1990  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
1991  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
1992  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
1993  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
1994  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
1995  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
1996  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
1997  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
1998  * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
1999  */
2000 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)
2001 {
2002  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
2003 }
2004 
2005 /**
2006  * @brief Set ADC group regular sequencer discontinuous mode:
2007  * sequence subdivided and scan conversions interrupted every selected
2008  * number of ranks.
2009  * @note It is not possible to enable both ADC group regular
2010  * continuous mode and sequencer discontinuous mode.
2011  * @note It is not possible to enable both ADC auto-injected mode
2012  * and ADC group regular sequencer discontinuous mode.
2013  * @rmtoll CR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n
2014  * CR1 DISCNUM LL_ADC_REG_SetSequencerDiscont
2015  * @param ADCx ADC instance
2016  * @param SeqDiscont This parameter can be one of the following values:
2017  * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2018  * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2019  * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2020  * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2021  * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2022  * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2023  * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2024  * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2025  * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2026  * @retval None
2027  */
2028 __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2029 {
2030  MODIFY_REG(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM, SeqDiscont);
2031 }
2032 
2033 /**
2034  * @brief Get ADC group regular sequencer discontinuous mode:
2035  * sequence subdivided and scan conversions interrupted every selected
2036  * number of ranks.
2037  * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n
2038  * CR1 DISCNUM LL_ADC_REG_GetSequencerDiscont
2039  * @param ADCx ADC instance
2040  * @retval Returned value can be one of the following values:
2041  * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
2042  * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
2043  * @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
2044  * @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
2045  * @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
2046  * @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
2047  * @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
2048  * @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
2049  * @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
2050  */
2051 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)
2052 {
2053  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_DISCEN | ADC_CR1_DISCNUM));
2054 }
2055 
2056 /**
2057  * @brief Set ADC group regular sequence: channel on the selected
2058  * scan sequence rank.
2059  * @note This function performs configuration of:
2060  * - Channels ordering into each rank of scan sequence:
2061  * whatever channel can be placed into whatever rank.
2062  * @note On this STM32 serie, ADC group regular sequencer is
2063  * fully configurable: sequencer length and each rank
2064  * affectation to a channel are configurable.
2065  * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2066  * @note Depending on devices and packages, some channels may not be available.
2067  * Refer to device datasheet for channels availability.
2068  * @note On this STM32 serie, to measure internal channels (VrefInt,
2069  * TempSensor, ...), measurement paths to internal channels must be
2070  * enabled separately.
2071  * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2072  * @rmtoll SQR3 SQ1 LL_ADC_REG_SetSequencerRanks\n
2073  * SQR3 SQ2 LL_ADC_REG_SetSequencerRanks\n
2074  * SQR3 SQ3 LL_ADC_REG_SetSequencerRanks\n
2075  * SQR3 SQ4 LL_ADC_REG_SetSequencerRanks\n
2076  * SQR3 SQ5 LL_ADC_REG_SetSequencerRanks\n
2077  * SQR3 SQ6 LL_ADC_REG_SetSequencerRanks\n
2078  * SQR2 SQ7 LL_ADC_REG_SetSequencerRanks\n
2079  * SQR2 SQ8 LL_ADC_REG_SetSequencerRanks\n
2080  * SQR2 SQ9 LL_ADC_REG_SetSequencerRanks\n
2081  * SQR2 SQ10 LL_ADC_REG_SetSequencerRanks\n
2082  * SQR2 SQ11 LL_ADC_REG_SetSequencerRanks\n
2083  * SQR2 SQ12 LL_ADC_REG_SetSequencerRanks\n
2084  * SQR1 SQ13 LL_ADC_REG_SetSequencerRanks\n
2085  * SQR1 SQ14 LL_ADC_REG_SetSequencerRanks\n
2086  * SQR1 SQ15 LL_ADC_REG_SetSequencerRanks\n
2087  * SQR1 SQ16 LL_ADC_REG_SetSequencerRanks
2088  * @param ADCx ADC instance
2089  * @param Rank This parameter can be one of the following values:
2090  * @arg @ref LL_ADC_REG_RANK_1
2091  * @arg @ref LL_ADC_REG_RANK_2
2092  * @arg @ref LL_ADC_REG_RANK_3
2093  * @arg @ref LL_ADC_REG_RANK_4
2094  * @arg @ref LL_ADC_REG_RANK_5
2095  * @arg @ref LL_ADC_REG_RANK_6
2096  * @arg @ref LL_ADC_REG_RANK_7
2097  * @arg @ref LL_ADC_REG_RANK_8
2098  * @arg @ref LL_ADC_REG_RANK_9
2099  * @arg @ref LL_ADC_REG_RANK_10
2100  * @arg @ref LL_ADC_REG_RANK_11
2101  * @arg @ref LL_ADC_REG_RANK_12
2102  * @arg @ref LL_ADC_REG_RANK_13
2103  * @arg @ref LL_ADC_REG_RANK_14
2104  * @arg @ref LL_ADC_REG_RANK_15
2105  * @arg @ref LL_ADC_REG_RANK_16
2106  * @param Channel This parameter can be one of the following values:
2107  * @arg @ref LL_ADC_CHANNEL_0
2108  * @arg @ref LL_ADC_CHANNEL_1
2109  * @arg @ref LL_ADC_CHANNEL_2
2110  * @arg @ref LL_ADC_CHANNEL_3
2111  * @arg @ref LL_ADC_CHANNEL_4
2112  * @arg @ref LL_ADC_CHANNEL_5
2113  * @arg @ref LL_ADC_CHANNEL_6
2114  * @arg @ref LL_ADC_CHANNEL_7
2115  * @arg @ref LL_ADC_CHANNEL_8
2116  * @arg @ref LL_ADC_CHANNEL_9
2117  * @arg @ref LL_ADC_CHANNEL_10
2118  * @arg @ref LL_ADC_CHANNEL_11
2119  * @arg @ref LL_ADC_CHANNEL_12
2120  * @arg @ref LL_ADC_CHANNEL_13
2121  * @arg @ref LL_ADC_CHANNEL_14
2122  * @arg @ref LL_ADC_CHANNEL_15
2123  * @arg @ref LL_ADC_CHANNEL_16
2124  * @arg @ref LL_ADC_CHANNEL_17
2125  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2126  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2127  *
2128  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
2129  * @retval None
2130  */
2131 __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2132 {
2133  /* Set bits with content of parameter "Channel" with bits position */
2134  /* in register and register position depending on parameter "Rank". */
2135  /* Parameters "Rank" and "Channel" are used with masks because containing */
2136  /* other bits reserved for other purpose. */
2137  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2138 
2139  MODIFY_REG(*preg,
2140  ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2141  (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2142 }
2143 
2144 /**
2145  * @brief Get ADC group regular sequence: channel on the selected
2146  * scan sequence rank.
2147  * @note On this STM32 serie, ADC group regular sequencer is
2148  * fully configurable: sequencer length and each rank
2149  * affectation to a channel are configurable.
2150  * Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
2151  * @note Depending on devices and packages, some channels may not be available.
2152  * Refer to device datasheet for channels availability.
2153  * @note Usage of the returned channel number:
2154  * - To reinject this channel into another function LL_ADC_xxx:
2155  * the returned channel number is only partly formatted on definition
2156  * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2157  * with parts of literals LL_ADC_CHANNEL_x or using
2158  * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2159  * Then the selected literal LL_ADC_CHANNEL_x can be used
2160  * as parameter for another function.
2161  * - To get the channel number in decimal format:
2162  * process the returned value with the helper macro
2163  * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2164  * @rmtoll SQR3 SQ1 LL_ADC_REG_GetSequencerRanks\n
2165  * SQR3 SQ2 LL_ADC_REG_GetSequencerRanks\n
2166  * SQR3 SQ3 LL_ADC_REG_GetSequencerRanks\n
2167  * SQR3 SQ4 LL_ADC_REG_GetSequencerRanks\n
2168  * SQR3 SQ5 LL_ADC_REG_GetSequencerRanks\n
2169  * SQR3 SQ6 LL_ADC_REG_GetSequencerRanks\n
2170  * SQR2 SQ7 LL_ADC_REG_GetSequencerRanks\n
2171  * SQR2 SQ8 LL_ADC_REG_GetSequencerRanks\n
2172  * SQR2 SQ9 LL_ADC_REG_GetSequencerRanks\n
2173  * SQR2 SQ10 LL_ADC_REG_GetSequencerRanks\n
2174  * SQR2 SQ11 LL_ADC_REG_GetSequencerRanks\n
2175  * SQR2 SQ12 LL_ADC_REG_GetSequencerRanks\n
2176  * SQR1 SQ13 LL_ADC_REG_GetSequencerRanks\n
2177  * SQR1 SQ14 LL_ADC_REG_GetSequencerRanks\n
2178  * SQR1 SQ15 LL_ADC_REG_GetSequencerRanks\n
2179  * SQR1 SQ16 LL_ADC_REG_GetSequencerRanks
2180  * @param ADCx ADC instance
2181  * @param Rank This parameter can be one of the following values:
2182  * @arg @ref LL_ADC_REG_RANK_1
2183  * @arg @ref LL_ADC_REG_RANK_2
2184  * @arg @ref LL_ADC_REG_RANK_3
2185  * @arg @ref LL_ADC_REG_RANK_4
2186  * @arg @ref LL_ADC_REG_RANK_5
2187  * @arg @ref LL_ADC_REG_RANK_6
2188  * @arg @ref LL_ADC_REG_RANK_7
2189  * @arg @ref LL_ADC_REG_RANK_8
2190  * @arg @ref LL_ADC_REG_RANK_9
2191  * @arg @ref LL_ADC_REG_RANK_10
2192  * @arg @ref LL_ADC_REG_RANK_11
2193  * @arg @ref LL_ADC_REG_RANK_12
2194  * @arg @ref LL_ADC_REG_RANK_13
2195  * @arg @ref LL_ADC_REG_RANK_14
2196  * @arg @ref LL_ADC_REG_RANK_15
2197  * @arg @ref LL_ADC_REG_RANK_16
2198  * @retval Returned value can be one of the following values:
2199  * @arg @ref LL_ADC_CHANNEL_0
2200  * @arg @ref LL_ADC_CHANNEL_1
2201  * @arg @ref LL_ADC_CHANNEL_2
2202  * @arg @ref LL_ADC_CHANNEL_3
2203  * @arg @ref LL_ADC_CHANNEL_4
2204  * @arg @ref LL_ADC_CHANNEL_5
2205  * @arg @ref LL_ADC_CHANNEL_6
2206  * @arg @ref LL_ADC_CHANNEL_7
2207  * @arg @ref LL_ADC_CHANNEL_8
2208  * @arg @ref LL_ADC_CHANNEL_9
2209  * @arg @ref LL_ADC_CHANNEL_10
2210  * @arg @ref LL_ADC_CHANNEL_11
2211  * @arg @ref LL_ADC_CHANNEL_12
2212  * @arg @ref LL_ADC_CHANNEL_13
2213  * @arg @ref LL_ADC_CHANNEL_14
2214  * @arg @ref LL_ADC_CHANNEL_15
2215  * @arg @ref LL_ADC_CHANNEL_16
2216  * @arg @ref LL_ADC_CHANNEL_17
2217  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2218  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2219  *
2220  * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
2221  * (1) For ADC channel read back from ADC register,
2222  * comparison with internal channel parameter to be done
2223  * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2224  */
2225 __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2226 {
2227  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2228 
2229  return (uint32_t) (READ_BIT(*preg,
2230  ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2231  >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2232  );
2233 }
2234 
2235 /**
2236  * @brief Set ADC continuous conversion mode on ADC group regular.
2237  * @note Description of ADC continuous conversion mode:
2238  * - single mode: one conversion per trigger
2239  * - continuous mode: after the first trigger, following
2240  * conversions launched successively automatically.
2241  * @note It is not possible to enable both ADC group regular
2242  * continuous mode and sequencer discontinuous mode.
2243  * @rmtoll CR2 CONT LL_ADC_REG_SetContinuousMode
2244  * @param ADCx ADC instance
2245  * @param Continuous This parameter can be one of the following values:
2246  * @arg @ref LL_ADC_REG_CONV_SINGLE
2247  * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2248  * @retval None
2249  */
2250 __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
2251 {
2252  MODIFY_REG(ADCx->CR2, ADC_CR2_CONT, Continuous);
2253 }
2254 
2255 /**
2256  * @brief Get ADC continuous conversion mode on ADC group regular.
2257  * @note Description of ADC continuous conversion mode:
2258  * - single mode: one conversion per trigger
2259  * - continuous mode: after the first trigger, following
2260  * conversions launched successively automatically.
2261  * @rmtoll CR2 CONT LL_ADC_REG_GetContinuousMode
2262  * @param ADCx ADC instance
2263  * @retval Returned value can be one of the following values:
2264  * @arg @ref LL_ADC_REG_CONV_SINGLE
2265  * @arg @ref LL_ADC_REG_CONV_CONTINUOUS
2266  */
2267 __STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)
2268 {
2269  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_CONT));
2270 }
2271 
2272 /**
2273  * @brief Set ADC group regular conversion data transfer: no transfer or
2274  * transfer by DMA, and DMA requests mode.
2275  * @note If transfer by DMA selected, specifies the DMA requests
2276  * mode:
2277  * - Limited mode (One shot mode): DMA transfer requests are stopped
2278  * when number of DMA data transfers (number of
2279  * ADC conversions) is reached.
2280  * This ADC mode is intended to be used with DMA mode non-circular.
2281  * - Unlimited mode: DMA transfer requests are unlimited,
2282  * whatever number of DMA data transfers (number of
2283  * ADC conversions).
2284  * This ADC mode is intended to be used with DMA mode circular.
2285  * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2286  * mode non-circular:
2287  * when DMA transfers size will be reached, DMA will stop transfers of
2288  * ADC conversions data ADC will raise an overrun error
2289  * (overrun flag and interruption if enabled).
2290  * @note To configure DMA source address (peripheral address),
2291  * use function @ref LL_ADC_DMA_GetRegAddr().
2292  * @rmtoll CR2 DMA LL_ADC_REG_SetDMATransfer
2293  * @param ADCx ADC instance
2294  * @param DMATransfer This parameter can be one of the following values:
2295  * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2296  * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2297  * @retval None
2298  */
2299 __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
2300 {
2301  MODIFY_REG(ADCx->CR2, ADC_CR2_DMA, DMATransfer);
2302 }
2303 
2304 /**
2305  * @brief Get ADC group regular conversion data transfer: no transfer or
2306  * transfer by DMA, and DMA requests mode.
2307  * @note If transfer by DMA selected, specifies the DMA requests
2308  * mode:
2309  * - Limited mode (One shot mode): DMA transfer requests are stopped
2310  * when number of DMA data transfers (number of
2311  * ADC conversions) is reached.
2312  * This ADC mode is intended to be used with DMA mode non-circular.
2313  * - Unlimited mode: DMA transfer requests are unlimited,
2314  * whatever number of DMA data transfers (number of
2315  * ADC conversions).
2316  * This ADC mode is intended to be used with DMA mode circular.
2317  * @note If ADC DMA requests mode is set to unlimited and DMA is set to
2318  * mode non-circular:
2319  * when DMA transfers size will be reached, DMA will stop transfers of
2320  * ADC conversions data ADC will raise an overrun error
2321  * (overrun flag and interruption if enabled).
2322  * @note To configure DMA source address (peripheral address),
2323  * use function @ref LL_ADC_DMA_GetRegAddr().
2324  * @rmtoll CR2 DMA LL_ADC_REG_GetDMATransfer
2325  * @param ADCx ADC instance
2326  * @retval Returned value can be one of the following values:
2327  * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
2328  * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
2329  */
2330 __STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx)
2331 {
2332  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_DMA));
2333 }
2334 
2335 /**
2336  * @}
2337  */
2338 
2339 /** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
2340  * @{
2341  */
2342 
2343 /**
2344  * @brief Set ADC group injected conversion trigger source:
2345  * internal (SW start) or from external IP (timer event,
2346  * external interrupt line).
2347  * @note On this STM32 serie, external trigger is set with trigger polarity:
2348  * rising edge (only trigger polarity available on this STM32 serie).
2349  * @note Availability of parameters of trigger sources from timer
2350  * depends on timers availability on the selected device.
2351  * @rmtoll CR2 JEXTSEL LL_ADC_INJ_SetTriggerSource
2352  * @param ADCx ADC instance
2353  * @param TriggerSource This parameter can be one of the following values:
2354  * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2355  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
2356  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
2357  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
2358  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
2359  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
2360  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
2361  * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
2362  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
2363  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
2364  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
2365  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
2366  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
2367  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
2368  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
2369  *
2370  * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
2371  * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
2372  * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
2373  * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
2374  * @retval None
2375  */
2376 __STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
2377 {
2378 /* Note: On this STM32 serie, ADC group injected external trigger edge */
2379 /* is used to perform a ADC conversion start. */
2380 /* This function does not set external trigger edge. */
2381 /* This feature is set using function */
2382 /* @ref LL_ADC_INJ_StartConversionExtTrig(). */
2383  MODIFY_REG(ADCx->CR2, ADC_CR2_JEXTSEL, (TriggerSource & ADC_CR2_JEXTSEL));
2384 }
2385 
2386 /**
2387  * @brief Get ADC group injected conversion trigger source:
2388  * internal (SW start) or from external IP (timer event,
2389  * external interrupt line).
2390  * @note To determine whether group injected trigger source is
2391  * internal (SW start) or external, without detail
2392  * of which peripheral is selected as external trigger,
2393  * (equivalent to
2394  * "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
2395  * use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
2396  * @note Availability of parameters of trigger sources from timer
2397  * depends on timers availability on the selected device.
2398  * @rmtoll CR2 JEXTSEL LL_ADC_INJ_GetTriggerSource
2399  * @param ADCx ADC instance
2400  * @retval Returned value can be one of the following values:
2401  * @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
2402  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO (1)
2403  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4 (1)
2404  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO (2)
2405  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1 (2)
2406  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4 (2)
2407  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO (2)
2408  * @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15 (2)
2409  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (2)(4)
2410  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC3 (3)
2411  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3 (3)
2412  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2 (3)
2413  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4 (3)
2414  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_TRGO (3)
2415  * @arg @ref LL_ADC_INJ_TRIG_EXT_TIM5_CH4 (3)
2416  *
2417  * (1) On STM32F1, parameter available on all ADC instances: ADC1, ADC2, ADC3 (for ADC instances ADCx available on the selected device).\n
2418  * (2) On STM32F1, parameter available only on ADC instances: ADC1, ADC2 (for ADC instances ADCx available on the selected device).\n
2419  * (3) On STM32F1, parameter available only on ADC instances: ADC3 (for ADC instances ADCx available on the selected device).\n
2420  * (4) On STM32F1, parameter available only on high-density and XL-density devices. A remap of trigger must be done at top level (refer to AFIO peripheral).
2421  */
2422 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)
2423 {
2424  return (uint32_t)(READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL));
2425 }
2426 
2427 /**
2428  * @brief Get ADC group injected conversion trigger source internal (SW start)
2429  or external
2430  * @note In case of group injected trigger source set to external trigger,
2431  * to determine which peripheral is selected as external trigger,
2432  * use function @ref LL_ADC_INJ_GetTriggerSource.
2433  * @rmtoll CR2 JEXTSEL LL_ADC_INJ_IsTriggerSourceSWStart
2434  * @param ADCx ADC instance
2435  * @retval Value "0" if trigger source external trigger
2436  * Value "1" if trigger source SW start.
2437  */
2438 __STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)
2439 {
2440  return (READ_BIT(ADCx->CR2, ADC_CR2_JEXTSEL) == LL_ADC_INJ_TRIG_SOFTWARE);
2441 }
2442 
2443 /**
2444  * @brief Set ADC group injected sequencer length and scan direction.
2445  * @note This function performs configuration of:
2446  * - Sequence length: Number of ranks in the scan sequence.
2447  * - Sequence direction: Unless specified in parameters, sequencer
2448  * scan direction is forward (from rank 1 to rank n).
2449  * @note On this STM32 serie, group injected sequencer configuration
2450  * is conditioned to ADC instance sequencer mode.
2451  * If ADC instance sequencer mode is disabled, sequencers of
2452  * all groups (group regular, group injected) can be configured
2453  * but their execution is disabled (limited to rank 1).
2454  * Refer to function @ref LL_ADC_SetSequencersScanMode().
2455  * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2456  * ADC conversion on only 1 channel.
2457  * @rmtoll JSQR JL LL_ADC_INJ_SetSequencerLength
2458  * @param ADCx ADC instance
2459  * @param SequencerNbRanks This parameter can be one of the following values:
2460  * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2461  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2462  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2463  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2464  * @retval None
2465  */
2466 __STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
2467 {
2468  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
2469 }
2470 
2471 /**
2472  * @brief Get ADC group injected sequencer length and scan direction.
2473  * @note This function retrieves:
2474  * - Sequence length: Number of ranks in the scan sequence.
2475  * - Sequence direction: Unless specified in parameters, sequencer
2476  * scan direction is forward (from rank 1 to rank n).
2477  * @note On this STM32 serie, group injected sequencer configuration
2478  * is conditioned to ADC instance sequencer mode.
2479  * If ADC instance sequencer mode is disabled, sequencers of
2480  * all groups (group regular, group injected) can be configured
2481  * but their execution is disabled (limited to rank 1).
2482  * Refer to function @ref LL_ADC_SetSequencersScanMode().
2483  * @note Sequencer disabled is equivalent to sequencer of 1 rank:
2484  * ADC conversion on only 1 channel.
2485  * @rmtoll JSQR JL LL_ADC_INJ_GetSequencerLength
2486  * @param ADCx ADC instance
2487  * @retval Returned value can be one of the following values:
2488  * @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
2489  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
2490  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
2491  * @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
2492  */
2493 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)
2494 {
2495  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
2496 }
2497 
2498 /**
2499  * @brief Set ADC group injected sequencer discontinuous mode:
2500  * sequence subdivided and scan conversions interrupted every selected
2501  * number of ranks.
2502  * @note It is not possible to enable both ADC group injected
2503  * auto-injected mode and sequencer discontinuous mode.
2504  * @rmtoll CR1 DISCEN LL_ADC_INJ_SetSequencerDiscont
2505  * @param ADCx ADC instance
2506  * @param SeqDiscont This parameter can be one of the following values:
2507  * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2508  * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2509  * @retval None
2510  */
2511 __STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
2512 {
2513  MODIFY_REG(ADCx->CR1, ADC_CR1_JDISCEN, SeqDiscont);
2514 }
2515 
2516 /**
2517  * @brief Get ADC group injected sequencer discontinuous mode:
2518  * sequence subdivided and scan conversions interrupted every selected
2519  * number of ranks.
2520  * @rmtoll CR1 DISCEN LL_ADC_REG_GetSequencerDiscont
2521  * @param ADCx ADC instance
2522  * @retval Returned value can be one of the following values:
2523  * @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
2524  * @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
2525  */
2526 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)
2527 {
2528  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JDISCEN));
2529 }
2530 
2531 /**
2532  * @brief Set ADC group injected sequence: channel on the selected
2533  * sequence rank.
2534  * @note Depending on devices and packages, some channels may not be available.
2535  * Refer to device datasheet for channels availability.
2536  * @note On this STM32 serie, to measure internal channels (VrefInt,
2537  * TempSensor, ...), measurement paths to internal channels must be
2538  * enabled separately.
2539  * This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
2540  * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2541  * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2542  * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2543  * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2544  * @param ADCx ADC instance
2545  * @param Rank This parameter can be one of the following values:
2546  * @arg @ref LL_ADC_INJ_RANK_1
2547  * @arg @ref LL_ADC_INJ_RANK_2
2548  * @arg @ref LL_ADC_INJ_RANK_3
2549  * @arg @ref LL_ADC_INJ_RANK_4
2550  * @param Channel This parameter can be one of the following values:
2551  * @arg @ref LL_ADC_CHANNEL_0
2552  * @arg @ref LL_ADC_CHANNEL_1
2553  * @arg @ref LL_ADC_CHANNEL_2
2554  * @arg @ref LL_ADC_CHANNEL_3
2555  * @arg @ref LL_ADC_CHANNEL_4
2556  * @arg @ref LL_ADC_CHANNEL_5
2557  * @arg @ref LL_ADC_CHANNEL_6
2558  * @arg @ref LL_ADC_CHANNEL_7
2559  * @arg @ref LL_ADC_CHANNEL_8
2560  * @arg @ref LL_ADC_CHANNEL_9
2561  * @arg @ref LL_ADC_CHANNEL_10
2562  * @arg @ref LL_ADC_CHANNEL_11
2563  * @arg @ref LL_ADC_CHANNEL_12
2564  * @arg @ref LL_ADC_CHANNEL_13
2565  * @arg @ref LL_ADC_CHANNEL_14
2566  * @arg @ref LL_ADC_CHANNEL_15
2567  * @arg @ref LL_ADC_CHANNEL_16
2568  * @arg @ref LL_ADC_CHANNEL_17
2569  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2570  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2571  *
2572  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
2573  * @retval None
2574  */
2575 __STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
2576 {
2577  /* Set bits with content of parameter "Channel" with bits position */
2578  /* in register depending on parameter "Rank". */
2579  /* Parameters "Rank" and "Channel" are used with masks because containing */
2580  /* other bits reserved for other purpose. */
2581  register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2582 
2583  MODIFY_REG(ADCx->JSQR,
2584  ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))),
2585  (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))));
2586 }
2587 
2588 /**
2589  * @brief Get ADC group injected sequence: channel on the selected
2590  * sequence rank.
2591  * @note Depending on devices and packages, some channels may not be available.
2592  * Refer to device datasheet for channels availability.
2593  * @note Usage of the returned channel number:
2594  * - To reinject this channel into another function LL_ADC_xxx:
2595  * the returned channel number is only partly formatted on definition
2596  * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
2597  * with parts of literals LL_ADC_CHANNEL_x or using
2598  * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2599  * Then the selected literal LL_ADC_CHANNEL_x can be used
2600  * as parameter for another function.
2601  * - To get the channel number in decimal format:
2602  * process the returned value with the helper macro
2603  * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
2604  * @rmtoll JSQR JSQ1 LL_ADC_INJ_SetSequencerRanks\n
2605  * JSQR JSQ2 LL_ADC_INJ_SetSequencerRanks\n
2606  * JSQR JSQ3 LL_ADC_INJ_SetSequencerRanks\n
2607  * JSQR JSQ4 LL_ADC_INJ_SetSequencerRanks
2608  * @param ADCx ADC instance
2609  * @param Rank This parameter can be one of the following values:
2610  * @arg @ref LL_ADC_INJ_RANK_1
2611  * @arg @ref LL_ADC_INJ_RANK_2
2612  * @arg @ref LL_ADC_INJ_RANK_3
2613  * @arg @ref LL_ADC_INJ_RANK_4
2614  * @retval Returned value can be one of the following values:
2615  * @arg @ref LL_ADC_CHANNEL_0
2616  * @arg @ref LL_ADC_CHANNEL_1
2617  * @arg @ref LL_ADC_CHANNEL_2
2618  * @arg @ref LL_ADC_CHANNEL_3
2619  * @arg @ref LL_ADC_CHANNEL_4
2620  * @arg @ref LL_ADC_CHANNEL_5
2621  * @arg @ref LL_ADC_CHANNEL_6
2622  * @arg @ref LL_ADC_CHANNEL_7
2623  * @arg @ref LL_ADC_CHANNEL_8
2624  * @arg @ref LL_ADC_CHANNEL_9
2625  * @arg @ref LL_ADC_CHANNEL_10
2626  * @arg @ref LL_ADC_CHANNEL_11
2627  * @arg @ref LL_ADC_CHANNEL_12
2628  * @arg @ref LL_ADC_CHANNEL_13
2629  * @arg @ref LL_ADC_CHANNEL_14
2630  * @arg @ref LL_ADC_CHANNEL_15
2631  * @arg @ref LL_ADC_CHANNEL_16
2632  * @arg @ref LL_ADC_CHANNEL_17
2633  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2634  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2635  *
2636  * (1) On STM32F1, parameter available only on ADC instance: ADC1.\n
2637  * (1) For ADC channel read back from ADC register,
2638  * comparison with internal channel parameter to be done
2639  * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2640  */
2641 __STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2642 {
2643  register uint32_t tmpreg1 = (READ_BIT(ADCx->JSQR, ADC_JSQR_JL) >> ADC_JSQR_JL_Pos) + 1U;
2644 
2645  return (uint32_t)(READ_BIT(ADCx->JSQR,
2646  ADC_CHANNEL_ID_NUMBER_MASK << (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1))))
2647  >> (5U * (uint8_t)(((Rank) + 3U) - (tmpreg1)))
2648  );
2649 }
2650 
2651 /**
2652  * @brief Set ADC group injected conversion trigger:
2653  * independent or from ADC group regular.
2654  * @note This mode can be used to extend number of data registers
2655  * updated after one ADC conversion trigger and with data
2656  * permanently kept (not erased by successive conversions of scan of
2657  * ADC sequencer ranks), up to 5 data registers:
2658  * 1 data register on ADC group regular, 4 data registers
2659  * on ADC group injected.
2660  * @note If ADC group injected injected trigger source is set to an
2661  * external trigger, this feature must be must be set to
2662  * independent trigger.
2663  * ADC group injected automatic trigger is compliant only with
2664  * group injected trigger source set to SW start, without any
2665  * further action on ADC group injected conversion start or stop:
2666  * in this case, ADC group injected is controlled only
2667  * from ADC group regular.
2668  * @note It is not possible to enable both ADC group injected
2669  * auto-injected mode and sequencer discontinuous mode.
2670  * @rmtoll CR1 JAUTO LL_ADC_INJ_SetTrigAuto
2671  * @param ADCx ADC instance
2672  * @param TrigAuto This parameter can be one of the following values:
2673  * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
2674  * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
2675  * @retval None
2676  */
2677 __STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
2678 {
2679  MODIFY_REG(ADCx->CR1, ADC_CR1_JAUTO, TrigAuto);
2680 }
2681 
2682 /**
2683  * @brief Get ADC group injected conversion trigger:
2684  * independent or from ADC group regular.
2685  * @rmtoll CR1 JAUTO LL_ADC_INJ_GetTrigAuto
2686  * @param ADCx ADC instance
2687  * @retval Returned value can be one of the following values:
2688  * @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
2689  * @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
2690  */
2691 __STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)
2692 {
2693  return (uint32_t)(READ_BIT(ADCx->CR1, ADC_CR1_JAUTO));
2694 }
2695 
2696 /**
2697  * @brief Set ADC group injected offset.
2698  * @note It sets:
2699  * - ADC group injected rank to which the offset programmed
2700  * will be applied
2701  * - Offset level (offset to be subtracted from the raw
2702  * converted data).
2703  * Caution: Offset format is dependent to ADC resolution:
2704  * offset has to be left-aligned on bit 11, the LSB (right bits)
2705  * are set to 0.
2706  * @note Offset cannot be enabled or disabled.
2707  * To emulate offset disabled, set an offset value equal to 0.
2708  * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_SetOffset\n
2709  * JOFR2 JOFFSET2 LL_ADC_INJ_SetOffset\n
2710  * JOFR3 JOFFSET3 LL_ADC_INJ_SetOffset\n
2711  * JOFR4 JOFFSET4 LL_ADC_INJ_SetOffset
2712  * @param ADCx ADC instance
2713  * @param Rank This parameter can be one of the following values:
2714  * @arg @ref LL_ADC_INJ_RANK_1
2715  * @arg @ref LL_ADC_INJ_RANK_2
2716  * @arg @ref LL_ADC_INJ_RANK_3
2717  * @arg @ref LL_ADC_INJ_RANK_4
2718  * @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2719  * @retval None
2720  */
2721 __STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
2722 {
2723  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
2724 
2725  MODIFY_REG(*preg,
2726  ADC_JOFR1_JOFFSET1,
2727  OffsetLevel);
2728 }
2729 
2730 /**
2731  * @brief Get ADC group injected offset.
2732  * @note It gives offset level (offset to be subtracted from the raw converted data).
2733  * Caution: Offset format is dependent to ADC resolution:
2734  * offset has to be left-aligned on bit 11, the LSB (right bits)
2735  * are set to 0.
2736  * @rmtoll JOFR1 JOFFSET1 LL_ADC_INJ_GetOffset\n
2737  * JOFR2 JOFFSET2 LL_ADC_INJ_GetOffset\n
2738  * JOFR3 JOFFSET3 LL_ADC_INJ_GetOffset\n
2739  * JOFR4 JOFFSET4 LL_ADC_INJ_GetOffset
2740  * @param ADCx ADC instance
2741  * @param Rank This parameter can be one of the following values:
2742  * @arg @ref LL_ADC_INJ_RANK_1
2743  * @arg @ref LL_ADC_INJ_RANK_2
2744  * @arg @ref LL_ADC_INJ_RANK_3
2745  * @arg @ref LL_ADC_INJ_RANK_4
2746  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2747  */
2748 __STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
2749 {
2750  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
2751 
2752  return (uint32_t)(READ_BIT(*preg,
2753  ADC_JOFR1_JOFFSET1)
2754  );
2755 }
2756 
2757 /**
2758  * @}
2759  */
2760 
2761 /** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
2762  * @{
2763  */
2764 
2765 /**
2766  * @brief Set sampling time of the selected ADC channel
2767  * Unit: ADC clock cycles.
2768  * @note On this device, sampling time is on channel scope: independently
2769  * of channel mapped on ADC group regular or injected.
2770  * @note In case of internal channel (VrefInt, TempSensor, ...) to be
2771  * converted:
2772  * sampling time constraints must be respected (sampling time can be
2773  * adjusted in function of ADC clock frequency and sampling time
2774  * setting).
2775  * Refer to device datasheet for timings values (parameters TS_vrefint,
2776  * TS_temp, ...).
2777  * @note Conversion time is the addition of sampling time and processing time.
2778  * Refer to reference manual for ADC processing time of
2779  * this STM32 serie.
2780  * @note In case of ADC conversion of internal channel (VrefInt,
2781  * temperature sensor, ...), a sampling time minimum value
2782  * is required.
2783  * Refer to device datasheet.
2784  * @rmtoll SMPR1 SMP17 LL_ADC_SetChannelSamplingTime\n
2785  * SMPR1 SMP16 LL_ADC_SetChannelSamplingTime\n
2786  * SMPR1 SMP15 LL_ADC_SetChannelSamplingTime\n
2787  * SMPR1 SMP14 LL_ADC_SetChannelSamplingTime\n
2788  * SMPR1 SMP13 LL_ADC_SetChannelSamplingTime\n
2789  * SMPR1 SMP12 LL_ADC_SetChannelSamplingTime\n
2790  * SMPR1 SMP11 LL_ADC_SetChannelSamplingTime\n
2791  * SMPR1 SMP10 LL_ADC_SetChannelSamplingTime\n
2792  * SMPR2 SMP9 LL_ADC_SetChannelSamplingTime\n
2793  * SMPR2 SMP8 LL_ADC_SetChannelSamplingTime\n
2794  * SMPR2 SMP7 LL_ADC_SetChannelSamplingTime\n
2795  * SMPR2 SMP6 LL_ADC_SetChannelSamplingTime\n
2796  * SMPR2 SMP5 LL_ADC_SetChannelSamplingTime\n
2797  * SMPR2 SMP4 LL_ADC_SetChannelSamplingTime\n
2798  * SMPR2 SMP3 LL_ADC_SetChannelSamplingTime\n
2799  * SMPR2 SMP2 LL_ADC_SetChannelSamplingTime\n
2800  * SMPR2 SMP1 LL_ADC_SetChannelSamplingTime\n
2801  * SMPR2 SMP0 LL_ADC_SetChannelSamplingTime
2802  * @param ADCx ADC instance
2803  * @param Channel This parameter can be one of the following values:
2804  * @arg @ref LL_ADC_CHANNEL_0
2805  * @arg @ref LL_ADC_CHANNEL_1
2806  * @arg @ref LL_ADC_CHANNEL_2
2807  * @arg @ref LL_ADC_CHANNEL_3
2808  * @arg @ref LL_ADC_CHANNEL_4
2809  * @arg @ref LL_ADC_CHANNEL_5
2810  * @arg @ref LL_ADC_CHANNEL_6
2811  * @arg @ref LL_ADC_CHANNEL_7
2812  * @arg @ref LL_ADC_CHANNEL_8
2813  * @arg @ref LL_ADC_CHANNEL_9
2814  * @arg @ref LL_ADC_CHANNEL_10
2815  * @arg @ref LL_ADC_CHANNEL_11
2816  * @arg @ref LL_ADC_CHANNEL_12
2817  * @arg @ref LL_ADC_CHANNEL_13
2818  * @arg @ref LL_ADC_CHANNEL_14
2819  * @arg @ref LL_ADC_CHANNEL_15
2820  * @arg @ref LL_ADC_CHANNEL_16
2821  * @arg @ref LL_ADC_CHANNEL_17
2822  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2823  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2824  *
2825  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
2826  * @param SamplingTime This parameter can be one of the following values:
2827  * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2828  * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2829  * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
2830  * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
2831  * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
2832  * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
2833  * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
2834  * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
2835  * @retval None
2836  */
2837 __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
2838 {
2839  /* Set bits with content of parameter "SamplingTime" with bits position */
2840  /* in register and register position depending on parameter "Channel". */
2841  /* Parameter "Channel" is used with masks because containing */
2842  /* other bits reserved for other purpose. */
2843  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
2844 
2845  MODIFY_REG(*preg,
2846  ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
2847  SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
2848 }
2849 
2850 /**
2851  * @brief Get sampling time of the selected ADC channel
2852  * Unit: ADC clock cycles.
2853  * @note On this device, sampling time is on channel scope: independently
2854  * of channel mapped on ADC group regular or injected.
2855  * @note Conversion time is the addition of sampling time and processing time.
2856  * Refer to reference manual for ADC processing time of
2857  * this STM32 serie.
2858  * @rmtoll SMPR1 SMP17 LL_ADC_GetChannelSamplingTime\n
2859  * SMPR1 SMP16 LL_ADC_GetChannelSamplingTime\n
2860  * SMPR1 SMP15 LL_ADC_GetChannelSamplingTime\n
2861  * SMPR1 SMP14 LL_ADC_GetChannelSamplingTime\n
2862  * SMPR1 SMP13 LL_ADC_GetChannelSamplingTime\n
2863  * SMPR1 SMP12 LL_ADC_GetChannelSamplingTime\n
2864  * SMPR1 SMP11 LL_ADC_GetChannelSamplingTime\n
2865  * SMPR1 SMP10 LL_ADC_GetChannelSamplingTime\n
2866  * SMPR2 SMP9 LL_ADC_GetChannelSamplingTime\n
2867  * SMPR2 SMP8 LL_ADC_GetChannelSamplingTime\n
2868  * SMPR2 SMP7 LL_ADC_GetChannelSamplingTime\n
2869  * SMPR2 SMP6 LL_ADC_GetChannelSamplingTime\n
2870  * SMPR2 SMP5 LL_ADC_GetChannelSamplingTime\n
2871  * SMPR2 SMP4 LL_ADC_GetChannelSamplingTime\n
2872  * SMPR2 SMP3 LL_ADC_GetChannelSamplingTime\n
2873  * SMPR2 SMP2 LL_ADC_GetChannelSamplingTime\n
2874  * SMPR2 SMP1 LL_ADC_GetChannelSamplingTime\n
2875  * SMPR2 SMP0 LL_ADC_GetChannelSamplingTime
2876  * @param ADCx ADC instance
2877  * @param Channel This parameter can be one of the following values:
2878  * @arg @ref LL_ADC_CHANNEL_0
2879  * @arg @ref LL_ADC_CHANNEL_1
2880  * @arg @ref LL_ADC_CHANNEL_2
2881  * @arg @ref LL_ADC_CHANNEL_3
2882  * @arg @ref LL_ADC_CHANNEL_4
2883  * @arg @ref LL_ADC_CHANNEL_5
2884  * @arg @ref LL_ADC_CHANNEL_6
2885  * @arg @ref LL_ADC_CHANNEL_7
2886  * @arg @ref LL_ADC_CHANNEL_8
2887  * @arg @ref LL_ADC_CHANNEL_9
2888  * @arg @ref LL_ADC_CHANNEL_10
2889  * @arg @ref LL_ADC_CHANNEL_11
2890  * @arg @ref LL_ADC_CHANNEL_12
2891  * @arg @ref LL_ADC_CHANNEL_13
2892  * @arg @ref LL_ADC_CHANNEL_14
2893  * @arg @ref LL_ADC_CHANNEL_15
2894  * @arg @ref LL_ADC_CHANNEL_16
2895  * @arg @ref LL_ADC_CHANNEL_17
2896  * @arg @ref LL_ADC_CHANNEL_VREFINT (1)
2897  * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1)
2898  *
2899  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
2900  * @retval Returned value can be one of the following values:
2901  * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
2902  * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
2903  * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5
2904  * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5
2905  * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5
2906  * @arg @ref LL_ADC_SAMPLINGTIME_55CYCLES_5
2907  * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
2908  * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
2909  */
2910 __STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
2911 {
2912  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
2913 
2914  return (uint32_t)(READ_BIT(*preg,
2915  ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
2916  >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
2917  );
2918 }
2919 
2920 /**
2921  * @}
2922  */
2923 
2924 /** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
2925  * @{
2926  */
2927 
2928 /**
2929  * @brief Set ADC analog watchdog monitored channels:
2930  * a single channel or all channels,
2931  * on ADC groups regular and-or injected.
2932  * @note Once monitored channels are selected, analog watchdog
2933  * is enabled.
2934  * @note In case of need to define a single channel to monitor
2935  * with analog watchdog from sequencer channel definition,
2936  * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
2937  * @note On this STM32 serie, there is only 1 kind of analog watchdog
2938  * instance:
2939  * - AWD standard (instance AWD1):
2940  * - channels monitored: can monitor 1 channel or all channels.
2941  * - groups monitored: ADC groups regular and-or injected.
2942  * - resolution: resolution is not limited (corresponds to
2943  * ADC resolution configured).
2944  * @rmtoll CR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n
2945  * CR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n
2946  * CR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels
2947  * @param ADCx ADC instance
2948  * @param AWDChannelGroup This parameter can be one of the following values:
2949  * @arg @ref LL_ADC_AWD_DISABLE
2950  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
2951  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
2952  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
2953  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
2954  * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
2955  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
2956  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
2957  * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
2958  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
2959  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
2960  * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
2961  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
2962  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
2963  * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
2964  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
2965  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
2966  * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
2967  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
2968  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
2969  * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
2970  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
2971  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
2972  * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
2973  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
2974  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
2975  * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
2976  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
2977  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
2978  * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
2979  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
2980  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
2981  * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
2982  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
2983  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
2984  * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
2985  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
2986  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
2987  * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
2988  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
2989  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
2990  * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
2991  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
2992  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
2993  * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
2994  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
2995  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
2996  * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
2997  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
2998  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
2999  * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3000  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3001  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3002  * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3003  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3004  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3005  * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3006  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3007  * @arg @ref LL_ADC_AWD_CH_VREFINT_REG (1)
3008  * @arg @ref LL_ADC_AWD_CH_VREFINT_INJ (1)
3009  * @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ (1)
3010  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG (1)
3011  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ (1)
3012  * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ (1)
3013  *
3014  * (1) On STM32F1, parameter available only on ADC instance: ADC1.
3015  * @retval None
3016  */
3017 __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup)
3018 {
3019  MODIFY_REG(ADCx->CR1,
3020  (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH),
3021  AWDChannelGroup);
3022 }
3023 
3024 /**
3025  * @brief Get ADC analog watchdog monitored channel.
3026  * @note Usage of the returned channel number:
3027  * - To reinject this channel into another function LL_ADC_xxx:
3028  * the returned channel number is only partly formatted on definition
3029  * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
3030  * with parts of literals LL_ADC_CHANNEL_x or using
3031  * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3032  * Then the selected literal LL_ADC_CHANNEL_x can be used
3033  * as parameter for another function.
3034  * - To get the channel number in decimal format:
3035  * process the returned value with the helper macro
3036  * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
3037  * Applicable only when the analog watchdog is set to monitor
3038  * one channel.
3039  * @note On this STM32 serie, there is only 1 kind of analog watchdog
3040  * instance:
3041  * - AWD standard (instance AWD1):
3042  * - channels monitored: can monitor 1 channel or all channels.
3043  * - groups monitored: ADC groups regular and-or injected.
3044  * - resolution: resolution is not limited (corresponds to
3045  * ADC resolution configured).
3046  * @rmtoll CR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n
3047  * CR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n
3048  * CR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels
3049  * @param ADCx ADC instance
3050  * @retval Returned value can be one of the following values:
3051  * @arg @ref LL_ADC_AWD_DISABLE
3052  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
3053  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ
3054  * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
3055  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG
3056  * @arg @ref LL_ADC_AWD_CHANNEL_0_INJ
3057  * @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
3058  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG
3059  * @arg @ref LL_ADC_AWD_CHANNEL_1_INJ
3060  * @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
3061  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG
3062  * @arg @ref LL_ADC_AWD_CHANNEL_2_INJ
3063  * @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
3064  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG
3065  * @arg @ref LL_ADC_AWD_CHANNEL_3_INJ
3066  * @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
3067  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG
3068  * @arg @ref LL_ADC_AWD_CHANNEL_4_INJ
3069  * @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
3070  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG
3071  * @arg @ref LL_ADC_AWD_CHANNEL_5_INJ
3072  * @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
3073  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG
3074  * @arg @ref LL_ADC_AWD_CHANNEL_6_INJ
3075  * @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
3076  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG
3077  * @arg @ref LL_ADC_AWD_CHANNEL_7_INJ
3078  * @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
3079  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG
3080  * @arg @ref LL_ADC_AWD_CHANNEL_8_INJ
3081  * @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
3082  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG
3083  * @arg @ref LL_ADC_AWD_CHANNEL_9_INJ
3084  * @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
3085  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG
3086  * @arg @ref LL_ADC_AWD_CHANNEL_10_INJ
3087  * @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
3088  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG
3089  * @arg @ref LL_ADC_AWD_CHANNEL_11_INJ
3090  * @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
3091  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG
3092  * @arg @ref LL_ADC_AWD_CHANNEL_12_INJ
3093  * @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
3094  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG
3095  * @arg @ref LL_ADC_AWD_CHANNEL_13_INJ
3096  * @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
3097  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG
3098  * @arg @ref LL_ADC_AWD_CHANNEL_14_INJ
3099  * @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
3100  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG
3101  * @arg @ref LL_ADC_AWD_CHANNEL_15_INJ
3102  * @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
3103  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG
3104  * @arg @ref LL_ADC_AWD_CHANNEL_16_INJ
3105  * @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
3106  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG
3107  * @arg @ref LL_ADC_AWD_CHANNEL_17_INJ
3108  * @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
3109  */
3110 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx)
3111 {
3112  return (uint32_t)(READ_BIT(ADCx->CR1, (ADC_CR1_AWDEN | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL | ADC_CR1_AWDCH)));
3113 }
3114 
3115 /**
3116  * @brief Set ADC analog watchdog threshold value of threshold
3117  * high or low.
3118  * @note On this STM32 serie, there is only 1 kind of analog watchdog
3119  * instance:
3120  * - AWD standard (instance AWD1):
3121  * - channels monitored: can monitor 1 channel or all channels.
3122  * - groups monitored: ADC groups regular and-or injected.
3123  * - resolution: resolution is not limited (corresponds to
3124  * ADC resolution configured).
3125  * @rmtoll HTR HT LL_ADC_SetAnalogWDThresholds\n
3126  * LTR LT LL_ADC_SetAnalogWDThresholds
3127  * @param ADCx ADC instance
3128  * @param AWDThresholdsHighLow This parameter can be one of the following values:
3129  * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3130  * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3131  * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
3132  * @retval None
3133  */
3134 __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3135 {
3136  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3137 
3138  MODIFY_REG(*preg,
3139  ADC_HTR_HT,
3140  AWDThresholdValue);
3141 }
3142 
3143 /**
3144  * @brief Get ADC analog watchdog threshold value of threshold high or
3145  * threshold low.
3146  * @note In case of ADC resolution different of 12 bits,
3147  * analog watchdog thresholds data require a specific shift.
3148  * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
3149  * @rmtoll HTR HT LL_ADC_GetAnalogWDThresholds\n
3150  * LTR LT LL_ADC_GetAnalogWDThresholds
3151  * @param ADCx ADC instance
3152  * @param AWDThresholdsHighLow This parameter can be one of the following values:
3153  * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
3154  * @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3155  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3156 */
3157 __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3158 {
3159  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3160 
3161  return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3162 }
3163 
3164 /**
3165  * @}
3166  */
3167 
3168 /** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
3169  * @{
3170  */
3171 
3172 #if defined(ADC_MULTIMODE_SUPPORT)
3173 /**
3174  * @brief Set ADC multimode configuration to operate in independent mode
3175  * or multimode (for devices with several ADC instances).
3176  * @note If multimode configuration: the selected ADC instance is
3177  * either master or slave depending on hardware.
3178  * Refer to reference manual.
3179  * @rmtoll CR1 DUALMOD LL_ADC_SetMultimode
3180  * @param ADCxy_COMMON ADC common instance
3181  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3182  * @param Multimode This parameter can be one of the following values:
3183  * @arg @ref LL_ADC_MULTI_INDEPENDENT
3184  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3185  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
3186  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
3187  * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3188  * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3189  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3190  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3191  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
3192  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
3193  * @retval None
3194  */
3195 __STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
3196 {
3197  MODIFY_REG(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD, Multimode);
3198 }
3199 
3200 /**
3201  * @brief Get ADC multimode configuration to operate in independent mode
3202  * or multimode (for devices with several ADC instances).
3203  * @note If multimode configuration: the selected ADC instance is
3204  * either master or slave depending on hardware.
3205  * Refer to reference manual.
3206  * @rmtoll CR1 DUALMOD LL_ADC_GetMultimode
3207  * @param ADCxy_COMMON ADC common instance
3208  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3209  * @retval Returned value can be one of the following values:
3210  * @arg @ref LL_ADC_MULTI_INDEPENDENT
3211  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
3212  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_FAST
3213  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL_SLOW
3214  * @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
3215  * @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
3216  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
3217  * @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
3218  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTFAST_INJ_SIM
3219  * @arg @ref LL_ADC_MULTI_DUAL_REG_INTSLOW_INJ_SIM
3220  */
3221 __STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)
3222 {
3223  return (uint32_t)(READ_BIT(ADCxy_COMMON->CR1, ADC_CR1_DUALMOD));
3224 }
3225 
3226 #endif /* ADC_MULTIMODE_SUPPORT */
3227 
3228 /**
3229  * @}
3230  */
3231 /** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
3232  * @{
3233  */
3234 
3235 /**
3236  * @brief Enable the selected ADC instance.
3237  * @note On this STM32 serie, after ADC enable, a delay for
3238  * ADC internal analog stabilization is required before performing a
3239  * ADC conversion start.
3240  * Refer to device datasheet, parameter tSTAB.
3241  * @rmtoll CR2 ADON LL_ADC_Enable
3242  * @param ADCx ADC instance
3243  * @retval None
3244  */
3245 __STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
3246 {
3247  SET_BIT(ADCx->CR2, ADC_CR2_ADON);
3248 }
3249 
3250 /**
3251  * @brief Disable the selected ADC instance.
3252  * @rmtoll CR2 ADON LL_ADC_Disable
3253  * @param ADCx ADC instance
3254  * @retval None
3255  */
3256 __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
3257 {
3258  CLEAR_BIT(ADCx->CR2, ADC_CR2_ADON);
3259 }
3260 
3261 /**
3262  * @brief Get the selected ADC instance enable state.
3263  * @rmtoll CR2 ADON LL_ADC_IsEnabled
3264  * @param ADCx ADC instance
3265  * @retval 0: ADC is disabled, 1: ADC is enabled.
3266  */
3267 __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)
3268 {
3269  return (READ_BIT(ADCx->CR2, ADC_CR2_ADON) == (ADC_CR2_ADON));
3270 }
3271 
3272 /**
3273  * @brief Start ADC calibration in the mode single-ended
3274  * or differential (for devices with differential mode available).
3275  * @note On this STM32 serie, before starting a calibration,
3276  * ADC must be disabled.
3277  * A minimum number of ADC clock cycles are required
3278  * between ADC disable state and calibration start.
3279  * Refer to literal @ref LL_ADC_DELAY_DISABLE_CALIB_ADC_CYCLES.
3280  * @note On this STM32 serie, hardware prerequisite before starting a calibration:
3281  the ADC must have been in power-on state for at least
3282  two ADC clock cycles.
3283  * @rmtoll CR2 CAL LL_ADC_StartCalibration
3284  * @param ADCx ADC instance
3285  * @retval None
3286  */
3287 __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
3288 {
3289  SET_BIT(ADCx->CR2, ADC_CR2_CAL);
3290 }
3291 
3292 /**
3293  * @brief Get ADC calibration state.
3294  * @rmtoll CR2 CAL LL_ADC_IsCalibrationOnGoing
3295  * @param ADCx ADC instance
3296  * @retval 0: calibration complete, 1: calibration in progress.
3297  */
3298 __STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)
3299 {
3300  return (READ_BIT(ADCx->CR2, ADC_CR2_CAL) == (ADC_CR2_CAL));
3301 }
3302 
3303 /**
3304  * @}
3305  */
3306 
3307 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
3308  * @{
3309  */
3310 
3311 /**
3312  * @brief Start ADC group regular conversion.
3313  * @note On this STM32 serie, this function is relevant only for
3314  * internal trigger (SW start), not for external trigger:
3315  * - If ADC trigger has been set to software start, ADC conversion
3316  * starts immediately.
3317  * - If ADC trigger has been set to external trigger, ADC conversion
3318  * start must be performed using function
3319  * @ref LL_ADC_REG_StartConversionExtTrig().
3320  * (if external trigger edge would have been set during ADC other
3321  * settings, ADC conversion would start at trigger event
3322  * as soon as ADC is enabled).
3323  * @rmtoll CR2 SWSTART LL_ADC_REG_StartConversionSWStart
3324  * @param ADCx ADC instance
3325  * @retval None
3326  */
3327 __STATIC_INLINE void LL_ADC_REG_StartConversionSWStart(ADC_TypeDef *ADCx)
3328 {
3329  SET_BIT(ADCx->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
3330 }
3331 
3332 /**
3333  * @brief Start ADC group regular conversion from external trigger.
3334  * @note ADC conversion will start at next trigger event (on the selected
3335  * trigger edge) following the ADC start conversion command.
3336  * @note On this STM32 serie, this function is relevant for
3337  * ADC conversion start from external trigger.
3338  * If internal trigger (SW start) is needed, perform ADC conversion
3339  * start using function @ref LL_ADC_REG_StartConversionSWStart().
3340  * @rmtoll CR2 EXTEN LL_ADC_REG_StartConversionExtTrig
3341  * @param ExternalTriggerEdge This parameter can be one of the following values:
3342  * @arg @ref LL_ADC_REG_TRIG_EXT_RISING
3343  * @param ADCx ADC instance
3344  * @retval None
3345  */
3346 __STATIC_INLINE void LL_ADC_REG_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3347 {
3348  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3349 }
3350 
3351 /**
3352  * @brief Stop ADC group regular conversion from external trigger.
3353  * @note No more ADC conversion will start at next trigger event
3354  * following the ADC stop conversion command.
3355  * If a conversion is on-going, it will be completed.
3356  * @note On this STM32 serie, there is no specific command
3357  * to stop a conversion on-going or to stop ADC converting
3358  * in continuous mode. These actions can be performed
3359  * using function @ref LL_ADC_Disable().
3360  * @rmtoll CR2 EXTSEL LL_ADC_REG_StopConversionExtTrig
3361  * @param ADCx ADC instance
3362  * @retval None
3363  */
3364 __STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3365 {
3366  CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG);
3367 }
3368 
3369 /**
3370  * @brief Get ADC group regular conversion data, range fit for
3371  * all ADC configurations: all ADC resolutions and
3372  * all oversampling increased data width (for devices
3373  * with feature oversampling).
3374  * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData32
3375  * @param ADCx ADC instance
3376  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3377  */
3378 __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)
3379 {
3380  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3381 }
3382 
3383 /**
3384  * @brief Get ADC group regular conversion data, range fit for
3385  * ADC resolution 12 bits.
3386  * @note For devices with feature oversampling: Oversampling
3387  * can increase data width, function for extended range
3388  * may be needed: @ref LL_ADC_REG_ReadConversionData32.
3389  * @rmtoll DR RDATA LL_ADC_REG_ReadConversionData12
3390  * @param ADCx ADC instance
3391  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3392  */
3393 __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)
3394 {
3395  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
3396 }
3397 
3398 #if defined(ADC_MULTIMODE_SUPPORT)
3399 /**
3400  * @brief Get ADC multimode conversion data of ADC master, ADC slave
3401  * or raw data with ADC master and slave concatenated.
3402  * @note If raw data with ADC master and slave concatenated is retrieved,
3403  * a macro is available to get the conversion data of
3404  * ADC master or ADC slave: see helper macro
3405  * @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
3406  * (however this macro is mainly intended for multimode
3407  * transfer by DMA, because this function can do the same
3408  * by getting multimode conversion data of ADC master or ADC slave
3409  * separately).
3410  * @rmtoll DR DATA LL_ADC_REG_ReadMultiConversionData32\n
3411  * DR ADC2DATA LL_ADC_REG_ReadMultiConversionData32
3412  * @param ADCx ADC instance
3413  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3414  * @param ConversionData This parameter can be one of the following values:
3415  * @arg @ref LL_ADC_MULTI_MASTER
3416  * @arg @ref LL_ADC_MULTI_SLAVE
3417  * @arg @ref LL_ADC_MULTI_MASTER_SLAVE
3418  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3419  */
3420 __STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_TypeDef *ADCx, uint32_t ConversionData)
3421 {
3422  return (uint32_t)(READ_BIT(ADCx->DR,
3423  ADC_DR_ADC2DATA)
3424  >> POSITION_VAL(ConversionData)
3425  );
3426 }
3427 #endif /* ADC_MULTIMODE_SUPPORT */
3428 
3429 /**
3430  * @}
3431  */
3432 
3433 /** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
3434  * @{
3435  */
3436 
3437 /**
3438  * @brief Start ADC group injected conversion.
3439  * @note On this STM32 serie, this function is relevant only for
3440  * internal trigger (SW start), not for external trigger:
3441  * - If ADC trigger has been set to software start, ADC conversion
3442  * starts immediately.
3443  * - If ADC trigger has been set to external trigger, ADC conversion
3444  * start must be performed using function
3445  * @ref LL_ADC_INJ_StartConversionExtTrig().
3446  * (if external trigger edge would have been set during ADC other
3447  * settings, ADC conversion would start at trigger event
3448  * as soon as ADC is enabled).
3449  * @rmtoll CR2 JSWSTART LL_ADC_INJ_StartConversionSWStart
3450  * @param ADCx ADC instance
3451  * @retval None
3452  */
3453 __STATIC_INLINE void LL_ADC_INJ_StartConversionSWStart(ADC_TypeDef *ADCx)
3454 {
3455  SET_BIT(ADCx->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
3456 }
3457 
3458 /**
3459  * @brief Start ADC group injected conversion from external trigger.
3460  * @note ADC conversion will start at next trigger event (on the selected
3461  * trigger edge) following the ADC start conversion command.
3462  * @note On this STM32 serie, this function is relevant for
3463  * ADC conversion start from external trigger.
3464  * If internal trigger (SW start) is needed, perform ADC conversion
3465  * start using function @ref LL_ADC_INJ_StartConversionSWStart().
3466  * @rmtoll CR2 JEXTEN LL_ADC_INJ_StartConversionExtTrig
3467  * @param ExternalTriggerEdge This parameter can be one of the following values:
3468  * @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
3469  * @param ADCx ADC instance
3470  * @retval None
3471  */
3472 __STATIC_INLINE void LL_ADC_INJ_StartConversionExtTrig(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
3473 {
3474  SET_BIT(ADCx->CR2, ExternalTriggerEdge);
3475 }
3476 
3477 /**
3478  * @brief Stop ADC group injected conversion from external trigger.
3479  * @note No more ADC conversion will start at next trigger event
3480  * following the ADC stop conversion command.
3481  * If a conversion is on-going, it will be completed.
3482  * @note On this STM32 serie, there is no specific command
3483  * to stop a conversion on-going or to stop ADC converting
3484  * in continuous mode. These actions can be performed
3485  * using function @ref LL_ADC_Disable().
3486  * @rmtoll CR2 JEXTSEL LL_ADC_INJ_StopConversionExtTrig
3487  * @param ADCx ADC instance
3488  * @retval None
3489  */
3490 __STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
3491 {
3492  CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG);
3493 }
3494 
3495 /**
3496  * @brief Get ADC group regular conversion data, range fit for
3497  * all ADC configurations: all ADC resolutions and
3498  * all oversampling increased data width (for devices
3499  * with feature oversampling).
3500  * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData32\n
3501  * JDR2 JDATA LL_ADC_INJ_ReadConversionData32\n
3502  * JDR3 JDATA LL_ADC_INJ_ReadConversionData32\n
3503  * JDR4 JDATA LL_ADC_INJ_ReadConversionData32
3504  * @param ADCx ADC instance
3505  * @param Rank This parameter can be one of the following values:
3506  * @arg @ref LL_ADC_INJ_RANK_1
3507  * @arg @ref LL_ADC_INJ_RANK_2
3508  * @arg @ref LL_ADC_INJ_RANK_3
3509  * @arg @ref LL_ADC_INJ_RANK_4
3510  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3511  */
3512 __STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
3513 {
3514  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
3515 
3516  return (uint32_t)(READ_BIT(*preg,
3517  ADC_JDR1_JDATA)
3518  );
3519 }
3520 
3521 /**
3522  * @brief Get ADC group injected conversion data, range fit for
3523  * ADC resolution 12 bits.
3524  * @note For devices with feature oversampling: Oversampling
3525  * can increase data width, function for extended range
3526  * may be needed: @ref LL_ADC_INJ_ReadConversionData32.
3527  * @rmtoll JDR1 JDATA LL_ADC_INJ_ReadConversionData12\n
3528  * JDR2 JDATA LL_ADC_INJ_ReadConversionData12\n
3529  * JDR3 JDATA LL_ADC_INJ_ReadConversionData12\n
3530  * JDR4 JDATA LL_ADC_INJ_ReadConversionData12
3531  * @param ADCx ADC instance
3532  * @param Rank This parameter can be one of the following values:
3533  * @arg @ref LL_ADC_INJ_RANK_1
3534  * @arg @ref LL_ADC_INJ_RANK_2
3535  * @arg @ref LL_ADC_INJ_RANK_3
3536  * @arg @ref LL_ADC_INJ_RANK_4
3537  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3538  */
3539 __STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
3540 {
3541  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
3542 
3543  return (uint16_t)(READ_BIT(*preg,
3544  ADC_JDR1_JDATA)
3545  );
3546 }
3547 
3548 /**
3549  * @}
3550  */
3551 
3552 /** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
3553  * @{
3554  */
3555 
3556 /**
3557  * @brief Get flag ADC group regular end of sequence conversions.
3558  * @rmtoll SR EOC LL_ADC_IsActiveFlag_EOS
3559  * @param ADCx ADC instance
3560  * @retval State of bit (1 or 0).
3561  */
3562 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)
3563 {
3564  /* Note: on this STM32 serie, there is no flag ADC group regular */
3565  /* end of unitary conversion. */
3566  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3567  /* in other STM32 families). */
3568  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS));
3569 }
3570 
3571 
3572 /**
3573  * @brief Get flag ADC group injected end of sequence conversions.
3574  * @rmtoll SR JEOC LL_ADC_IsActiveFlag_JEOS
3575  * @param ADCx ADC instance
3576  * @retval State of bit (1 or 0).
3577  */
3578 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)
3579 {
3580  /* Note: on this STM32 serie, there is no flag ADC group injected */
3581  /* end of unitary conversion. */
3582  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3583  /* in other STM32 families). */
3584  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS));
3585 }
3586 
3587 /**
3588  * @brief Get flag ADC analog watchdog 1 flag
3589  * @rmtoll SR AWD LL_ADC_IsActiveFlag_AWD1
3590  * @param ADCx ADC instance
3591  * @retval State of bit (1 or 0).
3592  */
3593 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)
3594 {
3595  return (READ_BIT(ADCx->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3596 }
3597 
3598 /**
3599  * @brief Clear flag ADC group regular end of sequence conversions.
3600  * @rmtoll SR EOC LL_ADC_ClearFlag_EOS
3601  * @param ADCx ADC instance
3602  * @retval None
3603  */
3604 __STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
3605 {
3606  /* Note: on this STM32 serie, there is no flag ADC group regular */
3607  /* end of unitary conversion. */
3608  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3609  /* in other STM32 families). */
3610  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_EOS);
3611 }
3612 
3613 
3614 /**
3615  * @brief Clear flag ADC group injected end of sequence conversions.
3616  * @rmtoll SR JEOC LL_ADC_ClearFlag_JEOS
3617  * @param ADCx ADC instance
3618  * @retval None
3619  */
3620 __STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
3621 {
3622  /* Note: on this STM32 serie, there is no flag ADC group injected */
3623  /* end of unitary conversion. */
3624  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3625  /* in other STM32 families). */
3626  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_JEOS);
3627 }
3628 
3629 /**
3630  * @brief Clear flag ADC analog watchdog 1.
3631  * @rmtoll SR AWD LL_ADC_ClearFlag_AWD1
3632  * @param ADCx ADC instance
3633  * @retval None
3634  */
3635 __STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
3636 {
3637  WRITE_REG(ADCx->SR, ~LL_ADC_FLAG_AWD1);
3638 }
3639 
3640 #if defined(ADC_MULTIMODE_SUPPORT)
3641 /**
3642  * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC master.
3643  * @rmtoll SR EOC LL_ADC_IsActiveFlag_MST_EOS
3644  * @param ADCxy_COMMON ADC common instance
3645  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3646  * @retval State of bit (1 or 0).
3647  */
3648 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
3649 {
3650  /* Note: on this STM32 serie, there is no flag ADC group regular */
3651  /* end of unitary conversion. */
3652  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3653  /* in other STM32 families). */
3654  return (READ_BIT(ADCxy_COMMON->SR, ADC_SR_EOC) == (ADC_SR_EOC));
3655 }
3656 
3657 /**
3658  * @brief Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
3659  * @rmtoll SR EOC LL_ADC_IsActiveFlag_SLV_EOS
3660  * @param ADCxy_COMMON ADC common instance
3661  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3662  * @retval State of bit (1 or 0).
3663  */
3664 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)
3665 {
3666  /* Note: on this STM32 serie, there is no flag ADC group regular */
3667  /* end of unitary conversion. */
3668  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3669  /* in other STM32 families). */
3670 
3671  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3672 
3673  return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
3674 }
3675 
3676 
3677 /**
3678  * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC master.
3679  * @rmtoll SR JEOC LL_ADC_IsActiveFlag_MST_JEOS
3680  * @param ADCxy_COMMON ADC common instance
3681  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3682  * @retval State of bit (1 or 0).
3683  */
3684 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
3685 {
3686  /* Note: on this STM32 serie, there is no flag ADC group injected */
3687  /* end of unitary conversion. */
3688  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3689  /* in other STM32 families). */
3690  return (READ_BIT(ADC1->SR, ADC_SR_JEOC) == (ADC_SR_JEOC));
3691 }
3692 
3693 /**
3694  * @brief Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
3695  * @rmtoll SR JEOC LL_ADC_IsActiveFlag_SLV_JEOS
3696  * @param ADCxy_COMMON ADC common instance
3697  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3698  * @retval State of bit (1 or 0).
3699  */
3700 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)
3701 {
3702  /* Note: on this STM32 serie, there is no flag ADC group injected */
3703  /* end of unitary conversion. */
3704  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3705  /* in other STM32 families). */
3706 
3707  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3708 
3709  return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
3710 }
3711 
3712 /**
3713  * @brief Get flag multimode ADC analog watchdog 1 of the ADC master.
3714  * @rmtoll SR AWD LL_ADC_IsActiveFlag_MST_AWD1
3715  * @param ADCxy_COMMON ADC common instance
3716  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3717  * @retval State of bit (1 or 0).
3718  */
3719 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
3720 {
3721  return (READ_BIT(ADC1->SR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3722 }
3723 
3724 /**
3725  * @brief Get flag multimode analog watchdog 1 of the ADC slave.
3726  * @rmtoll SR AWD LL_ADC_IsActiveFlag_SLV_AWD1
3727  * @param ADCxy_COMMON ADC common instance
3728  * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3729  * @retval State of bit (1 or 0).
3730  */
3731 __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
3732 {
3733  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3734 
3735  return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3736 }
3737 
3738 #endif /* ADC_MULTIMODE_SUPPORT */
3739 
3740 /**
3741  * @}
3742  */
3743 
3744 /** @defgroup ADC_LL_EF_IT_Management ADC IT management
3745  * @{
3746  */
3747 
3748 /**
3749  * @brief Enable interruption ADC group regular end of sequence conversions.
3750  * @rmtoll CR1 EOCIE LL_ADC_EnableIT_EOS
3751  * @param ADCx ADC instance
3752  * @retval None
3753  */
3754 __STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
3755 {
3756  /* Note: on this STM32 serie, there is no flag ADC group regular */
3757  /* end of unitary conversion. */
3758  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3759  /* in other STM32 families). */
3760  SET_BIT(ADCx->CR1, ADC_CR1_EOCIE);
3761 }
3762 
3763 
3764 /**
3765  * @brief Enable interruption ADC group injected end of sequence conversions.
3766  * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
3767  * @param ADCx ADC instance
3768  * @retval None
3769  */
3770 __STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
3771 {
3772  /* Note: on this STM32 serie, there is no flag ADC group injected */
3773  /* end of unitary conversion. */
3774  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3775  /* in other STM32 families). */
3776  SET_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
3777 }
3778 
3779 /**
3780  * @brief Enable interruption ADC analog watchdog 1.
3781  * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
3782  * @param ADCx ADC instance
3783  * @retval None
3784  */
3785 __STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
3786 {
3787  SET_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
3788 }
3789 
3790 /**
3791  * @brief Disable interruption ADC group regular end of sequence conversions.
3792  * @rmtoll CR1 EOCIE LL_ADC_DisableIT_EOS
3793  * @param ADCx ADC instance
3794  * @retval None
3795  */
3796 __STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
3797 {
3798  /* Note: on this STM32 serie, there is no flag ADC group regular */
3799  /* end of unitary conversion. */
3800  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3801  /* in other STM32 families). */
3802  CLEAR_BIT(ADCx->CR1, ADC_CR1_EOCIE);
3803 }
3804 
3805 
3806 /**
3807  * @brief Disable interruption ADC group injected end of sequence conversions.
3808  * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
3809  * @param ADCx ADC instance
3810  * @retval None
3811  */
3812 __STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
3813 {
3814  /* Note: on this STM32 serie, there is no flag ADC group injected */
3815  /* end of unitary conversion. */
3816  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3817  /* in other STM32 families). */
3818  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_JEOS);
3819 }
3820 
3821 /**
3822  * @brief Disable interruption ADC analog watchdog 1.
3823  * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
3824  * @param ADCx ADC instance
3825  * @retval None
3826  */
3827 __STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
3828 {
3829  CLEAR_BIT(ADCx->CR1, LL_ADC_IT_AWD1);
3830 }
3831 
3832 /**
3833  * @brief Get state of interruption ADC group regular end of sequence conversions
3834  * (0: interrupt disabled, 1: interrupt enabled).
3835  * @rmtoll CR1 EOCIE LL_ADC_IsEnabledIT_EOS
3836  * @param ADCx ADC instance
3837  * @retval State of bit (1 or 0).
3838  */
3839 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)
3840 {
3841  /* Note: on this STM32 serie, there is no flag ADC group regular */
3842  /* end of unitary conversion. */
3843  /* Flag noted as "EOC" is corresponding to flag "EOS" */
3844  /* in other STM32 families). */
3845  return (READ_BIT(ADCx->CR1, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS));
3846 }
3847 
3848 
3849 /**
3850  * @brief Get state of interruption ADC group injected end of sequence conversions
3851  * (0: interrupt disabled, 1: interrupt enabled).
3852  * @rmtoll CR1 JEOCIE LL_ADC_EnableIT_JEOS
3853  * @param ADCx ADC instance
3854  * @retval State of bit (1 or 0).
3855  */
3856 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)
3857 {
3858  /* Note: on this STM32 serie, there is no flag ADC group injected */
3859  /* end of unitary conversion. */
3860  /* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3861  /* in other STM32 families). */
3862  return (READ_BIT(ADCx->CR1, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS));
3863 }
3864 
3865 /**
3866  * @brief Get state of interruption ADC analog watchdog 1
3867  * (0: interrupt disabled, 1: interrupt enabled).
3868  * @rmtoll CR1 AWDIE LL_ADC_EnableIT_AWD1
3869  * @param ADCx ADC instance
3870  * @retval State of bit (1 or 0).
3871  */
3872 __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)
3873 {
3874  return (READ_BIT(ADCx->CR1, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1));
3875 }
3876 
3877 /**
3878  * @}
3879  */
3880 
3881 #if defined(USE_FULL_LL_DRIVER)
3882 /** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
3883  * @{
3884  */
3885 
3886 /* Initialization of some features of ADC common parameters and multimode */
3887 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);
3888 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
3889 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
3890 
3891 /* De-initialization of ADC instance, ADC group regular and ADC group injected */
3892 /* (availability of ADC group injected depends on STM32 families) */
3893 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
3894 
3895 /* Initialization of some features of ADC instance */
3896 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);
3897 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
3898 
3899 /* Initialization of some features of ADC instance and ADC group regular */
3900 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
3901 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
3902 
3903 /* Initialization of some features of ADC instance and ADC group injected */
3904 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
3905 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);
3906 
3907 /**
3908  * @}
3909  */
3910 #endif /* USE_FULL_LL_DRIVER */
3911 
3912 /**
3913  * @}
3914  */
3915 
3916 /**
3917  * @}
3918  */
3919 
3920 #endif /* ADC1 || ADC2 || ADC3 */
3921 
3922 /**
3923  * @}
3924  */
3925 
3926 #ifdef __cplusplus
3927 }
3928 #endif
3929 
3930 #endif /* __STM32F1xx_LL_ADC_H */
3931 
3932 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
ADC_CR1_AWDSGL
#define ADC_CR1_AWDSGL
Definition: stm32f103xb.h:3326
ADC_TypeDef::JSQR
__IO uint32_t JSQR
Definition: stm32f103xb.h:160
ADC_TypeDef::SMPR1
__IO uint32_t SMPR1
Definition: stm32f103xb.h:149
ADC_DR_DATA
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Definition: stm32f103xb.h:3793
ADC_HTR_HT
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Definition: stm32f103xb.h:3565
ADC_TypeDef::JDR1
__IO uint32_t JDR1
Definition: stm32f103xb.h:161
ADC_TypeDef::SQR1
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Definition: stm32f103xb.h:157
ADC_CR2_CAL
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Definition: stm32f103xb.h:3372
ADC_TypeDef::HTR
__IO uint32_t HTR
Definition: stm32f103xb.h:155
ADC_CR2_SWSTART
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Definition: stm32f103xb.h:3409
READ_BIT
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Definition: stm32f1xx.h:182
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Definition: stm32f103xb.h:3305
ADC_CR1_JDISCEN
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Definition: stm32f103xb.h:3335
POSITION_VAL
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Definition: stm32f1xx.h:192
ADC_CR1_EOCIE
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Definition: stm32f103xb.h:3360
ADC_Common_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:172
ADC_Common_TypeDef::CR1
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Definition: stm32f103xb.h:171
ADC_TypeDef::JOFR1
__IO uint32_t JOFR1
Definition: stm32f103xb.h:151
ADC_CR1_AWDEN
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Definition: stm32f103xb.h:3357
ADC_JSQR_JL_Pos
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Definition: stm32f103xb.h:3764
ADC_SR_EOC
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Definition: stm32f103xb.h:3299
ADC_CR1_DISCEN
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Definition: stm32f103xb.h:3332
ADC_CR2_DMA
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Definition: stm32f103xb.h:3378
ADC1
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Definition: stm32f103xb.h:670
ADC_CR2_ADON
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Definition: stm32f103xb.h:3366
ADC_CR1_DISCNUM
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Definition: stm32f103xb.h:3339
ADC_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32f103xb.h:148
ADC_TypeDef::DR
__IO uint32_t DR
Definition: stm32f103xb.h:165
MODIFY_REG
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Definition: stm32f1xx.h:190
ADC_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:146
ADC_SMPR2_SMP0
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ADC_SQR1_L
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ADC_JOFR1_JOFFSET1
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Definition: stm32f103xb.h:3545
ADC_TypeDef
Analog to Digital Converter
Definition: stm32f103xb.h:144
__STATIC_INLINE
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Definition: cmsis_armcc.h:59
ADC_CR2_EXTSEL
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Definition: stm32f103xb.h:3396
ADC_JSQR_JL
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Definition: stm32f103xb.h:3766
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Definition: stm32f103xb.h:3354
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Definition: stm32f1xx.h:186
stm32f1xx.h
CMSIS STM32F1xx Device Peripheral Access Layer Header File.
__IO
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Definition: core_armv8mbl.h:196
ADC_DR_ADC2DATA
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Definition: stm32f103xb.h:3796
ADC_Common_TypeDef
Definition: stm32f103xb.h:168
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ADC_JDR1_JDATA
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__IO uint32_t CR1
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Definition: stm32f103xb.h:3323
ADC_CR1_JAUTO
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Definition: stm32f103xb.h:3329
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Definition: stm32f1xx.h:178
ADC_Common_TypeDef::SR
__IO uint32_t SR
Definition: stm32f103xb.h:170
ADC_CR2_JSWSTART
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Definition: stm32f103xb.h:3406
ADC_CR2_JEXTTRIG
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Definition: stm32f103xb.h:3392
CLEAR_BIT
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Definition: stm32f1xx.h:180
ADC_CR2_CONT
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Definition: stm32f103xb.h:3369
ADC_CR2_TSVREFE
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Definition: stm32f103xb.h:3412
ErrorStatus
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Definition: stm32f1xx.h:164
ADC_CR2_EXTTRIG
#define ADC_CR2_EXTTRIG
Definition: stm32f103xb.h:3403
ADC_CR2_ALIGN
#define ADC_CR2_ALIGN
Definition: stm32f103xb.h:3381
ADC_CR1_DUALMOD
#define ADC_CR1_DUALMOD
Definition: stm32f103xb.h:3346
ADC12_COMMON
#define ADC12_COMMON
Definition: stm32f103xb.h:672