mpu_armv8.h File Reference

Go to the source code of this file.

Data Structures
struct	ARM_MPU_Region_t

Macros
#define	ARM_MPU_ARMV8_H
#define	ARM_MPU_ATTR_DEVICE   ( 0U )
	Attribute for device memory (outer only) More...
#define	ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )
	Attribute for non-cacheable, normal memory. More...
#define	ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)   (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
	Attribute for normal memory (outer and inner) More...
#define	ARM_MPU_ATTR_DEVICE_nGnRnE   (0U)
	Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_nGnRE   (1U)
	Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_nGRE   (2U)
	Device memory type non Gathering, Re-ordering, Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR_DEVICE_GRE   (3U)
	Device memory type Gathering, Re-ordering, Early Write Acknowledgement. More...
#define	ARM_MPU_ATTR(O, I)   (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
	Memory Attribute. More...
#define	ARM_MPU_SH_NON   (0U)
	Normal memory non-shareable More...
#define	ARM_MPU_SH_OUTER   (2U)
	Normal memory outer shareable More...
#define	ARM_MPU_SH_INNER   (3U)
	Normal memory inner shareable More...
#define	ARM_MPU_AP_(RO, NP)   (((RO & 1U) << 1U) | (NP & 1U))
	Memory access permissions. More...
#define	ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
	Region Base Address Register value. More...
#define	ARM_MPU_RLAR(LIMIT, IDX)
	Region Limit Address Register value. More...

Functions
__STATIC_INLINE void	ARM_MPU_Enable (uint32_t MPU_Control)
__STATIC_INLINE void	ARM_MPU_Disable (void)
__STATIC_INLINE void	ARM_MPU_SetMemAttrEx (MPU_Type *mpu, uint8_t idx, uint8_t attr)
__STATIC_INLINE void	ARM_MPU_SetMemAttr (uint8_t idx, uint8_t attr)
__STATIC_INLINE void	ARM_MPU_ClrRegionEx (MPU_Type *mpu, uint32_t rnr)
__STATIC_INLINE void	ARM_MPU_ClrRegion (uint32_t rnr)
__STATIC_INLINE void	ARM_MPU_SetRegionEx (MPU_Type *mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void	ARM_MPU_SetRegion (uint32_t rnr, uint32_t rbar, uint32_t rlar)
__STATIC_INLINE void	orderedCpy (volatile uint32_t *dst, const uint32_t *__RESTRICT src, uint32_t len)
__STATIC_INLINE void	ARM_MPU_LoadEx (MPU_Type *mpu, uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)
__STATIC_INLINE void	ARM_MPU_Load (uint32_t rnr, ARM_MPU_Region_t const *table, uint32_t cnt)

Macro Definition Documentation

ARM_MPU_AP_

#define ARM_MPU_AP_	(		RO,
			NP
	)		(((RO & 1U) << 1U) | (NP & 1U))

Memory access permissions.

Parameters

RO	Read-Only: Set to 1 for read-only memory.
NP	Non-Privileged: Set to 1 for non-privileged memory.

Definition at line 80 of file mpu_armv8.h.

ARM_MPU_ARMV8_H

#define ARM_MPU_ARMV8_H

Definition at line 32 of file mpu_armv8.h.

ARM_MPU_ATTR

#define ARM_MPU_ATTR	(		O,
			I
	)		(((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))

Memory Attribute.

Parameters

O	Outer memory attributes
I	O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes

Definition at line 65 of file mpu_armv8.h.

ARM_MPU_ATTR_DEVICE

#define ARM_MPU_ATTR_DEVICE   ( 0U )

Attribute for device memory (outer only)

Definition at line 35 of file mpu_armv8.h.

ARM_MPU_ATTR_DEVICE_GRE

#define ARM_MPU_ATTR_DEVICE_GRE   (3U)

Device memory type Gathering, Re-ordering, Early Write Acknowledgement.

Definition at line 59 of file mpu_armv8.h.

ARM_MPU_ATTR_DEVICE_nGnRE

#define ARM_MPU_ATTR_DEVICE_nGnRE   (1U)

Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement.

Definition at line 53 of file mpu_armv8.h.

ARM_MPU_ATTR_DEVICE_nGnRnE

#define ARM_MPU_ATTR_DEVICE_nGnRnE   (0U)

Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement.

Definition at line 50 of file mpu_armv8.h.

ARM_MPU_ATTR_DEVICE_nGRE

#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)

Device memory type non Gathering, Re-ordering, Early Write Acknowledgement.

Definition at line 56 of file mpu_armv8.h.

ARM_MPU_ATTR_MEMORY_

#define ARM_MPU_ATTR_MEMORY_	(		NT,
			WB,
			RA,
			WA
	)		(((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))

Attribute for normal memory (outer and inner)

Parameters

NT	Non-Transient: Set to 1 for non-transient data.
WB	Write-Back: Set to 1 to use write-back update policy.
RA	Read Allocation: Set to 1 to use cache allocation on read miss.
WA	Write Allocation: Set to 1 to use cache allocation on write miss.

Definition at line 46 of file mpu_armv8.h.

ARM_MPU_ATTR_NON_CACHEABLE

#define ARM_MPU_ATTR_NON_CACHEABLE   ( 4U )

Attribute for non-cacheable, normal memory.

Definition at line 38 of file mpu_armv8.h.

ARM_MPU_RBAR

#define ARM_MPU_RBAR	(		BASE,
			SH,
			RO,
			NP,
			XN
	)

Value:

  ((BASE & MPU_RBAR_BASE_Msk) | \
  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))

Region Base Address Register value.

Parameters

BASE	The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
SH	Defines the Shareability domain for this memory region.
RO	Read-Only: Set to 1 for a read-only memory region.
NP	Non-Privileged: Set to 1 for a non-privileged memory region. \oaram XN eXecute Never: Set to 1 for a non-executable memory region.

Definition at line 89 of file mpu_armv8.h.

ARM_MPU_RLAR

#define ARM_MPU_RLAR	(		LIMIT,
			IDX
	)

Value:

  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
  (MPU_RLAR_EN_Msk))

Region Limit Address Register value.

Parameters

LIMIT	The limit address bits [31:5] for this memory region. The value is one extended.
IDX	The attribute index to be associated with this memory region.

Definition at line 99 of file mpu_armv8.h.

ARM_MPU_SH_INNER

#define ARM_MPU_SH_INNER   (3U)

Normal memory inner shareable

Definition at line 74 of file mpu_armv8.h.

ARM_MPU_SH_NON

#define ARM_MPU_SH_NON   (0U)

Normal memory non-shareable

Definition at line 68 of file mpu_armv8.h.

ARM_MPU_SH_OUTER

#define ARM_MPU_SH_OUTER   (2U)

Normal memory outer shareable

Definition at line 71 of file mpu_armv8.h.

Function Documentation

ARM_MPU_ClrRegion()

__STATIC_INLINE void ARM_MPU_ClrRegion

(

uint32_t

rnr

)

Clear and disable the given MPU region.

Parameters

rnr	Region number to be cleared.

Definition at line 215 of file mpu_armv8.h.

{
  ARM_MPU_ClrRegionEx(MPU, rnr);
}

ARM_MPU_ClrRegionEx()

__STATIC_INLINE void ARM_MPU_ClrRegionEx	(	MPU_Type *	mpu,
		uint32_t	rnr
	)

Clear and disable the given MPU region of the given MPU.

Parameters

mpu	Pointer to MPU to be used.
rnr	Region number to be cleared.

Definition at line 206 of file mpu_armv8.h.

{
  mpu->RNR = rnr;
  mpu->RLAR = 0U;
}

ARM_MPU_Disable()

__STATIC_INLINE void ARM_MPU_Disable

(

void

)

Disable the MPU.

Definition at line 127 of file mpu_armv8.h.

{
  __DSB();
  __ISB();
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
#endif
  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
}

ARM_MPU_Enable()

__STATIC_INLINE void ARM_MPU_Enable

(

uint32_t

MPU_Control

)

Enable the MPU.

Parameters

MPU_Control

Default access permissions for unconfigured regions.

Definition at line 115 of file mpu_armv8.h.

{
  __DSB();
  __ISB();
  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
#endif
}

ARM_MPU_Load()

__STATIC_INLINE void ARM_MPU_Load	(	uint32_t	rnr,
		ARM_MPU_Region_t const *	table,
		uint32_t	cnt
	)

Load the given number of MPU regions from a table.

Parameters

rnr	First region number to be configured.
table	Pointer to the MPU configuration table.
cnt	Amount of regions to be configured.

Definition at line 315 of file mpu_armv8.h.

{
  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
}

ARM_MPU_LoadEx()

__STATIC_INLINE void ARM_MPU_LoadEx	(	MPU_Type *	mpu,
		uint32_t	rnr,
		ARM_MPU_Region_t const *	table,
		uint32_t	cnt
	)

Load the given number of MPU regions from a table to the given MPU.

Parameters

mpu	Pointer to the MPU registers to be used.
rnr	First region number to be configured.
table	Pointer to the MPU configuration table.
cnt	Amount of regions to be configured.

Definition at line 285 of file mpu_armv8.h.

{
  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
  if (cnt == 1U) {
    mpu->RNR = rnr;
    orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
  } else {
    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
    
    mpu->RNR = rnrBase;
    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
      orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
      table += c;
      cnt -= c;
      rnrOffset = 0U;
      rnrBase += MPU_TYPE_RALIASES;
      mpu->RNR = rnrBase;
    }
    
    orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
  }
}

ARM_MPU_SetMemAttr()

__STATIC_INLINE void ARM_MPU_SetMemAttr	(	uint8_t	idx,
		uint8_t	attr
	)

Set the memory attribute encoding.

Parameters

idx	The attribute index to be set [0-7]
attr	The attribute value to be set.

Definition at line 186 of file mpu_armv8.h.

{
  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
}

ARM_MPU_SetMemAttrEx()

__STATIC_INLINE void ARM_MPU_SetMemAttrEx	(	MPU_Type *	mpu,
		uint8_t	idx,
		uint8_t	attr
	)

Set the memory attribute encoding to the given MPU.

Parameters

mpu	Pointer to the MPU to be configured.
idx	The attribute index to be set [0-7]
attr	The attribute value to be set.

Definition at line 169 of file mpu_armv8.h.

{
  const uint8_t reg = idx / 4U;
  const uint32_t pos = ((idx % 4U) * 8U);
  const uint32_t mask = 0xFFU << pos;
  
  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
    return; // invalid index
  }
  
  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
}

ARM_MPU_SetRegion()

__STATIC_INLINE void ARM_MPU_SetRegion	(	uint32_t	rnr,
		uint32_t	rbar,
		uint32_t	rlar
	)

Configure the given MPU region.

Parameters

rnr	Region number to be configured.
rbar	Value for RBAR register.
rlar	Value for RLAR register.

Definition at line 248 of file mpu_armv8.h.

{
  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
}

ARM_MPU_SetRegionEx()

__STATIC_INLINE void ARM_MPU_SetRegionEx	(	MPU_Type *	mpu,
		uint32_t	rnr,
		uint32_t	rbar,
		uint32_t	rlar
	)

Configure the given MPU region of the given MPU.

Parameters

mpu	Pointer to MPU to be used.
rnr	Region number to be configured.
rbar	Value for RBAR register.
rlar	Value for RLAR register.

Definition at line 236 of file mpu_armv8.h.

{
  mpu->RNR = rnr;
  mpu->RBAR = rbar;
  mpu->RLAR = rlar;
}

orderedCpy()

__STATIC_INLINE void orderedCpy	(	volatile uint32_t *	dst,
		const uint32_t *__RESTRICT	src,
		uint32_t	len
	)

Memcopy with strictly ordered memory access, e.g. for register targets.

Parameters

dst	Destination data is copied to.
src	Source data is copied from.
len	Amount of data words to be copied.

Definition at line 270 of file mpu_armv8.h.

{
  uint32_t i;
  for (i = 0U; i < len; ++i) 
  {
    dst[i] = src[i];
  }
}