DIY Logging Volt/Ampmeter
Macros
HAL ETH Aliased Defines maintained for legacy purpose

Macros

#define VLAN_TAG   ETH_VLAN_TAG
 
#define MIN_ETH_PAYLOAD   ETH_MIN_ETH_PAYLOAD
 
#define MAX_ETH_PAYLOAD   ETH_MAX_ETH_PAYLOAD
 
#define JUMBO_FRAME_PAYLOAD   ETH_JUMBO_FRAME_PAYLOAD
 
#define MACMIIAR_CR_MASK   ETH_MACMIIAR_CR_MASK
 
#define MACCR_CLEAR_MASK   ETH_MACCR_CLEAR_MASK
 
#define MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK
 
#define DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK
 
#define ETH_MMCCR   0x00000100U
 
#define ETH_MMCRIR   0x00000104U
 
#define ETH_MMCTIR   0x00000108U
 
#define ETH_MMCRIMR   0x0000010CU
 
#define ETH_MMCTIMR   0x00000110U
 
#define ETH_MMCTGFSCCR   0x0000014CU
 
#define ETH_MMCTGFMSCCR   0x00000150U
 
#define ETH_MMCTGFCR   0x00000168U
 
#define ETH_MMCRFCECR   0x00000194U
 
#define ETH_MMCRFAECR   0x00000198U
 
#define ETH_MMCRGUFCR   0x000001C4U
 
#define ETH_MAC_TXFIFO_FULL   0x02000000U /* Tx FIFO full */
 
#define ETH_MAC_TXFIFONOT_EMPTY   0x01000000U /* Tx FIFO not empty */
 
#define ETH_MAC_TXFIFO_WRITE_ACTIVE   0x00400000U /* Tx FIFO write active */
 
#define ETH_MAC_TXFIFO_IDLE   0x00000000U /* Tx FIFO read status: Idle */
 
#define ETH_MAC_TXFIFO_READ   0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
 
#define ETH_MAC_TXFIFO_WAITING   0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
 
#define ETH_MAC_TXFIFO_WRITING   0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
 
#define ETH_MAC_TRANSMISSION_PAUSE   0x00080000U /* MAC transmitter in pause */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE   0x00000000U /* MAC transmit frame controller: Idle */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING   0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING   0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
 
#define ETH_MAC_MII_TRANSMIT_ACTIVE   0x00010000U /* MAC MII transmit engine active */
 
#define ETH_MAC_RXFIFO_EMPTY   0x00000000U /* Rx FIFO fill level: empty */
 
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
 
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
 
#define ETH_MAC_RXFIFO_FULL   0x00000300U /* Rx FIFO fill level: full */
 
#define ETH_MAC_READCONTROLLER_IDLE   0x00000000U /* Rx FIFO read controller IDLE state */
 
#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U /* Rx FIFO read controller Reading frame data */
 
#define ETH_MAC_READCONTROLLER_READING_STATUS   0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
 
#define ETH_MAC_READCONTROLLER_FLUSHING   0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
 
#define ETH_MAC_RXFIFO_WRITE_ACTIVE   0x00000010U /* Rx FIFO write controller active */
 
#define ETH_MAC_SMALL_FIFO_NOTACTIVE   0x00000000U /* MAC small FIFO read / write controllers not active */
 
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE   0x00000002U /* MAC small FIFO read controller active */
 
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE   0x00000004U /* MAC small FIFO write controller active */
 
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE   0x00000006U /* MAC small FIFO read / write controllers active */
 
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U /* MAC MII receive protocol engine active */
 

Detailed Description

Macro Definition Documentation

◆ DMAOMR_CLEAR_MASK

#define DMAOMR_CLEAR_MASK   ETH_DMAOMR_CLEAR_MASK

Definition at line 1327 of file stm32_hal_legacy.h.

◆ ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE

#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U /* MAC MII receive protocol engine active */

Definition at line 1370 of file stm32_hal_legacy.h.

◆ ETH_MAC_MII_TRANSMIT_ACTIVE

#define ETH_MAC_MII_TRANSMIT_ACTIVE   0x00010000U /* MAC MII transmit engine active */

Definition at line 1353 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_FLUSHING

#define ETH_MAC_READCONTROLLER_FLUSHING   0x00000060U /* Rx FIFO read controller Flushing the frame data and status */

Definition at line 1364 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_IDLE

#define ETH_MAC_READCONTROLLER_IDLE   0x00000000U /* Rx FIFO read controller IDLE state */

Definition at line 1360 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_READING_DATA

#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U /* Rx FIFO read controller Reading frame data */

Definition at line 1361 of file stm32_hal_legacy.h.

◆ ETH_MAC_READCONTROLLER_READING_STATUS

#define ETH_MAC_READCONTROLLER_READING_STATUS   0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */

Definition at line 1362 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_ABOVE_THRESHOLD

#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD   0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */

Definition at line 1356 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_BELOW_THRESHOLD

#define ETH_MAC_RXFIFO_BELOW_THRESHOLD   0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */

Definition at line 1355 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_EMPTY

#define ETH_MAC_RXFIFO_EMPTY   0x00000000U /* Rx FIFO fill level: empty */

Definition at line 1354 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_FULL

#define ETH_MAC_RXFIFO_FULL   0x00000300U /* Rx FIFO fill level: full */

Definition at line 1357 of file stm32_hal_legacy.h.

◆ ETH_MAC_RXFIFO_WRITE_ACTIVE

#define ETH_MAC_RXFIFO_WRITE_ACTIVE   0x00000010U /* Rx FIFO write controller active */

Definition at line 1365 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_NOTACTIVE

#define ETH_MAC_SMALL_FIFO_NOTACTIVE   0x00000000U /* MAC small FIFO read / write controllers not active */

Definition at line 1366 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_READ_ACTIVE

#define ETH_MAC_SMALL_FIFO_READ_ACTIVE   0x00000002U /* MAC small FIFO read controller active */

Definition at line 1367 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_RW_ACTIVE

#define ETH_MAC_SMALL_FIFO_RW_ACTIVE   0x00000006U /* MAC small FIFO read / write controllers active */

Definition at line 1369 of file stm32_hal_legacy.h.

◆ ETH_MAC_SMALL_FIFO_WRITE_ACTIVE

#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE   0x00000004U /* MAC small FIFO write controller active */

Definition at line 1368 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMISSION_PAUSE

#define ETH_MAC_TRANSMISSION_PAUSE   0x00080000U /* MAC transmitter in pause */

Definition at line 1348 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF

#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */

Definition at line 1351 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE

#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE   0x00000000U /* MAC transmit frame controller: Idle */

Definition at line 1349 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING

#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING   0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */

Definition at line 1352 of file stm32_hal_legacy.h.

◆ ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING

#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING   0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */

Definition at line 1350 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_FULL

#define ETH_MAC_TXFIFO_FULL   0x02000000U /* Tx FIFO full */

Definition at line 1341 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_IDLE

#define ETH_MAC_TXFIFO_IDLE   0x00000000U /* Tx FIFO read status: Idle */

Definition at line 1344 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_READ

#define ETH_MAC_TXFIFO_READ   0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */

Definition at line 1345 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WAITING

#define ETH_MAC_TXFIFO_WAITING   0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */

Definition at line 1346 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WRITE_ACTIVE

#define ETH_MAC_TXFIFO_WRITE_ACTIVE   0x00400000U /* Tx FIFO write active */

Definition at line 1343 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFO_WRITING

#define ETH_MAC_TXFIFO_WRITING   0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */

Definition at line 1347 of file stm32_hal_legacy.h.

◆ ETH_MAC_TXFIFONOT_EMPTY

#define ETH_MAC_TXFIFONOT_EMPTY   0x01000000U /* Tx FIFO not empty */

Definition at line 1342 of file stm32_hal_legacy.h.

◆ ETH_MMCCR

#define ETH_MMCCR   0x00000100U

Definition at line 1329 of file stm32_hal_legacy.h.

◆ ETH_MMCRFAECR

#define ETH_MMCRFAECR   0x00000198U

Definition at line 1338 of file stm32_hal_legacy.h.

◆ ETH_MMCRFCECR

#define ETH_MMCRFCECR   0x00000194U

Definition at line 1337 of file stm32_hal_legacy.h.

◆ ETH_MMCRGUFCR

#define ETH_MMCRGUFCR   0x000001C4U

Definition at line 1339 of file stm32_hal_legacy.h.

◆ ETH_MMCRIMR

#define ETH_MMCRIMR   0x0000010CU

Definition at line 1332 of file stm32_hal_legacy.h.

◆ ETH_MMCRIR

#define ETH_MMCRIR   0x00000104U

Definition at line 1330 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFCR

#define ETH_MMCTGFCR   0x00000168U

Definition at line 1336 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFMSCCR

#define ETH_MMCTGFMSCCR   0x00000150U

Definition at line 1335 of file stm32_hal_legacy.h.

◆ ETH_MMCTGFSCCR

#define ETH_MMCTGFSCCR   0x0000014CU

Definition at line 1334 of file stm32_hal_legacy.h.

◆ ETH_MMCTIMR

#define ETH_MMCTIMR   0x00000110U

Definition at line 1333 of file stm32_hal_legacy.h.

◆ ETH_MMCTIR

#define ETH_MMCTIR   0x00000108U

Definition at line 1331 of file stm32_hal_legacy.h.

◆ JUMBO_FRAME_PAYLOAD

#define JUMBO_FRAME_PAYLOAD   ETH_JUMBO_FRAME_PAYLOAD

Definition at line 1323 of file stm32_hal_legacy.h.

◆ MACCR_CLEAR_MASK

#define MACCR_CLEAR_MASK   ETH_MACCR_CLEAR_MASK

Definition at line 1325 of file stm32_hal_legacy.h.

◆ MACFCR_CLEAR_MASK

#define MACFCR_CLEAR_MASK   ETH_MACFCR_CLEAR_MASK

Definition at line 1326 of file stm32_hal_legacy.h.

◆ MACMIIAR_CR_MASK

#define MACMIIAR_CR_MASK   ETH_MACMIIAR_CR_MASK

Definition at line 1324 of file stm32_hal_legacy.h.

◆ MAX_ETH_PAYLOAD

#define MAX_ETH_PAYLOAD   ETH_MAX_ETH_PAYLOAD

Definition at line 1322 of file stm32_hal_legacy.h.

◆ MIN_ETH_PAYLOAD

#define MIN_ETH_PAYLOAD   ETH_MIN_ETH_PAYLOAD

Definition at line 1321 of file stm32_hal_legacy.h.

◆ VLAN_TAG

#define VLAN_TAG   ETH_VLAN_TAG

Definition at line 1320 of file stm32_hal_legacy.h.