DIY Logging Volt/Ampmeter
SEGGER_RTT_Conf.h
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12 * SEGGER RTT * Real Time Transfer for embedded targets *
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45 File : SEGGER_RTT_Conf.h
46 Purpose : Implementation of SEGGER real-time transfer (RTT) which
47  allows real-time communication on targets which support
48  debugger memory accesses while the CPU is running.
49 Revision: $Rev: 21386 $
50 
51 */
52 
53 #ifndef SEGGER_RTT_CONF_H
54 #define SEGGER_RTT_CONF_H
55 
56 #ifdef __IAR_SYSTEMS_ICC__
57  #include <intrinsics.h>
58 #endif
59 
60 /*********************************************************************
61 *
62 * Defines, configurable
63 *
64 **********************************************************************
65 */
66 
67 //
68 // Take in and set to correct values for Cortex-A systems with CPU cache
69 //
70 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system
71 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached
72 //
73 // Most common case:
74 // Up-channel 0: RTT
75 // Up-channel 1: SystemView
76 //
77 #ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS
78  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3)
79 #endif
80 //
81 // Most common case:
82 // Down-channel 0: RTT
83 // Down-channel 1: SystemView
84 //
85 #ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
86  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3)
87 #endif
88 
89 #ifndef BUFFER_SIZE_UP
90  #define BUFFER_SIZE_UP (1024) // Size of the buffer for terminal output of target, up to host (Default: 1k)
91 #endif
92 
93 #ifndef BUFFER_SIZE_DOWN
94  #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
95 #endif
96 
97 #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
98  #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
99 #endif
100 
101 #ifndef SEGGER_RTT_MODE_DEFAULT
102  #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
103 #endif
104 
105 /*********************************************************************
106 *
107 * RTT memcpy configuration
108 *
109 * memcpy() is good for large amounts of data,
110 * but the overhead is big for small amounts, which are usually stored via RTT.
111 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
112 *
113 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
114 * This is may be required with memory access restrictions,
115 * such as on Cortex-A devices with MMU.
116 */
117 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP
118  #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
119 #endif
120 //
121 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
122 //
123 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
124 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes))
125 //#endif
126 
127 //
128 // Target is not allowed to perform other RTT operations while string still has not been stored completely.
129 // Otherwise we would probably end up with a mixed string in the buffer.
130 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
131 //
132 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
133 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
134 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
135 // (Higher priority = lower priority number)
136 // Default value for embOS: 128u
137 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
138 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
139 // or define SEGGER_RTT_LOCK() to completely disable interrupts.
140 //
141 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
142  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
143 #endif
144 
145 /*********************************************************************
146 *
147 * RTT lock configuration for SEGGER Embedded Studio,
148 * Rowley CrossStudio and GCC
149 */
150 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
151  #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
152  #define SEGGER_RTT_LOCK() { \
153  unsigned int _SEGGER_RTT__LockState; \
154  __asm volatile ("mrs %0, primask \n\t" \
155  "movs r1, #1 \n\t" \
156  "msr primask, r1 \n\t" \
157  : "=r" (_SEGGER_RTT__LockState) \
158  : \
159  : "r1", "cc" \
160  );
161 
162  #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
163  : \
164  : "r" (_SEGGER_RTT__LockState) \
165  : \
166  ); \
167  }
168  #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
169  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
170  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
171  #endif
172  #define SEGGER_RTT_LOCK() { \
173  unsigned int _SEGGER_RTT__LockState; \
174  __asm volatile ("mrs %0, basepri \n\t" \
175  "mov r1, %1 \n\t" \
176  "msr basepri, r1 \n\t" \
177  : "=r" (_SEGGER_RTT__LockState) \
178  : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
179  : "r1", "cc" \
180  );
181 
182  #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
183  : \
184  : "r" (_SEGGER_RTT__LockState) \
185  : \
186  ); \
187  }
188 
189  #elif defined(__ARM_ARCH_7A__)
190  #define SEGGER_RTT_LOCK() { \
191  unsigned int _SEGGER_RTT__LockState; \
192  __asm volatile ("mrs r1, CPSR \n\t" \
193  "mov %0, r1 \n\t" \
194  "orr r1, r1, #0xC0 \n\t" \
195  "msr CPSR_c, r1 \n\t" \
196  : "=r" (_SEGGER_RTT__LockState) \
197  : \
198  : "r1", "cc" \
199  );
200 
201  #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
202  "mrs r1, CPSR \n\t" \
203  "bic r1, r1, #0xC0 \n\t" \
204  "and r0, r0, #0xC0 \n\t" \
205  "orr r1, r1, r0 \n\t" \
206  "msr CPSR_c, r1 \n\t" \
207  : \
208  : "r" (_SEGGER_RTT__LockState) \
209  : "r0", "r1", "cc" \
210  ); \
211  }
212  #elif defined(__riscv) || defined(__riscv_xlen)
213  #define SEGGER_RTT_LOCK() { \
214  unsigned int _SEGGER_RTT__LockState; \
215  __asm volatile ("csrr %0, mstatus \n\t" \
216  "csrci mstatus, 8 \n\t" \
217  "andi %0, %0, 8 \n\t" \
218  : "=r" (_SEGGER_RTT__LockState) \
219  : \
220  : \
221  );
222 
223  #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \
224  "or %0, %0, a1 \n\t" \
225  "csrs mstatus, %0 \n\t" \
226  : \
227  : "r" (_SEGGER_RTT__LockState) \
228  : "a1" \
229  ); \
230  }
231  #else
232  #define SEGGER_RTT_LOCK()
233  #define SEGGER_RTT_UNLOCK()
234  #endif
235 #endif
236 
237 /*********************************************************************
238 *
239 * RTT lock configuration for IAR EWARM
240 */
241 #ifdef __ICCARM__
242  #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \
243  (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
244  #define SEGGER_RTT_LOCK() { \
245  unsigned int _SEGGER_RTT__LockState; \
246  _SEGGER_RTT__LockState = __get_PRIMASK(); \
247  __set_PRIMASK(1);
248 
249  #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
250  }
251  #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \
252  (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \
253  (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \
254  (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
255  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
256  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
257  #endif
258  #define SEGGER_RTT_LOCK() { \
259  unsigned int _SEGGER_RTT__LockState; \
260  _SEGGER_RTT__LockState = __get_BASEPRI(); \
261  __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
262 
263  #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \
264  }
265  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \
266  (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
267  #define SEGGER_RTT_LOCK() { \
268  unsigned int _SEGGER_RTT__LockState; \
269  __asm volatile ("mrs r1, CPSR \n\t" \
270  "mov %0, r1 \n\t" \
271  "orr r1, r1, #0xC0 \n\t" \
272  "msr CPSR_c, r1 \n\t" \
273  : "=r" (_SEGGER_RTT__LockState) \
274  : \
275  : "r1", "cc" \
276  );
277 
278  #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
279  "mrs r1, CPSR \n\t" \
280  "bic r1, r1, #0xC0 \n\t" \
281  "and r0, r0, #0xC0 \n\t" \
282  "orr r1, r1, r0 \n\t" \
283  "msr CPSR_c, r1 \n\t" \
284  : \
285  : "r" (_SEGGER_RTT__LockState) \
286  : "r0", "r1", "cc" \
287  ); \
288  }
289  #endif
290 #endif
291 
292 /*********************************************************************
293 *
294 * RTT lock configuration for IAR RX
295 */
296 #ifdef __ICCRX__
297  #define SEGGER_RTT_LOCK() { \
298  unsigned long _SEGGER_RTT__LockState; \
299  _SEGGER_RTT__LockState = __get_interrupt_state(); \
300  __disable_interrupt();
301 
302  #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
303  }
304 #endif
305 
306 /*********************************************************************
307 *
308 * RTT lock configuration for IAR RL78
309 */
310 #ifdef __ICCRL78__
311  #define SEGGER_RTT_LOCK() { \
312  __istate_t _SEGGER_RTT__LockState; \
313  _SEGGER_RTT__LockState = __get_interrupt_state(); \
314  __disable_interrupt();
315 
316  #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
317  }
318 #endif
319 
320 /*********************************************************************
321 *
322 * RTT lock configuration for KEIL ARM
323 */
324 #ifdef __CC_ARM
325  #if (defined __TARGET_ARCH_6S_M)
326  #define SEGGER_RTT_LOCK() { \
327  unsigned int _SEGGER_RTT__LockState; \
328  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \
329  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \
330  _SEGGER_RTT__PRIMASK = 1u; \
331  __schedule_barrier();
332 
333  #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \
334  __schedule_barrier(); \
335  }
336  #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
337  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
338  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
339  #endif
340  #define SEGGER_RTT_LOCK() { \
341  unsigned int _SEGGER_RTT__LockState; \
342  register unsigned char BASEPRI __asm( "basepri"); \
343  _SEGGER_RTT__LockState = BASEPRI; \
344  BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
345  __schedule_barrier();
346 
347  #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \
348  __schedule_barrier(); \
349  }
350  #endif
351 #endif
352 
353 /*********************************************************************
354 *
355 * RTT lock configuration for TI ARM
356 */
357 #ifdef __TI_ARM__
358  #if defined (__TI_ARM_V6M0__)
359  #define SEGGER_RTT_LOCK() { \
360  unsigned int _SEGGER_RTT__LockState; \
361  _SEGGER_RTT__LockState = __get_PRIMASK(); \
362  __set_PRIMASK(1);
363 
364  #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
365  }
366  #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
367  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
368  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
369  #endif
370  #define SEGGER_RTT_LOCK() { \
371  unsigned int _SEGGER_RTT__LockState; \
372  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
373 
374  #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \
375  }
376  #endif
377 #endif
378 
379 /*********************************************************************
380 *
381 * RTT lock configuration for CCRX
382 */
383 #ifdef __RX
384  #include <machine.h>
385  #define SEGGER_RTT_LOCK() { \
386  unsigned long _SEGGER_RTT__LockState; \
387  _SEGGER_RTT__LockState = get_psw() & 0x010000; \
388  clrpsw_i();
389 
390  #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \
391  }
392 #endif
393 
394 /*********************************************************************
395 *
396 * RTT lock configuration for embOS Simulation on Windows
397 * (Can also be used for generic RTT locking with embOS)
398 */
399 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
400 
401 void OS_SIM_EnterCriticalSection(void);
402 void OS_SIM_LeaveCriticalSection(void);
403 
404 #define SEGGER_RTT_LOCK() { \
405  OS_SIM_EnterCriticalSection();
406 
407 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \
408  }
409 #endif
410 
411 /*********************************************************************
412 *
413 * RTT lock configuration fallback
414 */
415 #ifndef SEGGER_RTT_LOCK
416  #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
417 #endif
418 
419 #ifndef SEGGER_RTT_UNLOCK
420  #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
421 #endif
422 
423 #endif
424 /*************************** End of file ****************************/